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1430 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 3, MARCH 2012

DC Link Active Power Filter forThree-Phase Diode Rectifier

Xiong Du, Luowei Zhou, Senior Member, IEEE , Hao Lu, and Heng-Ming Tai, Senior Member, IEEE

Abstract—In this paper, a dc link active power filter (APF) forthree-phase diode rectifier is proposed. The proposed dc link APF,which is composed of two series-connected bidirectional boostconverters, intends to eliminate the input current harmonics. It isparalleled at the dc link of the diode rectifier and is coupled to theac input with three line-frequency switches. Compared with thefull power processed power factor correction (PFC) solution, thedc link APF is partially power processed in that it only compen-sates for the harmonic current component at the dc link. Thus, itfeatures with lower power processing. Moreover, it exhibits bettertotal harmonic distortion of the ac line current when comparedwith the traditional ac side shunt APF. Voltage and current loop

models are developed for average current control, and the selectionof the current loop bandwidth is presented. Switching stressesof the ac APF, the dc link APF, and the six-switch PFC arealso calculated and analyzed. Experimental and simulation resultsdemonstrate the effectiveness of this dc link APF.

Index Terms—Active power filter (APF), bandwidth, compensa-tion performance, diode rectifier, power factor correction (PFC).

I. INTRODUCTION

HARMONIC current pollution generated by nonlinearloads is a serious problem in power systems. Numerous

harmonic standards have been put forward on this issue, forexample, IEEE and IEC standards [1]. Since three-phase dioderectifiers are widely used in industry, such as adjustable speeddrives and dc power supplies [2]–[4], the harmonics generatedby the diode rectifier in the line current is a main concern inpower electronics. To eliminate the harmonic current generatedby this type of harmonic source, the shunt active power filter(APF) or series APF has been an effective solution [5]–[11].However, the rating of APF is normally small because of itspartial power processing property. Hence, it generally featureswith low cost and small volume. Shunt APF’s are usually paral-leled at the ac side. Therefore, both the voltage and the current

Manuscript received September 26, 2010; revised January 24, 2011,

April 26, 2011, and July 23, 2011; accepted August 15, 2011. Date of pub-lication September 6, 2011; date of current version October 25, 2011. Thiswork was supported in part by Foundation for the Author of National ExcellentDoctoral Dissertation of China under Grant 200948, in part by the Programfor New Century Excellent Talents in University under Grant NCET-09-0839,in part by the National 111 Project of China under Grant B08036, and in partby Scientific Research Foundation of State Key Lab of Power TransmissionEquipment and System Security under Grant 2007DA10512711101.

X. Du, L. Zhou, and H. Lu are with the State Key Laboratory of Power Trans-mission Equipment and System Security and New Technology, and the Collegeof Electrical Engineering, Chongqing University, Chongqing 400044, China(e-mail: [email protected]; [email protected]; [email protected]).

H.-M. Tai is with the Department of Electrical Engineering, University of Tulsa, Tulsa, OK 74104 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2167112

processed by APF are with alternating values. We name thetraditional shunt APF, the ac side APF thereafter, to distinguishwith the dc link APF to be studied in this paper.

A four-quadrant inverter is commonly used in the powerstage of the ac side APF, and an ac side APF always needscomplicated harmonic current detection and control. On theother hand, the three-phase power factor correction (PFC),which is a full power processing solution, has been exten-sively studied [12]–[19]. The most popular topology of thethree-phase PFC is a six-switch bridge. This type of PFC has

the feature of bidirectional power flowing capability. In somespecific applications, unidirectional PFC topologies such asthe Vienna converter [15], [16] and the series connected dual-boost converter [19], [20] are considered. Both bidirectionaland unidirectional three-phase PFCs are required to process allthe load power. Thus, most of them suffer from higher siliconcost as compared with the APF solutions which require onlypartial power processing. Multipulse rectifiers, which employlow frequency phase shift transformer to synthesize reasonableline current waveform, are also reported for the reduction of thesilicon cost [17], [18]. Due to the application of low frequencytransformer, the volume is a critical limitation.

For three-phase diode rectifiers, low cost harmonic elimi-

nation methods, which adopt a few passive or active compo-nents to inject triple-order harmonic currents at the dc link of the three-phase diode rectifier for line current correction andharmonic injection, have been reported [21]–[27]. The circuitpresented in [21] is a series connected dual-boost converterwith tuned LC filter which functions as a third order harmoniccurrent injection network. Later, the tuned LC filter is replacedwith a low frequency zigzag connected transformer so that theparameter variation effect of the LC filter can be avoided [22].The active switches in these two topologies need to processall the output power at high switching frequency while theLC filter suffers from parameter sensitivity, and low frequency

zigzag transformer still appears large volume. To eliminateactive switches, passive harmonic current injection circuits,which combine separate LC filter and low frequency star-delta transformer, have been proposed [23]–[25]. Similar to thecircuits in [21], [22], these circuits still experience parametersensitivity and large volume. To dodge the parameter sensitivityeffect of the passive filter network in [23]–[25], a compact highfrequency active current shaping network has been developedto replace the passive filter, and three ac switches are employedto take place of the bulky low frequency transformer [26].However, the line current would not be proportional to the linevoltage theoretically because of only one current variable beingcontrolled instantaneously. This is because two independent

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DU et al.: DC LINK ACTIVE POWER FILTER FOR THREE-PHASE DIODE RECTIFIER 1431

phase currents are present in the three-phase three-wire system.Hence, the line current performance is limited and the linecurrent total harmonic distortion (THD) is high. With the sameactive current shaping network, the ac switches are replacedwith star-delta transformer for cost reduction [27]. As reportedin [26], the performance of this harmonic current injection

method is not acceptable because the line current THD is stillaround 8.5%.In this paper, we propose a dc link APF for three-phase diode

rectifiers. Although the dc link filter for a single phase rec-tifier has been studied [28], [29], extension to the three phaseis not straightforward and requires new topology and controlstrategy. The dc link APF studied in this paper differs fromthe active dc filter in HVDC [30] in terms of the connectionstructure and the function. The active dc filter is connected atthe bottom of an existing passive dc filter at the rectifier station.It is mainly used to reduce the dc current ripples and to increasethe dynamic response of the dc current ripple filter [30]. On theother hand, the dc link APF is connected in parallel at the dcterminal of the diode rectifier and coupled with the ac input.Its main function is to suppress the line side input current, notto regulate the dc link performance. The proposed topologyconsists of two series-connected bidirectional boost converters,which function as harmonic current generators to compensatefor the phase currents to be in phase with the correspondingline voltages, not just triple current injection as in [21]–[27].Moreover, three line-frequency ac switches decouple the three-phase circuit to the two-phase circuit to simplify the controleffort. Compensation performance of this three-phase dc linkAPF is analyzed and is evaluated under limited switchingfrequency and limited current loop bandwidth. The current

loop bandwidth selection is presented based on the frequencydomain evaluation. In addition, the voltage loop and currentloop models are developed for the control design, and switchingstress is calculated and analyzed. Performance comparison withthe ac side APF and three-phase PFC is also conducted. Sim-ulation results and experimental results measured from a DSP-controlled prototype are presented to verify the performance of the proposed dc link APF.

II. PROPOSED DC L IN K ACTIVE POWER F ILTER

Consider a three-phase diode rectifier with a dc load as

shown in Fig. 1. The dc load is modeled with a simple RLload. It can be justified even under the output capacitor filtercondition in that an inductor is usually placed in front of the capacitor to smooth the dc link current. If there is noother mechanism to improve the input current quality of thediode rectifier, the input line currents are polluted with seriesharmonic components. To alleviate the harmonic pollution, adc link APF is proposed. This dc link APF is coupled to theac input with three ac switches working at line frequency andconnected to the load, as shown in Fig. 1. It consists of twoseries-connected bidirectional boost converters, which containpositive part components L p, S p1, S p2, C p and negative partcomponents Ln, S n1, S n2, C n.

The operation principle of the dc link APF can be examinedas the series connected dual-boost three-phase PFC [19], [20].

Fig. 1. Schematic of proposed dc link active power filter for three-phase dioderectifier.

Fig. 2. Line period division and ac switches conduction states.

Fig. 3. Equivalent circuit for the interval I.

The input line voltages are divided into six intervals, I–VI, asshown in Fig. 2. In each interval, only one ac switch conducts.For example, in interval I, S b conducts while S a and S care off. The dc link APF is simplified to a series-conductedbidirectional boost converter. Fig. 3 shows the equivalent circuitof the dc link APF for interval I.

The dc link currents have correspondence with the ac inputcurrents. Distinct interval produces different correspondence.For example, the currents i p, im, in are ia, ib, and ic, respec-tively, in interval I. The input voltage v pm of the positive boostconverter is equal to vab, so is the voltage vmn of the negative

boost converter equal to vbc. The dc load is modeled with aconstant dc current source.

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If the line current ix can be controlled in proportion to thecorresponding line voltage in each interval such as

ix = vxRe

(1)

where x = p, m, n, v p, vm, vn are the voltages between node

p, m, n and node o in Fig. 1, Re is the equivalent phase resis-tance. Then, the line currents also hold the same proportionalityto the corresponding line voltages [19], [20],1 i.e.,

iy = vyRe

(2)

where y = a,b,c. v p and vn are the positive and negativeenvelopes of the line voltages, and vm is the complementvoltage

v p = Max(va, vb, vc) (3)

vn = Min(va, vb, vc) (4)

vm = va + vb + vc − v p − vn. (5)

In the steady state, the dc voltages of the capacitors areassumed to be equal

vcp = vcn (6)

and their dc component is V c. Due to the equivalent series-connected boost converter topology, the complementary highfrequency switches S p1, S p2 and S n1, S n2 can be controlled toregulate the dc rail current i p and in, respectively, to satisfy therelationship (1).

When S p1 is on and S p2 is off, the voltage across the inductor

L p is positive, i.e.,vLp = v pm > 0. (7)

Then the inductor current iLp will increase. When S p1 is off and S p2 is on, the voltage across L p is negative

vLp = v pm − vcp < 0. (8)

The inductor current iLp decreases. This current regulationprocess also can be applied to the negative part boost topology.

Typical operation waveforms of the dc link APF rectifierare shown in Fig. 4 under the symmetrical sinusoidal inputcondition. The voltages and currents are drawn with p.u. values.The voltage base is the amplitude value of the phase voltage,and the current base is the dc load current which is assumedto be constant dc with 50 Hz line frequency. The top panelillustrates the voltages v pm and vnm of the positive part andnegative part boost converter, respectively. The middle paneldisplays the current waveforms in the positive boost converter.Those in the negative part have similar waveforms and are notshown. The bottom panel exhibits the input phase voltage andthe line current of phase a. From Fourier analysis of the line

1Equations (1) and (2) are based on the three-phase voltages without zero-sequence component. If the zero-sequence voltage exists in the line voltage,

then vx should be changed to v

x = vx−

(vp + vm + vn)/3, and vy shouldbe changed to v

y = vy − (va + vb + vc)/3 because the zero-sequence cur-rent does not exist in the three-phase three-wire system.

Fig. 4. Typical operation waveforms of the proposed dc link APF.

current of a three-phase diode rectifier with inductive load, thephase current amplitude can be obtained by

I m = 2√ 3

π p.u. (9)

This indicates the quantitative relationship of the currentsshown in the middle panel in Fig. 4. As can be seen from Fig. 4,the current processed by the dc link APF is just part of the loadcurrent. This situation enables the reduction of power rating,like the traditional ac side APF. However, the compensationperformance of the dc link APF is much better than that of thetraditional ac side APF, which will be described in Section IV.

III. CONTROL OF

DC LIN K

APF A. Control Structure

Average current control [31] is employed to control thedc link APF for digital implementation. The input voltage feed-forward [32] is also adopted here to eliminate the input voltageeffect to the current loop. Fig. 5 shows the block diagram of theoverall current control, which consists of one outer voltage loopand two inner current loops. V m is the amplitude of the carriersignal, which is the signal employed in the sine-triangle PWMto generate duty ratios.

The sum of the voltages from the two dc capacitors iscompared with a dc voltage reference U ref . The difference is

fed to the voltage loop compensator, a PI controller P I 1 toobtain the equivalent phase conductance ge. Multiplying ge to

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Fig. 5. Average current control with input voltage feedforward.

the respective line voltage yields the reference currents of thepositive part and the negative part boost converter

i pref = ge · v p (10)

inref = ge · vn. (11)

The reference currents i pref and inref are compared with thesensed dc rail currents i p and in, respectively. The differencesare fed to the inner current loop compensators Gc, whichconsists of two PI controllers P I 2 and P I 3. The output of the current compensator determines the duty ratios through thePWM circuits. d p and dn are, respectively, the duty ratios of theswitches S p1 and S n1. Moreover, the duty ratios of switches S p2and S n2 are (1 − d p) and (1 − dn), respectively. The dashedline indicates the input voltage feedforward that eliminates theinput voltage coupling effect.

The control structure is similar to that of the typical single-phase PFC [33]. The difference lies in that the inductor currentin the single-phase PFC is controlled directly by the duty ratio

of the PFC switch, whereas the inductor currents are controlledindirectly by the duty ratios d p and dn in the proposed structure.Models of the voltage loop and the current loop are discussedbelow.

B. Voltage Loop Model

As in the conventional cascaded loop control, the bandwidthof the outer voltage loop is much smaller than that of theinner current loop. Hence, dynamics of the current loop (e.g.,inductor current) can be ignored when modeling the voltageloop. Double averaging method [33] is applied to obtain a

simple first-order power stage voltage model with small signallinearization. From Fig. 3 and according to power balance,we have

v pm(i p − iLoad) + vmn(−in − iLoad)

= C vcpdvcp

dt + Cvcn

dvcndt

(12)

where vcp and vcn are voltage across the capacitors C p and C n,respectively. All the time variables in (12) represent the valuesaveraged in one switching period. Averaging (12) for one thirdof the line period yields

3V 2 p2

ge − 3√ 3V pI loadπ

= C V cd(vcp + vcn)

dt (13)

Fig. 6. Voltage loop model.

where V p is the amplitude of the phase voltage, and C isthe capacitance under symmetrical conditions, C p = C n = C .Consider the perturbation on ge and vcp + vcn, and neglect theperturbation of I load, we obtain the transfer function

Gve(s) = vcp(s) + vcn(s)

ge(s) =

3V 2 p2CV cs

. (14)

The voltage loop model is shown in Fig. 6, in which H v(s) isthe voltage sensing scale for practical implementation. Gv(s)is the voltage compensator transfer function, represented by atraditional PI controller.

C. Current Loop Model

In each interval shown in Fig. 2, the equivalent circuit inFig. 3 has symmetric structure. Thus, the current loop can beanalyzed in either the positive part or the negative part boostconverter. The positive part is selected here. When analyzingthe fast current loop, the voltage dynamics can be approximatedby a simple constant dc voltage source. Then, the output of thevoltage loop is treated as a constant admittance Ge. The currentloop modeling method in [34] is applied to obtain the currentloop model shown in Fig. 7 with leading edge modulation. Thedashed-line represents the input voltage feedforward. Without

the input voltage feedforward, the inductor current can bederived as

I Lp(s) =Gc(s) V c

V m

1sLp

1 + Gc(s) V cV m

1sLp

[I pref (s) − I Load(s)]

+

1sLp

1 + Gc(s) V cV m

1sLp

V pm(s)

=Gc(s) V c

V m

sL p + Gc(s) V cV m

[I pref (s) − I Load(s)]

+ V pm(s)sL p + Gc(s) V c

V m

.

This shows that the inductor current response is coupled withthe input voltage. Adding the feedforward part to the currentloop, the inductor current becomes

I Lp(s) =V cV m

Gc(s) [I pref (s) − I Load(s)]

sL p + V cV m

Gc(s). (15)

The input voltage coupling is eliminated through the voltagefeedforward.

Control design is straightforward because both the voltage

model and the current model are simple first-order models.The simple PI controller can be tuned to meet the control

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Fig. 7. Current loop model.

objectives [35]. The main concern becomes the determinationof the frequency bandwidth of the voltage loop and the currentloop. Since each loop has its own control target, the voltageloop bandwidth should be set smaller than the lowest ordervoltage ripple in the dc bus voltage. In addition, the currentloop bandwidth is required to be as high as possible to improve

the current compensation performance. Generally, the currentloop bandwidth is limited to 1/5 to 1/10 of the switchingfrequency [31].

Regarding the compensation performance of dc link APF, itis desired to have higher current loop bandwidth with higherswitching frequency. On the other hand, lower current loopbandwidth with smaller switching frequency is recommendedto account for the device switching frequency and the efficiency.The criterion for the selection of current loop bandwidth will bepresented in the next section.

IV. COMPENSATION PERFORMANCE EVALUATION

This section describes the relationship between the com-pensation performance and the current loop bandwidth of theproposed dc link APF and evaluates the compensation perfor-mances of the dc link APF and the traditional ac side APF.Both APFs have the following characteristics on compensationperformance.

1) If the current harmonic components in the line currentcould be neglected with infinite current loop bandwidth,then the THD of the line current is assumed zero for thedc link and the ac side APF.

2) For finite current loop bandwidth, only the frequency

components with harmonic orders smaller than the band-width will be compensated.

3) The switching frequency related current ripples are ig-nored because these harmonics are easy to be filteredout and usually are much higher than the harmonic orderspecified by the standards.

The line current in ac side APF still contains the currentharmonics with frequencies higher than the current loop band-width, and these high frequency components directly affect theline current THD. In contrast, for dc link APF, the compensatedharmonics with frequency less than the current loop bandwidthwill appear in the dc rail currents (i p and in) to form the

desired current waveforms (as shown in the middle panel of Fig. 4). That is, due to the finite current loop bandwidth, the

compensated positive part inductor current contains only finitenumber of harmonics and can be expressed as

iLp(t) =N

n=0

I Lpn cos nωt. (16)

where values of n are the integer multiples of 3 and ω is the fun-damental frequency. N is the largest harmonic order of whichthe frequency is smaller than the current loop bandwidth. Therelationship between the harmonic components in the dc railcurrents i p, in and the ac line current will be developed below.This relationship will be applied to quantify the bandwidtheffect for compensation performance on dc link APF.

Assume the line voltage has symmetrical sinusoidal wave-form. A switch function S fa(t) for phase a, shown in Fig. 8,is introduced to establish the time domain relationship betweenthe dc rail currents and the line current. The switch functionS fa(t) is given by

S fa(t) =

0 −

T 2 < t ≤ −

T 6

1 −T 6

< t ≤ T 6

0 T 6

< t ≤ T 2 .

(17)

T is the line period. Then, the line current can be expressed interms of the dc rail currents and the switch function

ia(t) = i p(t)S fa(t) + in(t)S fa

t − T

2

−

1 − S fa(t) − S fa

t − T

2

· [i p(t) + in(t)] (18)

or

ia(t) =

2S fa(t) + S fa

t − T

2

− 1

i p(t)

+

2S fa

t − T

2

+ S fa(t) − 1

in(t). (19)

Under symmetrical conditions, the dc rail currents have thefollowing relationship:

in(t) = −i p

t − T

2

. (20)

Define a new switch function

S (t) = 2S fa(t) + S fa

t − T

2

− 1. (21)

Substituting (20) and (21) into (18) yields

ia(t) = i p(t)S (t) − i p

t − T

2

S

t − T

2

. (22)

The line current harmonic components can be calculated viathe frequency components of i p(t) and S (t) by the convolutionmethods.

Ideally, i p(t) is periodic with period T /3. Thus, in oneperiod, i p(t) has the following expression:

i p(t) = I m cos(ωt), −T

6 ≤ t ≤ T

6 . (23)

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Fig. 8. Switch function S fa (t).

Its Fourier series expansion is

i p(t) =

∞n=−∞

I pnejnωt (24)

where

I pn = 3√

3

2π

(

−1)

n3 +1 1

n2

− 1

I m (25)

and values of n are multiples of 3. The switch function S (t)can be expressed with harmonic decomposition

S (t) =

∞n=−∞

S nejnωt

=

∞n=−∞

2

nπ sin

nπ

3

1 − cos

nπ

3

ejnωt. (26)

Values of n that are multiples of 3 cause S n to become zero.Thus, no multiples of a third harmonic may exist in S (t).

From the property of Fourier expansion for periodic functions,we have

i p

t − T

2

=

∞n=−∞

(−1)nI pnejnωt (27)

S

t − T

2

=

∞n=−∞

(−1)nS nejnωt. (28)

Substituting (23)–(28) into (22) yields the line current

ia(t) =h

C h cos(hωt). (29)

The coefficient C h is

C h =+∞l=−∞

4I plS h−l (30)

or

C h = 4I m

∞l=−∞

3√

3

2π (−1)

l3+1 1

l2 − 1

×

2

(h − l)π sin

(h − l)π

3

1 − cos

(h − l)π

3

(31)

where values of l are multiples of 3, h is odd and h = l. l is theharmonic order of i p(t). When the current loop bandwidth is

infinite, both l and h extend to infinity. Suppose that the currentloop bandwidth is limited to N times of the fundamental linefrequency, the lower bound and upper bound in the summationof (31) becomes −N and N , respectively. It follows from(30) that we obtain the relationship between the harmoniccomponents of the line current and that of the dc rail currents.

Next, we evaluate the line current performance under specificcurrent loop bandwidth using the relationship (30) and (31).Ideally, the line current can be compensated by the dc link

APF to harmonic free with infinite switching frequency. How-ever, this is not the case in reality. Suppose that the currentloop bandwidth is limited to the N times of the fundamentalline frequency. Since the harmonic standard only considers theharmonics up to the 50th order, the line current T HDdc by thedc link APF can be calculated as

T HDdc =

50h=5 C 2h

C 1(32)

C h is the hth harmonics from (31). Similarly, the line currentT HDac by the ac side APF can be expressed as

T HDac =

50h=N +1 H 2h

H 1(33)

where the coefficient

H h = 2

hπ sin

hπ

3

· (1 − cos(hπ)) (34)

is the amplitude of the hth harmonics [36]. It can be seen from(32) and (33) that the harmonic components in the line current

of the ac side APF start at N + 1, whereas the harmonics startsat 5 for the dc link APF. This is because the line current of the dc link APF contains only the (6k ± 1)th harmonics, wherek is the positive integer.

Table I lists the line current THD for both dc link APF andac side APF under various current loop bandwidths. It showsthat under the same current loop bandwidth, compensation per-formance of the dc link APF is much better than that of the acside APF. THD of the dc link APF is less than 0.5% with 1 kHzor higher current loop bandwidth, and further improvement of THD by increasing the bandwidth is not significant. Therefore,the current loop bandwidth of the dc link APF can be set in therange of 1 kHz to 2 kHz for the line frequency of 50 Hz in thepractical implementation. Selection of the switching frequencyin the order of ten thousand Hz is reasonable and in goodagreement with the commercial IGBT power devices. Fig. 9shows the compensated phase current waveforms by the ac sideAPF and the dc link APF with 1050 Hz current loop bandwidth.

V. SWITCHING STRESS ANALYSIS

The total active switching stress of switching power convert-ers is a key measure that determines the converter cost andefficiency [37]. This section provides the evaluation of the totalactive switching stress of the proposed dc link APF, the six-

switch three-phase PFC, and the traditional shunt six-switchthree-phase APF. The results will be used to gauge the silicon

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TABLE ICOMPARISON OF COMPENSATION PERFORMANCE UNDER

DIFFERENT CURRENT LOOP BANDWIDTH

Fig. 9. Compensated phase a current. (a) ac side APF. (b) dc link APF.

cost and efficiency indirectly. The total switching stress S S isdefined in [37] as

SS =K j=1

V jI j (35)

where K is the number of switches in the converter, V j is thevoltage stress (peak voltage), and I j the current stress (rmscurrent) applied to active semiconductor switch j .

Comparison is based on the conditions that these circuittopologies have the same line voltages and the same outputpower and work in the same switching frequency. In addition,the line currents are assumed to be purely sinusoidal, and theswitching frequency related harmonics are ignored. Thus, theline currents of these three circuits are also the same.

Both of the six-switch three-phase PFC and APF are assumedto work at bipolar conditions with independent phase currentcontrol. There are six high frequency switches each in these

two topologies, whereas the dc link APF consists of fourhigh frequency switches and three low frequency ac switches.

TABLE IICOMPARISON OF SWITCHING STRESS

TABLE IIIPARAMETERS OF PASSIVE COMPONENTS

Therefore, the switching stress of dc link APF is composed of both the high frequency switching stress and the low frequencyswitching stress.

The voltage stresses of all the high frequency switches areequal to their own dc bus voltage. For fair comparison, the samemodulation ratio M is selected for all circuits. To avoid thenonlinearity of the modulation, M should be less than or equalto 1. In the following, M is selected as one for simplicity of theanalysis.

In a six-switch APF or PFC, the minimum dc bus voltage istwo times the amplitude of the phase voltage. Using the p.u.unit and modulation ratio M = 1, the dc bus voltage V dc has a

value of 2. Thus, the voltage stresses of both PFC and ac APFare 2 p.u. The peak input voltage of the dual boost circuit inFig. 3 is 3/2, as observed from the waveforms in Fig. 4. Due toM = 1, the dc bus voltage is 3/2. This implies that the voltagestress of the high frequency switches in the dc link APF is also3/2. It is also true for the low frequency ac switches.

The input/output voltage relationship with the duty ratio of down switch at each phase for the three-phase PFC can beexpressed as [38]

dan = 1

2 − va

V dc(36)

where dan is the duty ratio of the down switch in phase a.Moreover, the duty ratio dap of the up switch in phase a is

dap = 1 − dan = 1

2 +

vaV dc

. (37)

Then, the current stress of phase a in the three-phase PFC canbe calculated as [37]

I ap =

1

T

T 0

i2a(t)dapdt (38)

I an =

1T

T 0

i2a(t)dandt (39)

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Fig. 10. Simulated steady-state response with inductive load. (a) dc link APF OFF. (b) dc link APF ON. (c) Current waveforms of positive boost converter.(d) dc bus voltages.

where T is the line period. From the three-phase symmetry,the current stress for other two phases will have the samevalue.

Similar arguments can be applied to the three-phase ac APF.The duty ratios of the down and up switches in phase a have thesame expression as those of three-phase PFC. Since the current

processed by the inverter is the difference between the loadcurrent and the line current, the current stress of phase a canbe calculated as

I ap =

1

T

T 0

i2La(t)dapdt (40)

I an =

1

T

T 0

i2La(t)dandt (41)

where iLa is the inductor current in phase a.

The same process can be applied to calculate the high fre-quency current stress in the dc link APF, where the duty ratio

of the high frequency switches S p1 and S n1 in the dc link APFcan be expressed as, respectively,

d p = 1 − v pmV c

(42)

dn = 1

− vmn

V c. (43)

The inductor currents iLp and iLn are used to calculate thecurrent stress. For the low frequency ac switches, the currentsflowing through them are portion of the line currents. Theircurrent stresses can be calculated based on the rms definitiondirectly and, thus, independent of the duty ratio.

Table II summarizes the values of switching stress for the six-switch PFC, the six-switch APF, and the dc link APF obtainedfrom the voltage and current stress calculation discussed above.As shown in Table II, the six-switch PFC has the highest totalswitching stress. Its value is nearly three times that of theac APF and two times that of the dc link APF. The higher

total switching stress of the dc link APF than the ac APF ismainly due to the fact that portion of the line current flows

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through the ac switch and incurs higher conduction loss in thedc link APF. However, the high frequency switching stress of the dc link APF is about one-third that of the ac APF. Thisfeature will enable the dc link APF to work more efficientlyin that the high frequency switching loss usually dominatesthe total loss in the switching power converter [37]. The result

demonstrates the silicon cost reduction property of the dclink APF.

VI. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Studies

Simulations were carried out to examine the performanceof the dc link APF to complement the experimental results.Three cases are investigated. They are: 1) the steady-stateresponse; and 2) the transient response with inductive load; and3) steady-state response with capacitive load. The parametersused include the line frequency f = 50 Hz, line-line RMSvoltage 380 V, L p = Ln = 4 mH, C p = C n = 500 µF, V cp =V cn = 550 V, and the switching frequency is 20 kHz. Inductivedc load is a RL load where R = 20 Ω and L = 100 mH.Capacitive load is a RC load, where C = 200 µF, R = 20 Ω,and a 5 mH inductor is inserted before the RC load to smooththe dc load current. The parameters of the passive componentsin real value and in p.u. value are summarized in Table III. Theimpedance base is the value of the load resistor 20 Ω.

Simulation results of the steady-state response with inductiveload are shown in Fig. 10. Fig. 10(a) and (b) show the sourcecurrent waveforms and the load voltage and current waveformswhen the dc link APF is OFF and ON, respectively. Fig. 10(c)

shows the current of the positive part boost converter. Thedc bus voltage waveforms are shown in Fig. 10(d). THD of the source current was 30.84% without compensation and wasreduced to 3.34% with compensation of the proposed dc linkAPF. It is observed from Fig. 10(a) and (b) that both the loadvoltage waveform and current waveform are nearly the samewith or without the dc link APF. This is in agreement withthe performance of the shunt ac APF; that is, APF does notaffect the performance of load voltage and load current. The dccomponent of the load current is 25.66 A, and the peak-peak300 Hz current ripple is about 0.3 A. This dc value is very closeto the dc component of the load, 25.72 A, of an ideal three-

phase diode rectifier loaded by a pure resistor. It is observedfrom Fig. 10(c) that the dc component of i p is 23.40 A, whichis also the same as the calculated value. The dc voltage sumof the split capacitors is 1100 V, which is equal to the referencevoltage. The peak-peak voltage ripple of each capacitor is about7 V with 150 Hz frequency, but the peak-peak ripple of thesum of these two capacitors is reduced to about 3 V and thefrequency is 300 Hz. This is due to the nearly 180 phase shiftbetween vcp and vcn, which leads to harmonic cancellation.Hence, we select (vcp + vcn) as the feedback signal in thevoltage loop of Fig. 6 because of the low ripple factor.

The transient response under dc load resistor change andsource voltage change is shown in Fig. 11. Fig. 11(a) displays

the response when the dc load resistor changes from 20 Ω to40 Ω at the time instance of 0.4 s and changed back to 20 Ω at

Fig. 11. Simulated transient responses with inductive load. (a) Load changefrom 20 Ω to 40 Ω at 0.4s and changed back to 20 Ω at 0.5 s. (b) Source voltagedrop 30% at 0.4 s and return to the rated value at 0.5 s.

0.5 s. Fig. 11(b) displays the response under the circumstancethat source voltage has a 30% voltage drop at 0.4 s and returnto the rated value at 0.5 s. These results of load change andsource voltage change examine the transient performance of thecontrol design discussed in Section III.

The voltage loop bandwidth affects the dynamic perfor-mance. The transient response can be improved by setting thevoltage loop bandwidth higher, as illustrated in Fig. 12. In thesimulations, the dc load resistor changes from 20 Ω to 40 Ω atthe time instance of 0.3 s and changes back to 20 Ω at 0.5 s.

The results shown in Fig. 12(a) and (b) are for the 15 Hz andthe 60 Hz voltage loop bandwidth, respectively. It is observedfrom Fig. 12(a) that the overshoot of dc voltage is about 90 Vand the settling time is about 150 ms. On the other hand, theovershoot is about 20 V, and the settling time is about 20 ms forthe 60 Hz voltage loop bandwidth. This demonstrates that thedynamical performance can be improved with higher voltageloop bandwidth.

The diode rectifier with a capacitive load was also investi-gated. The results are presented in Fig. 13. The line currentafter compensation is 8.1%, which is much higher than thatin the inductive condition. The reason is that the shunt APF ismore suitable for compensating inductive load and current type

harmonic source, but not for the capacitive load or voltage typeharmonic source [39].

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Fig. 12. Load transient simulation results. (a) With 15 Hz voltage loopbandwidth. (b) With 60 Hz voltage loop bandwidth.

Fig. 13. Steady-state response with capacitive load.

Fig. 14. Experimental results with current loop bandwidth of 1 kHz. (a) dc

link APF OFF; (b) dc link APF ON; and (c) current waveforms of the positiveboost converter.

B. Experimental Results

A 2 kW prototype was constructed in the lab to verifythe performance of the proposed dc link APF. Most of theparameters used in the experiment are the same as in thesimulation study, except that the dc load is a RL load withR = 110 Ω and L = 0.5 mH. The ac switch is implementedby MOSFET IRFP460 and the high frequency switch by IGBTPM75DSA120. The current is sensed by the LEM HX20-Pcurrent sensor. Digital controller is realized by the FreescaleDSP chip MC56F8323.

Experimental results with 1 kHz current loop bandwidth areshown in Fig. 14. Fig. 14(a) displays the current waveforms

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Fig. 15. Experimental results with 2 kHz current loop bandwidth.

when dc link APF is not functioning, and Fig. 14(b) exhibits thewaveforms when the dc link APF is working. Fig. 14(c) showsthe current waveforms of the positive part boost converter.These current waveforms agree with those currents shown inthe middle panel of Fig. 4. The current iLp processed by thedc link APF is just partial of the load current and is muchsmaller than the load current, as can be seen from Fig. 14(c).Moreover, extensive experiments have been conducted withincreased current bandwidths. The result for 2 kHz bandwidthis shown in Fig. 15. It can be seen from Figs. 14(b) and 15that the time domain line currents are no difference with eitherthe 1 kHz or the 2 kHz bandwidth. This result verifies theconclusion drawn in Section IV that the dc link APF has alreadyachieved satisfactory harmonics compensation effect with1 kHz bandwidth. Increasing the current loop bandwidth further

does not add much to the harmonics reduction.Frequency domain analysis from the measured data is con-

ducted to quantify the bandwidth effect. For example, the linecurrent THD without compensation is 27.1% and is reduced to6.1% with 1 kHz bandwidth. It is further reduced to 4.9% with2 kHz bandwidth. The spectrum comparison with 1 and 2 kHzbandwidths is shown in Fig. 16. It shows that amplitudes of both line current harmonics are almost the same. The measuredTHD value is larger than the value presented in Table I, which iscaused by the non-ideal condition in practical implementations.The THD difference of 1 kHz and 2 kHz is 1.2%, which iscoincided with the performance tension of the dc link APF.

Our test result (4.9% THD) is better than 8.5% THD obtainedin [26].The transient input currents and dc bus voltage under load

change were also tested. The results are shown in Fig. 17. Thecurrent and voltage responses for the load R changing from220 Ω to 110 Ω are shown in Fig. 17(a), and responses withR increasing from 110 Ω to 220 Ω are shown in Fig. 17(b). It isobserved that the input currents move from one stable operationstate to another stable operation state. The dc bus voltage goesback to the rated value after the transient stage. Results of Fig. 17 were obtained from the 15 Hz voltage loop bandwidth,which was selected to reduce the effect of the low frequencyvoltage ripple from the dc bus voltage. These responses take

a few line cycles to settle down. The relative long transientinterval is due to the low voltage loop bandwidth.

Fig. 16. Spectrum comparison for different current loop bandwidth; thepurple bar is for 1 kHz and dark red bar for 2 kHz.

Fig. 17. Transient response under load change. (a) Step-up load. (b) Step-down load.

VII. CONCLUSION

A novel harmonic reduction method, which uses the dc linkAPF for three-phase diode rectifier, has been presented. Aver-age current control with input voltage feedforward is appliedto the control of this circuit. Voltage loop and current loopmodels have been developed for control design. Evaluationon the relationship between compensation performance andcurrent loop bandwidth has also been presented. The resultsshow that, under the same current loop bandwidth, the dc linkAPF performs better than the ac side APF. Even though thecompensation performance of the dc link APF is inferior to that

of the three-phase PFC, it is still well above the requirementsset by the IEC 61000-3-2 Class A standard [40]. Results of

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switching stress comparison reveal that the dc link APF hasthe potential of high efficiency and better silicon cost reductionability than the six-switch PFC. Therefore, the dc link APF andthe developed control scheme offer a high performance low costalternative for the harmonic elimination of three-phase dioderectifier. A major limitation of the proposed circuit is that, if

the galvanic isolation is required, the isolation transformer isexpensive and bulky due to the dc component in voltage andcurrent processed by the dc link APF.

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2001.

Xiong Du obtained the B.S., M.S., and Ph.D. degreesin the electrical engineering from Chongqing Uni-versity, Chongqing, China, in 2000, 2002, and 2005,respectively.

He has been with Chongqing University, since2002 and is currently a professor in the Collegeof Electrical Engineering, Chongqing University. Hewas a visiting scholar at Rensselaer PolytechnicInstitute, Troy, NY, from July 2007 to July 2008.His research interests include switching power con-verters, power quality control, and renewable energy

power conversion.Dr. Du is a recipient of the National Excellent Doctoral Dissertation of Chinain 2008.

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Luowei Zhou (M’04–SM’04) received the B.S.,M.S., and Ph.D. degrees in electrical engineering atChongqing University, Chongqing, China, in 1982,1988, and 2000, respectively.

Since 1982, he has been with the College of Elec-trical Engineering, Chongqing University, China,where he is now a full professor. He was a visitingprofessor at the University of California, Irvine, be-

tween September 1998 and August 1999. He is theadministrative director of China Society of PowerSupply. His major fields of interest include the analy-

sis and control of power electronics circuits, realization of active power filters,power factor correction techniques, and high frequency power conversion. Hehas published more than 60 papers, holds one US patent and three Chinapatents, and has three patents pending.

Hao Lu received the B.S. and M.S. degrees inelectrical engineering from Chongqing University,Chongqing, China, in 2006 and 2009, respectively.

He has been with the Delta Energy System as asenior electronic design engineer since 2009. His re-search interests include switching power convertersand power quality control.

Heng-Ming Tai (M’87–SM’93) received the B.S.degree in electrical engineering fromNational Tsing-Hua University, Hsinchu, Taiwan, and the M.S. andPh.D. degrees in electrical engineering from TexasTech University, Lubbock, in 1987.

He is a professor in the Department of ElectricalEngineering at the University of Tulsa, Tulsa, OK.His research interests are in the areas of signal and

image processing and industrial electronics.Dr. Tai is a member of Eta Kappa Nu and a seniormember of IEEE.

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