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An FPGA Implementation of a Feed-Back

Chaotic Synchronization for Secure

Communications

M. S. AZZAZ,C. TANOUGAST, S. SADOUDI, A. BOURIDANE and A. DANDACHE

Laboratoire Systemes de Communications, Ecole Militaire Polytechnique, Alger, AlgerieLaboratoire LICM, Universite Paul Verlaine de Metz, Metz Technopole, France

Northumbria University, Newcastle, United Kingdom

[email protected], [email protected]

Abstract In this paper, we propose a hardware imple-mentation of a Feed-Back Chaotic Synchronization (FCS)for designing a real-time secure symmetric encryptionscheme. This proposed scheme allows for the design and im-plementation of real time synchronization between two em-bedded chaotic generators for secure communications. Theimplementation and experimental results mapped on twoXilinx FPGA Virtex technology platforms using two Lorenzthree-dimensional continuous chaotic systems demonstratethe feasibility and the usefulness of this synchronizationapproach in terms of performance and hardware resourcesfor embedded encryption systems.

I. INTRODUCTION

Chaos has been introduced to cryptography as its ergod-

icity, unpredictability, and sensitivity to parameter and ini-

tial condition meet the analogous requirements of a good

cryptosystem [1], [2]. One of the recent developmentsof nonlinear dynamics and chaos was the realization of

the chaos synchronization between two identical chaotic

systems introduced by Pecora andCarroll [3] which can

be used in cryptography. This synchronization becomes

vital for accurate recovery of the transmitted signal in

encrypted communications based on chaotic generators.

Generally, the strategy of the secure communication based

on chaos approach consists of implementing a cipher

key chaotic generator used for the encryption of the

plaintext. A digital implementation of chaotic generators

presents some advantages and provides accuracy and

large possibility of integration in embedded applications

especially for data encryption and secures communica-

tions between embedded systems. Unlike, in an analogue

implementations which exhibit some practical difficulties

to ensure information recovery and to deal with the

problem of the chaotic synchronization since the com-

ponent values vary with age, temperature, etc. [6], [7],

a digital implementation avoids the parameter mismatch

between the transmitter and the receiver. In this context,

advances in VLSI technology have been employed to the

manufacturing of reconfigurable logic including FPGA

chips and have helped their rapid growth in logic capacity,

performance and popularity. Recently, several structures

of chaotic systems have been implemented using FPGAtechnology. For example, Lorenz, Chua or Chen systems,

which can be used for designing chaotic hardware key

generation for data encryption systems, have been pro-

posed [3], [4], [5], [6], [20]. However, digital hardware

implementations have not been proposed to implement the

synchronization between embedded chaotic generators.

In addition, some researchers in the area have beenthen interested to investigate chaos synchronization in

various fields including secure communications, optics,

chemical and biological systems, etc. This paper pro-

poses a real-time hardware implementation of the Feed-

Back chaotic synchronization(FCS) between two chaotic

signal generators using FPGA technology. Our proposed

architecture can be used for synchronizing any three-

dimensional continuous chaotic systems (Chuas system,

Lus system, Colpitts system, etc.) used as hardware key

cipher generator for encrypted communications [3], [4],

[5], [6]. The feasibility and efficiency of our implementa-

tion approach are demonstrated from the synchronizationof two Lorenzs chaotic systems where one correspond to

a Masterchaotic system embedded in one FPGA circuit

(Transmitter side) and the second is the Slave chaotic

system also embedded in an FPGA (Receiverside). This

paper is organized as follows. Section II reviews briefly

the Lorenzs chaotic system. Section III details the chaotic

synchronization of two Lorenzs chaotic generators using

a Feed-Back Synchronization approach. Section IV gives

the modeling and RTL architecture of the master and slave

systems for use to map FCS synchronization. The syn-

thesis and hardware implementation results on Virtex-II

Xilinx FPGA technology and the performances evaluation

are also detailed in this Section. Section V shows the

hardware platform experimental and the real time results

of our implementation. Finally, a conclusion is given in

the Section VI.

II. LORENZS CHAOTIC MODEL

The system of Lorenz is a well known example of

a chaotic system. The Lorenzs three-variable model

provides a practical test case with qualitatively realistic

properties. It is represented by the following nonlinear

equation system [13]:

dxmdt = (ymxm)dym

dt = xmzm+rxmym

dzmdt

= xmymbzm

(1)

978-1-86135-369-6/10/$25.00 2010 IEEE

CCS-8 239 CSNDSP 2010

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The solution of this nonlinear equation system depends

mainly on the Lorenzs parameters and the initial condi-

tions specified by the initial values ofx = x0, y = y0and z = z0. The standard parameter values and initialconditions for the Lorenzs chaotic attractor are: = 10,r = 8/3 , b = 28 and x0 = 0, y0 = 5, z0 =20, respectively [12]. This model was integrated witha fourth-order Runge-Kuttas numerical resolution (RK-

4 method) scheme with the following value for the time

step h = 0.01 [9], [20]. This means a higher precisionis adopted and is especially applicable to engineering

problems and will result in better and attractive random

numerical sequencesx(n), n is cycle times of numericalintegral algorithm.

III. FEED-BACK CHAOTIC SYNCHRONIZATION

Figure 1 illustrates the principle ofFeed Back chaotic

synchronization (FCS) adopted in our synchronization of

chaotic generators to evaluate the error rate.

Fig. 1. Illustration of the Feed-Back Chaotic Synchronization imple-mentation.

In this implementation, the master Lorenz model of

the set of equations (1), and the slave system are nudgedtoward values obtained from the master run as shown in

the set of equations (1):

dxsdt

= (ysxs)dysdt

= xmzs+rxmysdzs

dt = xmysbzs

(2)

Where the subscript m represents the master sys-tem (xm, ym, zm) and s represents the slave system(xs, ys, zs). We consider that the two trajectories of thexm(t) and xs(t) chaotic signals are synchronized if :

limt

|xm(t)xs(t)|= 0 (3)

Unlike in an analogue implementation, our digital im-

plementation based on FPGA technology allows us to

synchronize two chaotic systems given the sensitivity of

the mismatch parameters . The structure of a Feed-Back

Chaotic Synchronization implementation is depicted in

Figure 2 which is based on Dynamic Feedback Modu-

lation (DFM) [13]. The role of the FCS is to transmit

the chaotic drive signal xm(t), which is then injectedinto the two subsystems (ym, zm) and (ys, zs) (as il-lustrated in Figure 2). At the receiver side, the slave

system regenerates the chaotic signal xs(t) and producesa synchronization error rate between the received drive

and the regenerated drive signals. This technique canbe applied to chaotic modulation [13]. However, in this

case study it is used for generating chaotic keys for

Fig. 2. Functional architecture of theFeed-Back Chaotic Synchroniza-

tion.

stream cipher communications where the synchronization

between the Encrypter and the Decrypter is required.

Next section discusses our proposed implementation [13].

IV. PROPOSED ARCHITECTURE AND

MODELING

In this section, we present an optimized hardware

description of the master chaotic system defined by the

set of equations (1) of the transmitting side and the slave

chaotic system defined by the set of equations (2) ofthe receiver side. Each system is implemented on Xilinx

FPGA technology Virtex-II pro [16].

A. RTL Architecture of the master and-slave chaotic

systems

Our proposed architecture consists of the implementa-

tion of the RK-4 method to resolve Lorenzs differential

equations system first. An overview of the proposed

Register Transfer Level (RTL) architecture for the master

chaotic system is given in Figure 3. More precisely, this

figure depicts our data-path processing architecture which

is based on fixed parameters , r and b as specifiedin the previous Section. The architecture consists of the

structural feedback of the three main blocks: F1, F2 andF3. These three functional units implement the set ofequations (1) at the transmitter. where:

F1 = dxmdtF2 =

dymdt

F3 = dz

m

dt

(4)

Similarly, RTL architecture of the slave chaotic system is

depicted in Figure 4. The parameters of the slave chaotic

system are similar to those of the master one but the three

main blocks implementing equations (1), is given by:

G1 = dxsdtG2 =

dysdt

G3 = dz

s

dt

(5)

The RTL description of the proposed architecture

has been implemented on Xilinx Virtex-II FPGA

(XC2V1000) [16] using VHDL structural description.

ISE 10.1i of Xilinx tools [17] have been used for this

implementation allowing to obtain the logic resource

requirements and the associated real time constraints. The

synthesis results after place and route and performance

analysis of our implementation are shown in Table I

(master side) and Table II (slave side). These tablesspecify the hardware resources in terms of the logic Slice

or the Slice Flip-Flops numbers and the performances.


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Fig. 3. RTL architecture of the master chaotic system.

Fig. 4. RTL architecture of the Slave chaotic system.

TABLE I

IMPLEMENTATIONR ESULTS OF THE M ASTERC RYPTOSYSTEM W IT H

VIRTEX-II-PRO FPGA (2VP30FF896-7)

Transmitter device utilization summary FPGA: 2vp30ff896-7

Number of Slices 2038 out of 13696

Number of BRAMs 813 out of 136

Number of MULT 18X18s 40 out of 136Maximum Fr eq uency 2 9.837 MHz

TABLE II

IMPLEMENTATIONR ESULTS OF THES LAVE S YNCHRONIZED

CRYPTOSYSTEM W IT HV IRTEX-II-PRO FPGA (2VP30FF896-7)

Receiver device utilization summary FPGA: 2vp30ff896-7

Number of Slices 2038 out of 13696

Number of BRAMs 813 out of 136

Number of MULT 18X18s 40 out of 136

Maximum Frequency 29.837 MHz

The results and their analysis have demonstrated that

both the master and slave chaotic systems have similar

synthesis results when implemented independently on

FPGA (Transmitter and Receiver). This proves that a

real-time FCS can be efficiency implemented with FPGA

technology. It can be stated that an attractive trade-off

between high speed and low logic resources has been

achieved. Indeed, our implementation on a Xilinx Virtex-

II device uses only 2038 CLB-Slices corresponding to

14 % of FPGA area, 40 multipliers and no block RAMs

for the master and the slave chaotic system because it

the transmitter is clearly symmetrical to the receiver. To

evaluate the behavior of the proposed system, it is neces-

sary to use some evaluation metrics. As adopted by the

research community, the metrics used for the evaluation

results for this system are the throughput rate and the

time latency. The throughput rate is defined as the number

of bits by unit of time. In our implementation, this rate

corresponds to 32 bit word-length during one operating

clock frequency. From the performance results (Table I or

Table II) it can be observed that a maximal throughput of0.95 Gbps has been achieved. It is worth noting that this


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Fig. 5. ModelSim simulation results of the proposed Chaotic Synchro-nization and its error rate.

throughput rate is computed after the initialization phase.

Latency is defined as the time necessary to generate one

single word-length signal after the start of the generator.

Our optimized implementation of the master or the slave

chaotic systems requires 6 clock cycles to generate one

word-length chaotic signal. In our architecture, a timelatency of 200 ns has been obtained. Thus, the hardware

implementation clearly show attractive performances in

terms of the throughput and resource costs required.

B. Structural Description and Functional Simulation Re-

sults

The two proposed architectures (Masterand Salvewith

parameters: = 10, r = 8/3 and b = 28) are simulatedto ascertain their correct functional operation with test

vectors returned by a software implementation usingModelSimsimulator tool [18]. This validation consists to

model and describe in VHDL directly the RK-4 method

using the followings RK-4 value coefficients (h = 0.01,coef = 1/6) [8]. Since the continuous chaotic signalsare real, our proposed architectures treat finite resolution

numbers using a binary representation. More precisely,

our data-path architectures have adopted hardware imple-

mentations based on finite solution numbers with a fixed

point representation of the real data on 32 bits (16Q16).

i.e. all data are fixed point format with 16 bits integer and

16 bits fraction. This fixed-point arithmetic format allows

a very useful and attractive trade off between high speed

and low area cost because the presentation on 32 bits(16Q16) gives more precision in the representation of the

real data while preserving the dynamic of the generated

chaotic signals. The ModelSim simulation results of the

Feed-Back chaotic synchronization between the Lorenzs

Master chaotic system of and the Lorenzs Slave chaotic

system; is shown in Figure 5.

The synchronization error is depicted in Figure 6. The

synchronization between the Master and Slave chaotic

systems is achieved after 470 samples. The time of

the simulation corresponding of the maximum frequency

allowed by the hardware synthesis is 0.033s. This means

that the synchronization is completely realized betweenthe master and slave chaotic systems after 18 s runningas shown in Figure 7.

Fig. 6. Functional simulation of the synchronization error rate.

Fig. 7. Feed-Back Chaotic Synchronization after 18 s.

V. EXPERIMENTAL MEASUREMENTS

RESULTS

A real-time experimentation for our implementation of

the Feed-Back Synchronizationbetween two XUP Virtex-

II-Pro FPGA platforms is shown in Figure 8. The first

FPGA platform is configured as a transmitter which is em-

bedded by the Master chaotic signal characterized by the

set of equations (1) and modeled by the RTL architecture

depicted in Figure 3. At the other side the second FPGA

platform is configured as a receiver which is mappedby the Slave chaotic signal characterized by the set of

equations (2) and modeled by the RTL architecture shown

in Figure 4. The transmitter and the receiver real-time

attractors measurements of our proposed architecture,

obtained by a direct implementation after optimization,

are depicted in Figures (9.a) and (9.c), respectively. These

Snapshots are given by a digital oscilloscope [19]. The

measured real-time signals of the drive signal Xm andthe regenerated Xs are presented in Figure (10.a). Basedon the Feed-Back Chaotic Synchronization principle, we

synchronize the response system to the drive system. By

using the Lorenz system, the chaotic synchronization is

achieved exactly, which is clearly shown in the Figure(10.b). However, this synchronization is lost when an

error of1015 is introduced at one parameter of the slave

Fig. 8. Real time experimentation on FPGA platforms of theFeed-BackChaotic synchronization after 18 s running.


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(a) (b)

Fig. 9. Real-time(x y) chaotic attractor of the Lorenz model: (a)Transmitter attractor, (b) Receiver attractor.

(a)

(b) (c)

Fig. 10. Real-Time Feed-Back Chaotic Synchronization: (a) Xmand Xs chaotic signals, (b) Achieved synchronization, (c) de-synchronization.

chaotic system (the receiver side) for example , this de-

synchronization is shown in Figure (10.c). These results

clearly confirm that the implemented chaotic synchroniza-tion works well and verifies the simulation results thereby

demonstrating its feasibility when using our proposed

architecture.

VI. CONCLUSION AND FUTURE WORK

This paper proposes a hardware implementation of a

Feed-Back Chaotic Synchronization for designing a real-

time secure symmetric encryption scheme. The proposed

implementation allows for the design of a real time

synchronization system between two embedded chaotic

generators for secure communications. Through a hard-

ware implementation using FPGA technology, we have

demonstrated that by considering two Lorenzs chaotic

generators as master and slave transmission systems, the

feasibility and efficiency of our synchronization approach

is obtained. This has been achieved and verified by real-

time experimentation and simulation of the proposed

architectures. In addition, our experimental results show

the robustness of the synchronization technique (syn-

chronization achieved after 18 s running). Moreover,our experimental results using Xilinx Virtex technology

have demonstrated that our approach can lead to designs

with small logic area, satisfactory throughput rates and

low latency for embedded applications. For example, animplementation on a Xilinx Virtex-II technology requires

only 2038 CLB-Slices, 40 multipliers and no block RAMs

for each side (Transmitter, Receiver). Our FPGA imple-

mentation achieves a throughput rate of 0.95 Gbps at a

clock frequency of 29.837 MHz with a low latency time

of 200 ns. Once can clearly conclude the feasibility of

deploying a chaotic synchronization between two three-

dimensional continuous chaotic systems. Finally, our new

approach is very simple, exhibits attractive performances

and is useful in the field of secure communications Ongo-

ing work is underway to further improve the performance

of the architecture targeting a full implementation in a

pipelined fashion although coming at the expense of an

increase the latency.

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