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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010 2785

FinFET SRAM Optimization With Fin Thicknessand Surface Orientation

Mingu Kang, S. C. Song, S. H. Woo, H. K. Park, Student Member, IEEE, M. H. Abu-Rahma, L. Ge, B. M. Han,J. Wang, G. Yeap, and S. O. Jung, Senior Member, IEEE

Abstract—In this paper, the design space, including fin thick-ness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors,and surface orientation, is researched to optimize the stability,leakage current, array dynamic energy, and read/write delay ofthe FinFET SRAM under layout area constraints. The simulationresults, which consider the variations of both Tfin and thresholdvoltage (Vth), show that most FinFET SRAM configurationsachieve a superior read/write noise margin when compared withplanar SRAMs. However, when two fins are used as pass gatetransistors (PG) in FinFET SRAMs, enormous array dynamicenergy is required due to the increased effective gate and draincapacitance. On the other hand, a FinFET SRAM with a one-finPG in the (110) plane shows a smaller write noise margin than theplanar SRAM. Thus, the one-fin PG in the (100) plane is suitablefor FinFET SRAM design. The one-fin PG FinFET SRAM withTfin = 10 nm and Hfin = 40 nm in the (100) plane achieves athree times larger noise margin when compared with the planarSRAM and consumes a 17% smaller bit-line toggling array energyat a cost of a 22% larger word-line toggling energy. It also achievesa 2.3 times smaller read delay and a 30% smaller write delay whencompared with the planar SRAM.

Index Terms—Cell current, FinFET, leakage current, read sta-bility, SRAM, surface orientation, write stability.

I. INTRODUCTION

F inFET technology is one of the leading candidates for analternative device structure to replace a planar CMOS for

an ultradeep submicrometer device region. The FinFET hassuperior scalability due to the stronger electrostatic control ofthe channel, which suppresses the short-channel effect (SCE)[1], [2]. The FinFET also has a potentially higher layout densitydue to its vertical structure and higher ON current, comparedto planar devices [3]. In addition, the thin body of a double-gate device is typically undoped or lightly doped. Thus, therandom dopant fluctuation (RDF) is significantly decreased,which results in the reduction of the threshold voltage (Vth)variation [4], [5]. The SRAM bit-cell is considered as the firstfunctional block in the system on a chip to be implemented

Manuscript received February 19, 2010; revised July 23, 2010; acceptedJuly 23, 2010. Date of publication August 30, 2010; date of current ver-sion November 5, 2010. The review of this paper was arranged by EditorC. Jungemann.

M. Kang was with the School of Electrical and Electronic Engineering,Yonsei University, Seoul 120-749, Korea. He is now with the Memory Division,Samsung Electronics, Hwaseong 445-701, Korea.

S. C. Song, M. H. Abu-Rahma, L. Ge, B. M. Han, J. Wang, and G. Yeap arewith Qualcomm Inc., San Diego, CA 92121 USA.

S. H. Woo, H. K. Park, and S. O. Jung are with the School of Electricaland Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail:[email protected]).

Digital Object Identifier 10.1109/TED.2010.2065170

using the FinFET because the critical issues of the SRAM bit-cell scaling, such as the demand for continuous bit-cell sizescaling and electrical stability problems, can be resolved [6].Thus, the optimal design of the SRAM bit-cell with the FinFETis analyzed in this paper.

For a standard planar CMOS, (100) silicon substrates havebeen used generally due to superior electron mobility, which ishigher in the (100) plane than that in the (110) plane. However,the mobility of a hole in the (100) plane is lower than thatin the (110) plane. For planar device technology, the deviceswith a (110) surface orientation have to be fabricated on siliconsubstrates with a (110) crystalline orientation, which is notgenerally used. However, both the (100) and (110) orientationsfor the FinFET can be achieved in the (100) plane because ofthe vertical structure. As shown in Fig. 1, the (110)-orientedFinFET can be achieved by only rotating the transistor layoutby 45◦ in the plane of a (100) wafer [7]. However, there isan inevitable area penalty for using multiorientation, whereboth (100)- and (110)-oriented FinFETs are used on the samewafer, because the angle between the (100)- and (110)-orientedFinFETs has to be 45◦ [8]. In addition, multiorientation is notpractical due to its complex fabrication process. Thus, single-oriented FinFET SRAM designs (all (110)- or (100)-orientedFinFETs in the (100) plane) are considered, rather than the mul-tioriented FinFET SRAM ones. The p-n mobility ratios used inthis paper are decided to express the general characteristics ofthe (100) and (110) orientations by considering the sensitivity tothe modest amount of process-induced strain from [7] and [9].The different results between the (100) and (110) orientations inthis paper are mainly caused by the p-n mobility ratio. The ratiolargely depends on the surface orientation but can be affectedby other elements, such as the materials and process-inducedstrain. Thus, it is noted that the models for the (100) and (110)orientations in this paper are one of the possible choices to showthe general trend between the orientations rather than representthe absolute characteristics of the orientations.

The Tfin variation of the FinFET is one of the major sourcesof the Vth variation along with the RDF. Thus, both the RDFand the Tfin variation are considered for the FinFET SRAM.While reducing the fin thickness (Tfin) suppresses the SCE,the fabrication of a thin FinFET is challenging and increasesthe variation of Tfin, which results in a large Vth variation[10]. Thus, different variations depending on the Tfin value areapplied for the FinFET SRAM.

Because of the vertical nature of the device structure, theFinFET can achieve a higher effective channel width (hence,a higher driving strength) per unit planar area by increasing

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2786 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010

Fig. 1. (a) FinFET with different Tfin value. (b) Multioriented FinFETs on(100) wafer.

the fin height (Hfin), compared to a planar device. However,the Hfin is limited by the Tfin, the source/drain implantationangle, and the planar area when multifins are used. Therefore,determining the appropriate combination of Hfin and Tfin iscritical to achieve an optimizing FinFET SRAM bit-cell withthe same layout area constraints. In this paper, the top portionof the fin is also used for the gate control.

This paper is organized as follows. The planar and FinFETSRAM bit-cell designs are described in Section II. The sta-tic noise margins in various design spaces are presented inSection III. The SRAM bit-cell and leakage currents are pro-vided in Section IV. The read/write delay and dynamic array en-ergy, including both the SRAM bit-cell and read/write drivers,are described in Section V. The evaluation for the FinFETSRAMs is presented in Section VI. Finally, the conclusionsare reported in Section VII. In this paper, a 32-nm foundry-compatible planar model parameter and a Berkeley commongate FinFET model parameter are used with a fixed 0.9-Vsupply voltage (VDD) for both the SRAM bit-cell and the logicarea [11].

II. SRAM BIT-CELL DESIGN

Since the Tfin fluctuation in the FinFET results in the Vth

variation, it can cause an SRAM device mismatch. Further-more, the saturation current (Idsat) per unit width is decreasedwith the reduction of Tfin due to the mobility degradationby scattering [12]. Thus, the characteristics of the FinFET

Fig. 2. (a) Planar SRAM bit-cell layout. (b) FinFET SRAM bit-cell layout.

SRAM need to be evaluated with the Tfin variation. In a planarSRAM bit-cell, the width of a transistor is the same as thehorizontal dimension of the transistor in the layout, as shownin Fig. 2(a). However, the geometric effective width of theFinFET is calculated as (2Hfin + Tfin) since the top portionof the fin is used for the gate control, which is different fromthe horizontal dimension. Thus, the horizontal dimension ofthe transistors in the FinFET SRAM bit-cell is defined as a2-D width as shown in Fig. 2(b). Even though the top portionof the fin is used for the gate control, the FinFET behaves asa double-gate device with scaling Tfin due to the diminishedchannel controllability at the top portion. As Tfin scales further,the FinFET suffers from more serious current crowding at thecorner of the fin. Therefore, the electrical effective widths ofthe FinFETs even with the same geometric effective width canbe different depending on the fin geometry.

Under the same layout area constraints for the planar andFinFET SRAM bit-cells, the stability, performance, and arraydynamic energy are analyzed for the planar SRAM and thevariant configurations of the FinFET SRAM. For the samelayout area, the 2-D width of a pull-down transistor (PD) inthe FinFET SRAM bit-cell is chosen to be same as the width(70 nm) of a PD in the planar SRAM bit-cell. In order not toexceed the area limitation, the maximum fin number is limitedto two. Therefore, the fin numbers (NU and ND) of a pull-up transistor (PU) and the PD are decided to be one and two,respectively, for a larger static noise margin. As shown inFig. 2(b), if the fin number (NG) of a pass gate transistor (PG)is not larger than ND, the bit-cell area is not affected by NG

because the 2-D width of the PG is not larger than that of thePD [13]. Thus, one and two of NG do not require an additionallayout area.

When NU is one in the FinFET SRAM bit-cell, the 2-Dwidth of the PU is decided by the minimum contact pad width(50 nm), which is similar to the PU width (45 nm) in the planarSRAM bit-cell [14]. On the other hand, as shown in Fig. 3, the

KANG et al.: FinFET SRAM OPTIMIZATION 2787

Fig. 3. FinFET diagram.

TABLE IFinFET SRAM DESIGN SPACES

2-D width of the PD in the FinFET SRAM bit-cell is decidedby the following equation

2-D Width of PD = 2 × MTP + Fin# × Tfin

+ Tan(θ) × Hfin × (Fin# − 1) (1)

where θ is a source/drain implantation angle that depends onprocess technology. MTP means the minimum margin fromthe edge of contact to the contact landing pad. The Hfin andTfin ratio depends on the technology constraint and is generallychosen to be 1–5 [15]. With 70 nm of the 2-D width of the PDin a FinFET SRAM bit-cell, the following three combinationsof Tfin and Hfin are created, assuming MTP = 5 nm andθ = 45◦: (Tfin,Hfin) = (10 nm, 40 nm), (15 nm, 30 nm), and(20 nm, 20 nm). The FinFET SRAM design spaces accordingto the surface orientation, fin ratio, and (Tfin,Hfin) combinationare described in Table I. To evaluate the effect of the FinFETgeometry, it is assumed that the identical implant doping isapplied to all the cases of the FinFET, and no separate implantstep for the SRAM bit-cell is used.

III. SRAM BIT-CELL STABILITY

Fig. 4 describes Idsat and the OFF current IOFF per unit widthof the FinFET and planar devices. As shown in Fig. 4(a), allthe FinFETs using three (Tfin,Hfin) combinations achieve alarger Idsat per unit width than the planar device. In a standard(100) plane, the Idsat of the NMOS is larger than that of thePMOS while the Idsat of the PMOS is larger than that of theNMOS in the (110) plane. Fig. 5 shows the Idsat–Vgs curves ofthe NMOS and PMOS in three (Tfin,Hfin) combinations in the(100) plane. The Vth is higher in a narrower fin by suppressedVth rolloff and DIBL owing to the improved short-channel

Fig. 4. (a) Idsat per unit width and (b) IOFF per unit width when gate length(Lg) = 35 nm and oxide thickness (Tox) = 1 nm.

Fig. 5. Idsat–Vgs curve of planar and FinFET with Lg = 35 nm and Tox =1 nm in the (100) plane.

effect. Thus, when Tfin is reduced, the Idsat and IOFF per unitwidth of the FinFET become smaller, as shown in Fig. 4. TheFinFET with Tfin = 20 nm, which suffers from the SCE, has aneven larger IOFF than that of a planar device. The geometriceffective widths in the (10 nm, 40 nm), (15 nm, 30 nm), and(20 nm, 20 nm) combinations are 90, 75, and 60 nm, respec-tively. Thus, as shown in Fig. 5, the Idsat is largest and smallestin the (10 nm, 40 nm) and (20 nm, 20 nm) combinations,respectively.


Fig. 6. RSNM and WNM of planar and FinFET SRAM bit-cells.

To measure the read static noise margin (RSNM) and thewrite noise margin (WNM), the statistical (Monte Carlo)simulations are performed with the Vth variation caused by theRDF and Tfin variation. When Tfin is thin, the Vth variation isincreased. Yu et al. [16] show that, when Tfin is 10, 15, and20 nm, the standard deviation of Vth caused by only the Tfin

variation (σVt.Tfin) is 15.5, 14, and 12.5 mV, respectively. Thesigma of the Vth variation caused by the RDF (σVt.RDF) isdecided by the following equation

σVt.RDF =Avt√

Width(= 2Hfin + Tfin) × Length(2)

where Avt is a technology constant proportional to the ox-ide thickness and the channel doping. In this paper, 2.5 and1.76 mV · μm are used for the Avt of the planar device andFinFET, respectively [17]. Even though the σVth.RDF is notindependent of the Tfin variation as shown in (2), the effectis negligible. Thus, σVt, which includes both σVt.RDF andσVt.Tfin, can be expressed by the following equation with theassumption that σVt.RDF and σVt.Tfin are independent

σVt =√

σ2Vt.RDF + σ2

Vt.Tfin. (3)

In Fig. 6, the RSNM and WNM of the planar and FinFETSRAM bit-cells are described. The RSNM and the WNM aremeasured with the methods described in [18] and [19], respec-tively. The RSNM and the WNM in the y-axis in Fig. 6 arepresented as μ/σ in order to standardize each result. Generally,the RSNM and WNM of the FinFET SRAM are larger thanthose of the planar SRAM because the effect of the small RDFsurpasses that of the Tfin variation.

The driving strength of the PG divided by that of the PUis defined as the alpha ratio. The driving strength of the PDdivided by that of the PG is defined as the beta ratio. The RSNMis proportional to the beta ratio while the WNM is proportionalto the alpha ratio [20]. In addition, when the driving strength ofthe PU relative to that of the PD is high, the trip point of theinverter becomes high. Thus, the RSNM is also proportional tothe driving strength of the PU divided by that of the PD.

Fig. 7. (a) Currents in SRAM bit-cell during read operation. (b) Butterflycurves of cases 1 and 3.

A schematic of the SRAM bit-cell and the butterfly curvesof cases 1 and 3 are shown in Fig. 7(a) and (b), respectively.In Fig. 7(b), the curved point (C-point) is the point wherethe gradient is −1. At the C-point, the PU and the PG inFig. 7(a) are in the linear region, and PD is in the saturationregion, respectively. Thus, the currents through the PU, PG,and PD (IPU, IPG, and IPD) can be expressed by the followingequations

IPU ≈KPU (VDD − VIN − |Vtp|) (VDD − VOUT) (4)

IPG ≈KPG(VDD − VOUT − VtnG)(VDD − VOUT) (5)

IPD =12KPD(VIN − VtnD)γ (6)

KPU = μP COX

(W

L

)PU

KPG = μNCOX

(W

L

)PG

KPD = μNCOX

(W

L

)PD

(7)

where μP and μN are the mobility of the PMOS and NMOStransistors, respectively. Vtp, VtnG, and VtnD are the thresh-old voltage of the PU, PG, and PD, respectively. (W/L)PU,(W/L)PG, and (W/L)PD are the width/length of the PU, PG,and PD, respectively, and COX is the oxide capacitance. γ isthe number between one and two. To measure the RSNM, it isassumed that the voltages of the word-line and the bit-line_b are


VDD. The summation of IPU and IPG is the same as IPD duringthe read operation. Thus, the following equations are derivedfrom (4)–(6)

VOUT =VDD − 12KPG

[− KPU(VDD − VIN − |Vtp|)

+ KPGVtnG +√

X]

(8)

dVOUT

dVIN= − 1

2KPG

[KPU +

1

2√

X

dX

dVIN

](9)

where

X = [KPU (VDD − VIN − |Vtp|) − KPGVtnG]2

+ 2KPGKPD(VIN − VtnD)γ (10)

dX

dVIN= − 2K2

PU (VDD − VIN − |Vtp|) + 2KPUKPGVtnG

+ 2KPGKPDγ(VIN − VtnD)γ−1. (11)

Because dVOUT/dVIN is −1 at the C-point, it is provenby the numerical calculation of (9) that the C-point occurs athigh VIN with high |Vtp|, VtnG, and VtpD. As a result, theC-point of the butterfly curve becomes sharper in case 1 thanin case 3, as shown in Fig. 7(b), which results in a largerSNM in case 1. Thus, as shown in Fig. 6, when Tfin is smaller,the RSNM becomes generally higher due to the higher Vth ofthe transistors. With NG = 2, the RSNM is decreased and theWNM is increased when compared with those with NG = 1because the beta and alpha ratios are decreased and increased,respectively, due to the enhanced driving strength of the PG.In the (110) plane, the RSNM is increased and the WNM isdecreased when compared with those in the (100) plane, due tothe enhanced driving strength of the PU.

Fig. 8 describes how much the σ of the RSNM and WNM(σRSNM and σWNM) are increased by the Tfin variation whencompared with the cases where only the RDF is applied withoutthe Tfin variation. σRSNM and σWNM can be increased by over18% from the Tfin variation. When Tfin is smaller, the variationof Tfin is larger, which results in a larger increase of σRSNM

and σWNM. Thus, the increase in σRSNM and σWNM caused bythe Tfin variation is three times larger in the (10 nm, 40 nm)combination when compared with that in the (20 nm, 20 nm)combination.

As shown in Fig. 5, the Vth of a planar device is smaller thanthat of the FinFET with Tfin = 10 and 15 nm. In addition, theeffect of the RDF is smaller on the FinFET than on the planardevice because of its lightly doped channel and larger effectivewidth, which results in a smaller Vth variation. As the FinFETshows less Vth variation, the FinFET SRAM bit-cell achieves agenerally larger RSNM and WNM, compared with the planarSRAM bit-cell despite the Tfin variation. The WNMs of theFinFET SRAM bit-cells in cases 7, 8, and 9 are smaller than thatof the planar SRAM bit-cell, owing to the strong PU in the (110)plane. When the RSNM and WNM of the planar SRAM bit-cellare regarded as criteria for stability, the FinFET SRAM bit-cellsin cases 7, 8, and 9 are not desirable. Thus, in the followingsections, cases 7, 8, and 9 are not analyzed further.

Fig. 8. Effect of Tfin variation on RSNM and WNM.

Fig. 9. Icell and IOFF per one SRAM bit-cell.

IV. LEAKAGE AND CELL CURRENT OF SRAM BIT-CELL

The cell current (Icell) and IOFF per unit SRAM bit-cell ofall cases are described in Fig. 9. Within the same layout area,the effective width of the transistor is larger in the FinFETSRAM than in the planar SRAM. Thus, a larger Icell is achievedin the FinFET SRAM bit-cell. The (Tfin = 10 nm,Hfin =40 nm) configuration achieves the largest Icell when comparedwith the other (Tfin,Hfin) configurations owing to the largesteffective width despite the highest Vth. When Tfin is smaller, theFinFET SRAM bit-cell achieves a smaller IOFF due to superiorelectrostatic channel controllability. When NG = 2, Icell andIOFF become larger because of the larger driving strength ofthe PG transistor. In the (110) plane, the driving strength of theNMOS is decreased, which results in smaller Icell and IOFF

than those in the (100) plane.


Fig. 10. (a) Definition of effective gate capacitance (Cgeff) and effectivedrain capacitance (Cdeff). (b) Cgeff and Cdeff per unit width for FinFET andplanar devices normalized to planar NMOS Cgeff .

V. DELAY AND ENERGY CONSUMPTION DURING READ

AND WRITE OPERATIONS

The effective gate capacitance (Cgeff) and the effective draincapacitance (Cdeff) are defined in Fig. 10(a), and the relativecapacitance per unit width when compared with the Cgeff ofthe planar NMOS is described in Fig. 10(b). The capacitance ismeasured by the delay required to drive Cgeff or Cdeff from 0 Vto VDD by the same inverter. The Cgeff includes not onlythe gate oxide capacitance but also the fringing and overlapcapacitances because the fringing and overlap capacitances areconnected across the gate and the drain. The Cdeff includes notonly the junction capacitance but also the fringing and overlapcapacitances. As shown in Fig. 10(b), the Cgeff of the FinFETper unit width is about 70% of that of a planar device, caused bya thicker gate dielectric which can be used owing to the strongelectrostatic channel controllability. In addition, owing to a lowchannel doping concentration and vertical structure, the Cdeff

per unit width of the FinFET is only 45% of that of a planardevice. The reduced Cgeff and Cdeff per unit width provide notonly the reduced bit-line toggling power but also the potentiallyreduced delay of the read and write operations.

In Fig. 11, the SRAM array configuration is describedto measure the delay and power consumption during theread and write operations. To consider the wiring capaci-tance, 0.2 fF/μm is assumed. The word-line and bit-line aredriven by a four-stage inverter chain. In the (100) plane,the PMOS width is decided to be two times the NMOSwidth in the inverter chain, to balance the driving strengths.

Fig. 11. SRAM array configuration.

Fig. 12. Word-line and bit-line toggling energies normalized to bit-line tog-gling energy of planar SRAM.

On the other hand, in the (110) plane, the PMOS widthis set to be the same as the NMOS width because thedriving strengths of the NMOS and PMOS are almost thesame, as shown in Fig. 4(a). The SRAM array consists of128 columns and 256 rows. The Tfin of the inverter chain isthe same as that of the SRAM bit-cell.

Fig. 12 describes the word-line and bit-line toggling energies,which are normalized to the bit-line toggling energy of theplanar SRAM, to toggle one word-line and one bit-line from0 V to VDD, respectively. The bit-line and word-line togglingenergies consumed at the last-stage inverter of the word-lineand bit-line drivers are measured. The word-line capacitanceis proportional to the PG Cgeff × NG. On the other hand, thebit-line capacitance is proportional to the PG Cdeff × NG. Asshown in Fig. 10(b), the Cgeff per unit width of the FinFET issmaller than that of the planar device. However, the effectivewidth of a FinFET PG is larger than that of a planar devicePG in all the cases. Thus, in all the cases except case 3, theCgeff of the FinFET PG is larger than that of the planar PG,which leads to a larger word-line capacitance in the FinFET


SRAM than in the planar SRAM. As a result, the word-linetoggling power of the FinFET SRAM is larger than that of theplanar SRAM. On the other hand, as shown in Fig. 10(b), theFinFET achieves a larger Cdeff reduction (55%) per unit widththan the Cgeff reduction (40%) per unit width when comparedwith the planar device. Thus, the FinFET SRAM in cases 1,2, and 3 achieves a bit-line energy reduction when comparedwith the planar SRAM. Because many bit-lines (several tens tohundreds of bit-lines) toggle when one word-line toggles duringthe read and write operations in an SRAM array, the bit-linetoggling energy is the dominant factor for most SRAM arrays.Thus, despite the increased word-line toggling energy, the totalenergy consumption in the array of the FinFET SRAM wouldbe much smaller than that of the planar SRAM in cases 1, 2, and3. The word-line and bit-line toggling energies are largest in the(10 nm, 40 nm) combination, owing to the largest effectivewidth of the PG. When NG = 2, the word-line and bit-linetoggling energies are larger than that when NG = 1 becauseof the larger effective width of the PG.

The read delay consists of the following two delay compo-nents: 1) the delay from the In_word triggering to the word-lineenabling and 2) the delay from the word-line enabling to thetime when the bit-line voltage becomes 20% of VDD. The writedelay is measured, provided that the valid data are loaded on abit-line before the write operation begins. Thus, the write delayconsists of the following two delay components: 1) the delayfrom the In_word triggering to the wordline enabling and 2) thedelay from the word-line enabling to the time when the voltagesof the VR and VL nodes become the same (VR–VL crossingpoint).

Fig. 13 shows the read and write delays. The FinFET SRAMshows smaller read and write delays in all the cases when com-pared with the planar SRAM since superior driving capabilitysurpasses the increment of Cgeff and Cdeff caused by a largereffective width. As shown in Fig. 5, when Tfin is smaller, Vth

becomes higher, which results in a smaller driving strength. Asa result, with a smaller Tfin, the first part of the read and writedelays, which is the delay of the inverter chain, becomes larger.When NG = 2, the first part of the read and write delays islarger than when NG = 1, due to the larger capacitance on theword-line. In case 1, the second part of the read delay is smallerthan in case 3, due to the superior driving strength of the PG bythe aid of its greater effective width. When NG = 2, the secondpart of the read and write delays is smaller than when NG = 1,due to the larger driving strength of the PG. In the (110) plane,the same widths are used for the NMOS and the PMOS in theinverter chain while the PMOS width is twice that of the NMOSin the (100) plane. Thus, the capacitance of the inverter chain isgenerally smaller in the (110) plane than that in the (100) plane.As a result, the first part of the read and write delays becomessmaller in the (110) plane. On the other hand, the second partof the read delay becomes larger, owing to the smaller drivingstrength of the PG.

VI. EVALUATION OF FINFET SRAM

As shown in the previous sections, the FinFET SRAM bit-cell with NG = 2 achieves large WNM and Icell and short

Fig. 13. SRAM operation delay. (a) Read delay. (b) Write delay.

read/write delays. Thus, if the performance or stability is themain target of the design, the cases with NG = 2 are the properchoices. Case 12 shows outstanding speed performance andmoderate stability. On the other hand, case 4 or 10 achievesdistinguished write stability. However, owing to the greatlyincreased Cgeff and Cdeff , the cases with NG = 2 consumeenormous word-line and bit-line toggling energies. If a lowpower consumption is considered to be a major goal of theSRAM, the FinFET SRAM bit-cell with NG = 2 is not desir-able. Because of the large IOFF with Tfin = 20 nm, case 3 isalso not recommendable, and cases 1 and 2 are applicable forlow-power design.

Case 2 has a larger IOFF when compared with case 1 becauseof a smaller Vth. IOFF significantly affects the total powerconsumption since most of the bit-cells are in a hold state. Thus,case 1 is more suitable for low-power application than case 2.Even with the Tfin variation, case 1 achieves 3.3 and 2.8 timeslarger RSNM and WNM, respectively, when compared withthe planar SRAM bit-cell because the effect of the small RDFand high Vth surpasses that of the Tfin variation. In addition,


case 1 achieves 2.6 times larger Icell and 103.7 times smallerIOFF when compared with the planar SRAM bit-cell due toa larger effective width achieved by the vertical structure andsuperior electrostatic channel control, respectively. Because ofa larger driving strength and smaller Cgeff and Cdeff than aplanar device, the FinFET SRAM in case 1 achieves a 2.3 timessmaller read delay and a 30% smaller write delay. The FinFETSRAM in case 1 also achieves a 17% smaller bit-line togglingpower at a cost of a 22% larger wordline toggling power whencompared with the planar SRAM, respectively.

VII. CONCLUSION

In this paper, the FinFET SRAMs with possible (Tfin,Hfin)combinations, fin ratio, and surface orientation are researchedwith regard to speed, stability, leakage current, and array dy-namic energy under area constraints. Despite the Tfin variation,the FinFET SRAM achieves a superior read/write noise margincompared to that of the planar SRAM, owing to the smallRDF. In addition, owing to the strong driving capability withthe aid of the vertical structure, most FinFET SRAM con-figurations show superior speed performance when comparedwith the planar SRAM. However, the cases with NG = 2consume too much word-line and bit-line toggling energiesbecause of the greatly increased Cgeff and Cdeff . Moreover, thecases with NG = 1 in the (110) plane show very poor writestability. In the case of NG = 1 in the (100) plane, the (Tfin =15 nm,Hfin = 30 nm) and (Tfin = 20 nm,Hfin = 20 nm) con-figurations show too much IOFF. The optimal configurationwith (Tfin = 10 nm,Hfin = 40 nm) and NG = 1 shows 103.7

times smaller IOFF due to a high Vth and shows three timeslarger read and write noise margins when compared with theplanar SRAM bit-cell despite the Tfin variation. It also achievesa 2.3 times smaller read delay and a 30% smaller write delaywhen compared with the planar SRAM.

REFERENCES

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Mingu Kang was born in Changwon-Si,Gyeongsangnam-Do, Korea, in 1981. He receivedthe B.S. and M.S. degrees in electrical and electronicengineering from Yonsei University, Seoul, Korea,in 2007 and 2009, respectively.

Since 2009, he has been with the Memory Di-vision, Samsung Electronics, Yongin, Korea, wherehe has been engaged in the design of PRAM. Hisresearch interests include low-power PRAM andSRAM and FinFET application for memory circuits.

S. C. Song received the Ph.D. degree in solid stateelectronics from The University of Texas at Austin,Austin, in 2000.

Since 2000, he has been in engineering and man-agement positions in various organizations, includ-ing Motorola, Samsung, and SEMATECH, workingon advanced CMOS process/device technology de-velopment. He is currently with Qualcomm Inc.,San Diego, CA, where he leads the 28-nm HK/MGtechnology development with leading foundries. Hehas contributed several key papers to high-profile

journals and conferences on various topics of CMOS technology, includingSiON, HK/MG, and FinFET. He is the holder of six U.S. patents.


S. H. Woo was born in Seoul, Korea, in 1983. Hereceived the B.S. degree in electrical and electronicengineering from Yonsei University, Seoul, Korea, in2009, where he is currently working toward the M.S.degree.

His current research interests include the analysisof offset voltage, sensing the dead zone of a senseamplifier, PVT variation sensing, and compensationcircuit design.

H. K. Park (S’10) was born in Iksan, Jeollabuk-do, Korea, in 1982. He received the B.S. degreein electrical and electronic engineering from YonseiUniversity, Seoul, Korea, in 2008, where he is cur-rently working toward the M.S. degree.

His current research interests include SRAM sta-bility, subthreshold SRAM bit-cell design, FinFETSRAM bit-cell design, and FinFET peripheral circuitdesign.

M. H. Abu-Rahma received the B.Sc. degree (withhonors) in electronics and communication engineer-ing from Ain Shams University, Cairo, Egypt, theM.Sc. degree in electronics and communication en-gineering from Cairo University, Giza, Egypt, andthe Ph.D. degree in electrical engineering from theUniversity of Waterloo, Waterloo, ON, Canada.

From 2001 to 2004, he was with Mentor Graph-ics, Egypt, where he worked on MOSFET compactmodel development and extraction. Since 2005, hehas been with Qualcomm Inc., San Diego, CA,

where he has been engaged in the research and development of low-powerembedded SRAM and CMOS circuits. He has authored and coauthored severaltechnical papers in refereed international conferences and journals. He isthe holder of one patent with ten more patents filed (pending). His researchinterests include low-power digital circuits, variation-tolerant memory design,and statistical design methodologies.

L. Ge received the B.Eng. degree from SoutheastUniversity, Nanjing, China, the M.Sc. degree fromthe National University of Singapore, Singapore, andthe Ph.D. degree from the Department of Electricaland Computer Engineering, University of Florida,Gainesville, in 2002. His doctoral research was fo-cused on the modeling and design of DG and SOICMOS devices and circuits.

From 2002 to 2008, he was with FreescaleSemiconductor CMOS Next Generation DesignFoundations, Austin, TX, where he worked on the

characterization and modeling of advanced CMOS technologies, includ-ing uniaxial stress effects. Since 2008, he has been with Qualcomm Inc.,San Diego, CA, where he is working on 28-nm SPICE modeling and technologyenablement. His current research and development interests include the model-ing and analysis of advanced CMOS devices and circuits, characterization andmodeling of uniaxial stress effects and layout effects of CMOS devices, andmodeling of nonclassical CMOS devices and circuits.

B. M. HanFrom 1989 to 1997, he was with Samsung Elec-

tronics, where he worked on the DRAM/eDRAM/GDRAM layout. From 1997 to 2000, he was withAAC, where he worked on a graphic memory lay-out. From 2000 to 2004, he was with IDT, wherehe worked on the SRAM and CAM layout. Since2004, he has been with the digital mask design teamof Qualcomm Inc., San Diego, CA. He has morethan 20 years of memory layout experience and iscurrently interested in new device technologies.

J. Wang received the B.S. and M.S. degrees inphysics from Peking University, Beijing, China, in1990 and 1993, respectively, while doing researchon e-beam lithography and a high-temperature su-perconductor Josephson junction device, and theM.S.E.E. degree from the University of Washing-ton, Seattle, in 1996. His graduate research focusedon an in situ temperature control system for waferprocessing.

In 1997, he was with Micron Technology, Boise,ID, where he worked on the process development of

many advanced memories, including stand-alone high-speed SRAM from 0.35-to 0.1-μm technology, 90-nm DRAM development, and 70-nm NAND Flashprocess development. Since 2004, he has been with Qualcomm Inc., San Diego,CA, where he is working on embedded memory solutions and is currently theManager for the memory technology group responsible for the enablement ofembedded SRAM, ROM, eDRAM, fuse, and multichip package DRAM.

G. Yeap received the B.S.E.E. (with honors),M.S.E.E., and Ph.D. degrees in microelectronicsfrom The University of Texas at Austin, Austin.

He has close to 20 years of semiconductor expe-riences in both wireless and CPU technology. From1995 to 1998, he was with AMD, where he workedas a Strategic Technologist. From 1997 to 2004, hewas with Motorola, where he worked on wirelesstechnology. Since 2004, he has been with QualcommInc., San Diego, CA, where he is currently the VicePresident of Technology.

S. O. Jung (M’00–SM’03) received the B.S. andM.S. degrees in the electronic engineering fromYonsei University, Seoul, Korea, in 1987 and 1989,respectively. He received the Ph.D. degree in elec-trical engineering from the University of Illinois atUrbana–Champaign, Urbana, in 2002.

From 1989 to 1998, he was with Samsung Elec-tronics, where he worked on specialty memories,such as video RAM, graphic RAM, and windowRAM, and merged memory logic. From 2001 to2003, he was with T-RAM Inc., where he was the

Leader of the thyristor-based memory design team. From 2003 to 2006, he waswith Qualcomm Inc., San Diego, CA, where he worked on high-performancelow-power embedded memories, process variation tolerant circuit design, andlow power circuit techniques. Since 2006, he has been an Associate Professorwith Yonsei University. His research interests include process variation tolerantcircuit design, low-power circuit design, mixed-mode circuit design, and futuregeneration memory and technology.

Dr. Jung is currently a board member of the IEEE SSCS Seoul Chapter.

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