04 cpu internals

8/13/2019 04 Cpu Internals

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November 12, 2003 Serguei Mokhov,[email protected]

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CPU Internals

SOEN228, Fall 2003


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Case: Programmed Input from Keyboard

data old data

data data

Keyboard Controller

CPU

IODR

CPU

Step 1 Step 2

Step 4Step 3

ASCII Key

copy:char IODR -> reg0 copy #0 -> IOSCR


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Case: Programmed Input from Keyboard

(2) The ready flag (ful l/empty bit) is typically a particular bit in the status

register of the I/O port.

The flag is equal to 1 iffthe data register (IODR) is holding valid data

yet to be read (consumed) by the reader. It will be reset to 0 when thereader has read the data register.

In this way, the I/O port can be used to carry out a transaction by using

busy-wait loop: each party will loop indefinitely to test the status flag

before it produces/consumes.

Drawback: Programmed I/O via busy-wait loops consume processingpower (time); for example, when the CPU executes in the busy-wait

loop, no useful work is done by the processor.

Compare CPU speed and human input speed!


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5

Interrupts and Interrupt

Handler


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Interrupts and Interrupt

Handler Programmed I/O suffers from the fact that the participants

in an I/O transfer may have greatly diversified speeds.

Using the keyboard example, we know that the system

could read thousands of times faster than the typing speedof the fastest typist.

Hence, the fast partner has to wait for the slow partner,leading to a huge waste of resources (for example,computational resources).

The asynchronybetween the synchronous computer andthe external world often requires better solutions.

Interrupts is one such a solution.


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Basic Principle (1)

The computer will assume that I/O activities

are temporally suspended (such as when the

human has not yet struck the next key) andscheduleitself to handle other

computational task (program).


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Basic Principle (2)

When I/O attention is needed, the external action

is translated into an interruptsignalthat gets into

the CPU. This serves as a trap, forcing the CPU to suspend

its current (possibly computational) program and

transfer its flow of control to an interrupt handling

subroutine.

This is equivalent to a hardwired subroutine jump.


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Basic Principle (3)

The interrupt service routine (handler) may

be chosen from a few candidates, based on

the type of interrupt received.

When finished, control could be returned to

the program that was interrupted, just like

subroutine return.


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Case: Interrupt Input from Keyboard

data old data

data data

Keyboard Controller

CPU

IODR

CPU

Step 1 Step 2

Step 4: Completion of ISRStep 3: CPU executes ISR

ASCII Key

copy:char IODR -> 0 copy #0 -> IOSCR

Interrupt CPU

CPU Acknowledges the Interrupt


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Interrupt Processing

Interrupt I/O involves the use of hardware signals:

when an I/O port needs CPU attention, an interrupt

signal is sent and later received by the CPU. The CPU can acknowledge the interrupt by returning an

INTA (interrupt acknowledge signal) and subsequently

jumps to the interrupt service routine (ISR) to

process/serve the I/O port.

The key feature is the asynchrony: the CPU is free to do

something else until attention is needed. Hence the

busy-wait is avoided.


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12

Enable keyboard

input and interrupts

Read/process

keyboard data buffer

Done?

No

Yes

Enable keyboard

input and interrupts

Go to do other useful

thingies

Interrupt Service Routine

Return from

Interrupt

Other CPU-bound process


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Key Observations

Since the CPU is freed from busy-wait, itcould be switched to perform other useful

program executions. Thus, it improves the utilizationof the

system, leading to a much better responsetime for all users.

I/O can proceed asynchronously. There is noassumption on the exact timing of events.


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Instruction Cycle and Interrupts

Instruction Cycle:

Interrupt Request (INTR) is tested at end of Cycle

If INTR is true, then a hardwired subroutine jump to the

interrupt service routine (ISR) will be used as the nextinstruction to be executed.

Notice that the current program is interruptedand the return

address is pushed on the stack as part of the subroutine call.

IF ID OF EX OS

call ISR Interrupt?

No

Yes


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Interrupt Acknowledge

1: Interrupt Service Routine:

CPU reads data from device port. 2: Interrupt Service Routine:

CPU transfer the data read to memory.

Memory

UnitCPU Device

12

Interrupt

Interrupt Acknowledge


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Interrupt Acknowledge (2)

Interrupt Acknowledge(INTA) is the signal from the

CPU indicating that the CPU is ready to handle the

interrupt.

Typically, this signal is used to handshake with the devicethat has caused the interrupt so that the device can identify

itself in the form of an interrupt vector.

The interrupt vector is received by the CPU and is used

as a pointer or address to the needed interrupt serviceroutine.

Problem:

How can the CPU scale up to the number of external interrupts?


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Multiplicity of Interrupt

Sources Interrupts can come from multiple devices or sources. In a typical computer system, interrupts could be caused

by:

Power Failure

Timer

I/O Devices such as disks, terminals, printers etc.

Hardware error conditions (parity error, etc.)

Software error conditions (divide-by-zero, etc.)

It raises a couple of issues: Priority

Interrupt Identification


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Priority Can we allow an interrupt to interrupt an interrupt handler? Why?

Which interrupt should be served next?

Usually, priorities can be assigned to various sources of interrupt accordingto some criteria, such as the penalty of not reacting in time, or the expectedreturn if served.

So, the following priority assignment is quite typical:

Power failure; Timer; Error; I/O.

Each sub-class of priority may correspond to a single bit of signalsent to the CPU interface.

This is the interrupt signal of that sub-class.

In implementation, the instruction cycle of the CPU is changed such that atthe end of a cycle, the existence of an unmasked(enabled) interrupt forcesthe CPU to execute the equivalence ofjump:subroutine interrupt_handler.


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Interrupt Identification

The choice of interrupt_handlercan beresolved in a number of ways.

In general, the CPU must identify the source of theinterrupt (with the highest priority).

This identification can be achieved using

Software polling: the interrupt handler can beprogrammed to poll through the various I/O interfaces(status registers), highest priority interface first.

Once it comes across an interface that indicates itsinterrupt status, then the handler proceeds to executethe corresponding handler for that interface.


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Software Polling Flowchart

ISR for 1Interface 1

ready?

ISR for 2

Interface 2

ready?

ISR for NInterface Nready?

Return to the Interrupted Program

Yes

Yes

Yes

No

No

No


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Hardware Polling (Daisy Chain) The polling can be done by hardware in which the interrupt requests

from all interfaces (devices) are ORed together to interrupt theCPU.

When the CPU acknowledges to the interrupt via INTA (interruptacknowledge), the latter signal is allowed to propagate through theinterfaces arranged in a daisy chain, with the highest priorityinterface receiving the INTA first.

An interface propagates INTA to its next lower priority neighboronly if it has not generated an interrupt request; otherwise, it willstop the propagation and identify itself to the CPU (for example, by

depositing its ID onto the system bus). Notice that INTR and INTA represent an instance of the 4-phase

handshaking solution explained earlier.


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Daisy Chain Priority Scheme INTR: Interrupt Request (to CPU)

INTA: Interrupt Acknowledge (from CPU)

INTA is propagated from device 1 to device N, and it stops at the first device that hasgenerated an interrupt.

Device

Interface N

Device

Interface 2

Device

Interface 1

To Data Bus

Interrupt Vector

INTR

INTR1 INTR1 INTRNControl Bus

INTA


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Interrupt Vector

A typical way is to associate an in terruptvector with entriesfor each interrupt source.

Entries in this interrupt vector actually point to(directly or indirectly) the starting address ofthe required interrupt service routine.

For example, the interrupt handler for thekeyboard is immediately executed once theinterrupt source is known to the CPU.


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Enabling/Disabling of

Interrupts Even though the use of priority in some sense already disables

lower priority interrupts from interrupting a higher priority

interrupt service routine, it is often necessary to disable certain

interrupts dynamically.

An example would involve an input process and an output process

from before.

The input process reads a character from the keyboard and the output

process writes the character to the display. The input and output must be done in a sequence alternately.

To synchronize the two processes, we could use the enabling/disabling

feature in interrupts.


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Enabling/Disabling of

Interrupts (2)

The Enabling/Disabling can be accomplishedusing MASKING.

A mask flag is associated with every interrupt

source. An interrupt will be received by the CPU only if

it has notbeen masked off, i.e., the associatedmask has not been reset.

The follow up diagram illustrates such a maskedinterface.


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Priority Encoder Resolution of

Interrupts

PriorityEncoder

1 2 3 ... N

INTR1

INTR2

INTRN

:

:

:

:INTR

INTA

Interrupt Mask Register

Eg: Intel 82C59A


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Context Switching (2) Since the handler will use the registers and even destroy their

content, it will be important to preserve these register contexts so

that when the interrupted program is returned, the original context

is still available and intact.

So, an assume-nothing interrupt handler will adopt the following

structure:interrupt_handler: push reg0

push reg1

::::

take care of service

pop reg7pop reg6

::::

return


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Drawbacks?

Is there any drawback using interrupt processing?

Interrupt is asynchronous and frees the CPU to perform

other tasks via proper context switching.

However, there is a price being paid every time context

switching takes place.

Alternative:

Why not free the CPU entirely from doing the work ofthe interrupt handler, except once-in-a-while?


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November 12, 2003 Serguei Mokhov,[email protected] 29

Direct Memory Access

(DMA)


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Motivation

I/O transfer often involves transferring a large

chunk of data to or from the computer, for

example, disk transfer involves multiple sectors. Much of the interrupt handler for such a disk

transfer involves moving memory pointers and

transferring the data until the needed number of

bytes are transferred.

The software managed transfer can be replaced by

a hardware component called DMA con trol ler .


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DMA Controller

A DMA controller is a hardware interfacecontaining:

data register:

data to be transmitted

status and control register: status and control

word/byte count register:

remaining word count

memory address register:

next memory location

device address register:

next device address


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A Typical DMA Control ler

Data

Count

Data

Register

Address

Register

ControlLogic

Data Lines

Address Lines

DMAR

DMAAINTRReadWrite


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DMA Controller (2) A DMA controller (DMAC) can be considered as an intelligent I/O

port.

We will illustrate its operation via a disk transfer example.

Reading 1K byte from Disk Address (1234) to RAM address

(1000).

The CPU executes only the following:

copy #1234h -> device_address_register;

copy #1000h -> memory_address_register;

copy #1024 -> word_count_register;

copy #1 -> device_status_register;

:::::

:::::

:::::


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DMA Controller (3)

The CPU is involved only as a master; it initializes thedisk address to be 1234h, followed by the target

storage address in RAM to be 1000h and the word

count of 1024 in the word count register.

Then it writes #1 into the device_status_register. Thistells the disk controller (the DMAC) to start reading.

Afterwards, the CPU moves on to do whatever else is

there to do.

As usual, the CPU can be interrupted later if attention

is needed.


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Behavior of the DMAC

The DMAC proceeds to control the disk driveto access the desired sector (address 1234h).

Afterwards, it proceeds to conduct the transfer

of 1024 bytes from disk to RAM starting fromRAM location 1000h.

The transfer is conducted by stealing memory

cycles from the CPU (the memory isconnected to both the CPU and the DMAC viaSystem Bus).


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Comparing DMA with Interrupt I/O You pay a price in using DMA. It incurs additional

hardware and hence cost.

What have you gained?

Suppose the total transfer time of 1K bytes from the disk takes

1 ms.

During this interval, the CPU is not paying any attention to the

DMAC.

If interrupts are used, the CPU will be interrupted 1024 times.

Suppose the interrupt handler for the disk takes 0.0005 ms toexecute.

The CPU will have to spend 0.512 ms to serve the interrupts.

Equivalently, its availability is reduced by 50%.

C i DMA ith I t t I/O


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Comparing DMA with Interrupt I/O

Notice also that if the external device is fast, interrupt processing

to update the external device may be too slow: interrupt handler involves a software solution that is usually slower than its

hardware counterpart.

As an immediate example, you can redo the comparison assuming that the

disk completes the transfer in 0.5 ms instead of 1 ms. What will happen?

Memory

UnitCPU Device

DMA

DMA

System


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System

Bus

Structure

MemoryCPU

Interrupt

I/O

Data Bus

Address Bus

Control Bus

DMA I/OInterrupt

I/O

Programmed

I/O

7 1 2 6 5 4 3

6 5 4 37 2 1

3 4 1

4

2 7

7 2 1

2 7 1

:::

Daisy Chain

1: Data2: Address3: INTR4: INTA5: DMAR6: DMAA7: Read / Write


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N b 12 2003 S i M kh 39

Library for PA4

/pkg/nasm/lib/libcomp228.a

04 cpu internals

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