04 2to4 decoder examples

7/28/2019 04 2to4 Decoder Examples

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VHDL Programming Styles

1. Structural- define explicit components and the connectionsbetween them

- like a text version of a schematic

2. Data Flow-assign expressions to signals-can include when and select statements

3. Behavioural/Algorithmic- write an algorithm that describes the circuits output- may not be synthesizable- may lead to a very large inefficient circuit


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2 to 4 decoder

IN0

IN1

EN

Y0

Y1

Y2

Y3

EN IN1 IN0 Y3 Y2 Y1 Y0


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-- 2 to 4 decoder, structural style; DO NOT USE AT THE GATE LEVEL

library IEEE;use IEEE.std_logic_1164.all;

entity dec2to4 isport ( IN0, IN1, EN : in std_logic; -- 2 bit coded input plus enable;

Y0, Y1, Y2, Y3 : out std_logic); -- 4 bit decoded outputend entity dec2to4;

architecture dec2to4_s of dec2to4 is Will not work in Quartussignal IN0_L, IN1_L : std_logic; but you will see this in

Begin generic VHDL texts.U1: inv port map (IN0_L, IN0);U2: inv port map (IN1_L, IN1);

U3: and3 port map (Y0, IN0_L, IN1_L, EN);U4: and3 port map (Y1, IN0, IN1_L, EN);U5: and3 port map (Y2, IN0_L, IN1, EN);U6: and3 port map (Y3, IN0, IN1, EN);

end architecture dec2to4_s;


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-- 2 to 4 decoder, dataflow style

-- 2 bit coded input plus enable; 4 bit decoded output-- if EN is 0, then output is 0000, else if EN is 1-- Input Output

-- 00 0001-- 01 0010-- 10 0100-- 11 1000

library IEEE;use IEEE.std_logic_1164.all;

entity dec2to4 isport ( IN0, IN1, EN : in std_logic;

Y0, Y1, Y2, Y3 : out std_logic);end entity dec2to4;

architecture dec2to4_df of dec2to4 isbeginY0


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Selected signal assignment signal assigned one of several values based on

a selection criterion

WITH expression SELECTsignal_name


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-- 2 to 4 decoder, behavioural style

-- using selected signal assignment

library IEEE;

use IEEE.std_logic_1164.all;

entity dec2to4 isport ( IN0, IN1, EN : in std_logic;

Y : out std_logic_vector (3 downto 0));end entity dec2to4;

architecture dec2to4_b of dec2to4 issignal ENA : std_logic_vector (2 downto 0);

beginENA


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Process looks like software programming

in architecture body

encloses a set of sequential statements

(everything else is concurrent)

if, case, and loop constructs can onlyappear inside a process


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Process syntax

[process_label:]

PROCESS (sensitivity list)

variable declarations

BEGIN

simple signal assignments

variable assignments

IF

CASE

LOOP

END PROCESS [process_label];


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IF

IF condition THEN

;

ELSE;

END IF;

IF condition1 THEN

;

ELSIF condition2 THEN;

ELSE

;END IF;


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CASE

CASE expression ISWHEN constant value1 =>

statement;

;WHEN constant value2 =>

statement;;

END CASE;

when clauses must cover all the cases; can use OTHERS


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-- 2 to 4 decoder, behavioural style; uses process; same library and enti ty

architecture dec2to4_b2 of dec2to4 issignal Inputs : std_logic_vector (1 downto 0);

beginInputs Y Y Y Y Y


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Process operation recap

when there is a change in the value of anysignal in the process sensitivity list,

process becomes active once active, statements in process are

evaluated sequentially

any assignments in the process are notvisible outside the process until allstatements have been evaluated


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Revisit two vats & a buzzer

>30C

low level

buzzer

>25C

>30C

low level

>25C

0

1

vat 0

vat 1 select vat 1

select vat 0

+V

library ieee;use ieee.std_logic_1164.all;

entity vat_buzzer is

port (v0over25, v0over30, v0low,

v1over25, v1over30, v1low,sel : in std_logic;buzzer : out std_logic );

end entity vat_buzzer;

architecture alternate ofvat_buzzer isbeginbuzzer

04 2to4 decoder examples

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