03 computer function instruction and execute putra
TRANSCRIPT
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William Stallings
Computer Organization
and Architecture
8th Edition
Chapter 3Top Level View of ComputerFunction and Interconnection
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Program Concept
Hardwired systems are inflexible
General purpose hardware can dodifferent tasks, given correct controlsignals
Instead of re-wiring, supply a new set ofcontrol signals
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What is a program?
A sequence of steps
For each step, an arithmetic or logicaloperation is done
For each operation, a different set of
control signals is needed
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Function of Control Unit
For each operation a unique code isprovided
e.g. ADD, MOVE
A hardware segment accepts the code and
issues the control signals
We have a computer!
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Components
The Control Unit and the Arithmetic andLogic Unit constitute the CentralProcessing Unit
Data and instructions need to get into the
system and results outInput/output
Temporary storage of code and results isneeded
Main memory
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Computer Components:
Top Level View
Thumb drive
Printer
Hard disk
CD-ROM
Network adapter
Graphic card
Etc..
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Instruction Cycle
Two steps:
Fetch
Execute
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Fetch Cycle
Program Counter (PC) holds address ofnext instruction to fetch
Processor fetches instruction frommemory location pointed to by PC
Increment PCUnless told otherwise
Instruction loaded into InstructionRegister (IR)
Processor interprets instruction andperforms required actions
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Execute Cycle
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processingSome arithmetic or logical operation on data
Control
Alteration of sequence of operationse.g. jump
Combination of above
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Let look at the example of how CPU run
the program
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The CPU structures
0001 10100100000
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The CPU structures
0001 110100100000
0011 101010001010
0111 101111010100
..
..
..
..
?
?
The easier way for us to write instruction
is to use hexadecimal
1940
3370
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Example of Program Execution
1940
5941
2941
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Instruction Cycle State Diagram
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William Stallings
Computer Organization
and Architecture8th Edition
Chapter 3Top Level View of ComputerInterrupt
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Interrupts
Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence ofprocessing
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error
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Program Flow Control
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Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:Suspend execution of current program
Save context
Set PC to start address of interrupt handlerroutine
Process interrupt
Restore context and continue interruptedprogram
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Transfer of Control via Interrupts
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Instruction Cycle with Interrupts
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Program Timing
Short I/O Wait
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Program Timing
Long I/O Wait
I t ti C l ( ith I t t )
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Instruction Cycle (with Interrupts) -
State Diagram
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Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilstprocessing one interrupt
Interrupts remain pending and are checkedafter first interrupt has been processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by
higher priority interruptsWhen higher priority interrupt has been
processed, processor returns to previousinterrupt
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Multiple Interrupts - Sequential
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Multiple Interrupts Nested
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Time Sequence of Multiple Interrupts
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William Stallings
Computer Organization
and Architecture8th Edition
Chapter 10Instruction Sets:
Characteristics and Functions
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What is an Instruction Set? (2)
The complete collection of instructions
that are understood by a CPU
Machine Code
Binary
fieldAddressing informationOperation
8 bits 24 bits
Operation Operand
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Elements of an Instruction
Operation code (Op code)
Do this
Source Operand reference
To this
Result Operand referencePut the answer here
Next Instruction Reference
When you have done that, do this...
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Instruction Cycle State Diagram (1)
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Instruction Cycle State Diagram (2)
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Instruction Representation (1)
In machine code each instruction has a
unique bit pattern
For human consumption (well,programmers anyway) a symbolic
representation is usede.g. ADD, SUB, LOAD
Operands can also be represented in thisway
ADD A,B
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0001 110100100000
0011 101010001010
0111 101111010100
..
..
..
..
?
?
The easier way for us to write instruction
is to use hexadecimal
1940
3370
Instruction Representation (2)
LOAD
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Simple Instruction Format
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Instruction Types
Data processing
Data storage (main memory)
Data movement (I/O)
Program flow control
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Number of Addresses (a)
3 addresses
Operand 1, Operand 2, Result
a = b + c;
ADD a, b, c
Needs very long words to hold everything
ADD a b cOperation Operand
Operation Source 1 Source 2 Destination
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Number of Addresses (b)
2 addresses
One address doubles as operand and result
a = a + b
ADD a, b
Reduces length of instruction
Requires some extra work
Temporary storage to hold some results
Operation Source Destination
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Number of Addresses (c)
1 address
LOAD B = AC B
Implicit second address
Usually a register (accumulator)
Common on early machines
Operation Source/Destination
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Number of Addresses (d)
0 (zero) addresses
All addresses implicit
Uses a stack
e.g. push
pop
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How Many Addresses
More addresses
More complex (powerful?) instructions
More registers
Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
Less complex (powerful?) instructions
More instructions per program
Faster fetch/execution of instructions
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Types of Operand
Addresses
Numbers
Integer/floating point
Characters
ASCII etc. Logical Data
Bits or flags
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Case study: x86
It is a Intel 8086 CPU
It being implemented on Intel, Cyric, AMD
It has instruction sets
The architecture used until today such as
in Intel pentium, Intel Core 2 & etc
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Case study: x86 Data Types
8 bit Byte
16 bit word 32 bit double word
64 bit quad word
128 bit double quadword Addressing is by 8 bit unit
Words do not need to align at even-numbered address
Data accessed across 32 bit bus in unitsof double word read at addresses divisibleby 4
Little endian
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x86 Numeric Data Formats
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Types of Operation
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control
Transfer of Control
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Data Transfer
Specify
Source
Destination
Amount of data
May be different instructions for differentmovements
e.g. IBM 370
Or one instruction and different addresses
e.g. VAX
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Arithmetic
Add, Subtract, Multiply, Divide
Signed Integer
Floating point
May include
Increment (a++)Decrement (a--)
Negate (-a)
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Logical
Bitwise operations
AND, OR, NOT
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Conversion
E.g. Binary to Decimal
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Input/Output
May be specific instructions
May be done using data movementinstructions (memory mapped)
May be done by a separate controller
(DMA)
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Transfer of Control
Branch
e.g. branch to x if result is zero
Skip
e.g. increment and skip if zero
ISZ Register1Branch xxxx
ADD A
Subroutine call
c.f. interrupt call
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Branch Instruction
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Nested Procedure Calls
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Byte Order Names
The problem is called Endian
The system on the left has the leastsignificant byte in the lowest address
This is called big-endian
The system on the right has the leastsignificant byte in the highest address
This is called little-endian
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Example of C Data Structure
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Alternative View of Memory Map
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William Stallings
Computer Organization
and Architecture8th Edition
Chapter 11Instruction Sets:
Addressing Modes and Formats
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Definition of this chapter 11
How is the address of an operand
specified How are the bits of an instruction
organized to define the operand address
and operation of that instruction? Chapter 10 is on:
What instruction does.
Examine types of operands and operations
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Addressing Modes
Immediate
Direct
Indirect
Register
Register Indirect Displacement
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Immediate Addressing
Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand No memory reference to fetch data
Fast
Limited range
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Immediate Addressing Diagram
OperandOpcode
Instruction
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Direct Addressing
Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand Single memory reference to access data
No additional calculations to work outeffective address
Limited address space
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Direct Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
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Indirect Addressing (1)
Memory cell pointed to by address field
contains the address of (pointer to) theoperand
EA = (A)
Look in A, find address (A) and look there foroperand
e.g. ADD (A)
Add contents of cell pointed to by contents of
A to accumulator
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Indirect Addressing Diagram (2)
Address AOpcodeInstruction
Memory
Operand
Pointer to operand
EA = (A)
Look in A, find address (A)
and look there for operand
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Indirect Addressing (3)
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself Multiple memory accesses to find operand
Hence slower
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Register Addressing (1)
Operand is held in register named in
address filed EA = R
Limited number of registers
Very small address field neededShorter instructions
Faster instruction fetch
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Register Addressing Diagram (2)
Register Address ROpcode
Instruction
Registers
Operand
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Register Addressing (3)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming orcompiler writing
N.B. C programming
register int a;
c.f. Direct addressing
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Register Indirect Addressing
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to bycontents of register R
Large address space (2n) One fewer memory access than indirect
addressing
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Register Indirect Addressing Diagram
Register Address ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Di l t Add i
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Displacement Addressing
EA = A + (R)
Address field hold two valuesA = base value
R = register that holds displacement
or vice versa
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Displacement Addressing Diagram
Register ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Address A
+