02 mn1780eu09mn 0001 bsc architecture

BSC Architecture Siemens

MN1780EU09MN_0001 © 2001 Siemens AG

1

Contents

1 Functions 3

1.1 Traffic Channel Switching 5

1.2 Signaling Information Processing 7

2 Modules 11

2.1 Switching Network 15

2.2 Peripheral Processors 16

2.3 Telephony Processor 19

2.4 Administrative Processor 20

2.5 Line Termination 22

2.6 Hard Disk 24

2.7 O&M Interface 26

2.8 Clock Unit 29

2.9 Packet Control Unit 30

2.10 Bus Systems 32

3 Rack Configuration 33

3.1 Hardware Compatibility 34

3.2 Rack Layout 35

3.3 Base Subrack 39

3.4 Expansion Subrack 42

4 Exercises 45

BSC Architecture

Siemens BSC Architecture

MN1780EU09MN_0001

© 2001 Siemens AG

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3

1 Functions


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The Base Station Controller BSC is the "brain" of the Siemens Base Station SBS.

The BSC is responsible for

��Traffic channel switching,

��Signaling information processing,

��(Central) Operation & Maintenance handling and alarm monitoring.

The BSC features interfaces to carry payload (and signaling) to

��Base Transceiver Station Equipment BTSE,

��Transcoder and Rate Adapter Unit TRAU,

��Mobile Switching Center MSC,

��Serving GPRS Support Node SGSN

as well as interfaces to provide Operation and Maintenance from

��Operation and Maintenance System OMC-B,

��Local Maintenance Terminal LMT.

Note: With the LMT connected to BSC (local or remote), all network elements controlled from this BSC (all BTSE and TRAU) may be administered.

BTSE

Link

Interface

SN Link

Interface

BSC

Control

LMTOMC

BSC

SGSN

BTSETRAU

PCU

Fig. 1 BSC architecture



5

1.1 Traffic Channel Switching

The BSC switches

��circuit-switched traffic (e.g. voice) coming from the MSC via the TRAU and

��packet-switched traffic (e.g. GPRS data) coming from the SGSN

��to the "serving" BTSE.

Both PCM30 and PCM24 lines are supported (by the same link interface modules).

BTSE

BTSE

TRAULink

Interface

Link

Interface

SN-1BSC

SGSNLink

Interface

Link

Interface

.

.

.

.

.

.

SN-0

Abis

via PCMB

Asub

via PCMS

Gb

via PCMG

PCM30/24PCM30/24

Fig. 2 Asub, Abis and Gb interfaces


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The switching of traffic channels is the task of the Switching Network SN operating with 16 kbit/s sub channels (e.g. 16 kbit/s = 13 kbit/s + 3 kbit/s for Full Rate speech).

While the BSC is transparent for circuit-switched traffic, the (packet-switched) traffic coming from SGSN is adapted by the Packet Control Unit PCU to the 16 kbit/s sub channels used on Abis (e.g. 9.05 kbit/s for CS-1).

TRAU

BSC

SGSN

.

.

.

.

.

.

Asub

Abis

Link

Interface

Link

Interface

SN-1

LinkInterface

LinkInterface

SN-0

3 2 1 0 3 2 1 0

4x16 kbit/s

Traffic Channels4x16 kbit/s

Traffic Channels

Gb

Permanent Virtual

Connection PVC

in Frame Relay

(„64 kbit/schannelized“)

3 2 1 0

4x16 kbit/s

Packet DataChannels

Packet

Control Unit

Fig. 3 BSC traffic channel switching



7

1.2 Signaling Information Processing

The BSC (PCU) processes (external) signaling information coming from the core network:

��CCSS#7 signaling between MSC and BSC (for circuit-switched traffic) and

��BSSGP related signaling between SGSN and PCU (for packet-switched traffic),

as well as SBS (internal) signaling:

��O&M information and traffic channel signaling to BTSE and TRAU (via LAPD protocol).

BTSE

BSC TRAU MSC

LAPDLAPD

4x16 kbit/s TCH

CCSS 7

64 kbit/s

CCSS 7

64 kbit/s

1x16 kbit/s TCH

Abis Asub A

SGSNGb

BSS GPRS Protocol

(over Frame Relay)

PCU

Fig. 4 SBS external and internal signaling


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Signaling Time Slots

The following types of signaling time slots are used:

��O&M signaling on Abis for the control of the BTSE by the BSC using the LAPD protocol ("LPDLM"),

��Traffic channel signaling to BTSE on Abis using the LAPD protocol ("LPDLR", LPDLM and LPDLR do not have to travel on the same time slot),

��O&M signaling on Asub for the control of the TRAU by the BSC using the LAPD protocol ("LPDLS"),

��Traffic channel signaling on A / Asub between BSC and MSC using CCSS#7 protocol ("SS7L").

For BTSplus max 8 LAPD time slots (4 of which are active) are available.

The BSS GPRS Protocol BSSGP is carried on the same Permanent Virtual Circuit between BSC and SGSN that carries the packet data traffic (no dedicated signaling timeslot is required).

BTSE TRAU

PCMB PCMS

Abis AsubPCMA

A

MSC

SGSN

PCMG

Gb

BSSGP

BSC

LPDLM&LPDLR LPDLS CCSS7

PCU

Um

Fig. 5 Interfaces and signaling



9

The signaling for circuit-switched traffic (CCSS#7) passes through the TRAU transparently (no transcoding) and is evaluated by the BSC. The BSS Application Part BSSAP comprises

��signaling between MS and MSC (passing transparently through the BSC: call control and mobility management) as well as

��BSS Management Application Part (for radio resource management, terminated on the BSC).

BTSE

BSC TRAU MSC

LAPD

LAPD

4x16 kbit/s TCH

CCSS 7

64 kbit/s

CCSS 7

64 kbit/s

1x16 kbit/s TCH

Abis Asub A

Fig. 6 CCSS#7signaling


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Time slot pattern on PCMA

Any sub slots on PCMS that are not subject to transcoding/rate adaptation by the TRAU cause time slots on PCMA to remain empty. Important links that are not transcoded carry:

��LAPD signaling (LPDLS),

��CCSS#7 signaling,

��Operation and Maintenance Link OMAL (X25A, if used).

Additionally, High-Speed Circuit-Switched Data (TRAU pooling) and Nailed-up Connections through the TRAU cause empty time slots on PCMA.

The distribution of time slots on PCMA depends on the configuration chosen. Generally speaking, the system clusters the empty time slots "at the back" of the PCMA lines.

BTSE

BSC TRAU MSC

LAPD

CCSS 7

64 kbit/s

CCSS 7

64 kbit/s

Abis Asub A

Not used

LAPD

Fig. 7 CCSS7 and LAPD signaling



11

2 Modules


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13

The different BSC modules are shown below:

Line Termination

QTLP

Line Termination

Line Termination

SwitchingNetwork

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

BS

SG

P

PP

XX

BS

SG

P

PP

XX

BS

SG

P

PP

XX

LA

P D

PP

XX

CC

S 7

PP

XX

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 8 BSC internal architecture


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The following table summarizes the BSC modules (for BSC High Capacity 1st Step, the modules in brackets are used in BSC "classic"):

Abbreviation Full Module Name

SNAP Switching Network

(SN16) (Switching Network 16 kbit/s)

PPXX Peripheral Processor (all-purpose)

(PPCC) (Peripheral Processor for CCSS7)

(PPLD) (Peripheral Processor for LAPD)

(PPCU) (Processor for Packet Control Unit)

TDPC Telephony and Distributor Processor Circuit

MEMT Memory of the TDPC

MPCC Main Processor Control Circuit

UBEX Universal Bus Extender Board

QTLP Quad Trunk Line Peripheral Board

IXLT Interface to LMT/OMC

PLLH Phase Locked Loop High Performance

PWRD Power Distributor (Base Shelf)

EPWR Expansion Power Supply (Expansion Shelf)



15

2.1 Switching Network

The Switching Network SN comprises a single stage switching matrix which

��switches, under the control of the Administrative Processor, the circuit-switched traffic channels between TRAU and BTSE,

��switches, under the control of the Administrative Processor, the packet data channels between BTSE, SGSN and PCU ,

��routes the signaling timeslots (LAPD and CCSS7) to/from the peripheral processors (acting as PPXL) via semi permanent connections (nailed-up connections),

��is protected by 1:1 redundancy (hot standby).

The capacity of the switching matrix is 8 x 8 Mbit/s for SNAP and 4 x 2 Mbit/s for SN16.

BTSE

BTSE

LPDLM/R

TRAU

SGSNLine

Termination

Line

Termination

Line

TerminationLine

Termination

L

A

P

D

C

C

S

7

Switching

Network

Telephony

Processor

Peripheral Processors

LPDLS

CCS7

BSC

BSSGPP

C

U

B

S

S

G

P

B

S

S

G

P

Fig. 9 Switching network


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2.2 Peripheral Processors

The Peripheral Processors of type PPXX are multifunctional boards

��handling LAPD and circuit-switched signaling (PPXL, located in base shelf) as well as

��acting as Packet Control Unit (PPXU, located in extension shelf).

Load Sharing

The PPXX work in load sharing, i.e. the number of PPXX boards required follows from the number of boards needed for a given bandwidth plus the number of boards for redundancy.

PPXU: An additional PPXX is required to guarantee the bandwidth in case of board failure.

PPXL: In normal operation, 2 PPXX boards share the load. In case of failure, the remaining PPXX takes over the load of the failed board.

Capacity

The LAPD / CCSS#7 signaling capacity (per module) is given by X+0.25xY+Z<=128

(X = number of 64 kbit/s links, Y = number of 16 kbit/s links, Z = number of CCSS#7 links, max 8).

The current backplane (BR6.0) supports 2 x 2 Mbit/s of packet data traffic (per module).

Example

6 PPXX in Extension Shelf are used for GPRS providing a bandwidth of 20 Mbit/s ("5+1" protected, load-sharing!) or 24 Mbit/s unprotected.

2 PPXX in Base Shelf are used for CCSS#7 and LAPD signaling providing (together max) 248 LAPD and 8 CCSS#7 links.

History

PPXX handle functions performed by three different boards before:

��PPCU acting as PCU, operating in cold standby (1:1),

��PPLD responsible for LAPD signaling, working in hot standby (n:1) and

��PPCC handling CCSS#7 signaling in load sharing (1+1).



17

2.2.1 CCSS#7 Signaling

The Peripheral Processor for CCSS7, PPXX in PPXL operation (former PPCC):

��handles CCSS7 MTP layer 2 for the signaling towards the MSC (A interface). The layer 2 is responsible for - error detection - error correction - recovery of a link failure.

PPCC boards (in base shelf) support max 4 CCSS#7 (64 kbit/s) each (max 8 CCSS#7 channels in total).

Line TerminationQTLP

Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

B

S

S

G

PO

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC

Telephony Processor

O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Peripheral

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 10 Peripheral processor for CCSS7


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2.2.2 LAPD Signaling

The Peripheral Processor for LAPD, PPXX as PPXL (former PPLD):

��is responsible for handling the level 2 LAPD protocol (used for signaling on the Abis and Asub interfaces):

- O&M signaling between BSC and TRAU: LPDLS

- O&M signaling between BSC and BTSE: LPDLM

- Radio signaling between BSC and BTSE (TRX): LPDLR

The PPLD handles up to 8 physical signaling links, both for 16 kbit/s or 64 kbit/s, and up to 64 Terminal Endpoint Identifiers (TEI). PPLD are protected by n:1 redundancy (active-hot standby, no load-sharing)

Line Termination

Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC

Telephony Processor

O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Peripheral

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 11 Peripheral processor for LAPD



19

2.3 Telephony Processor

The Telephony Processor is composed of two circuit boards:

��TDPC: Telephony and Distributor Processor Circuit,

��MEMT: Memory of the Telephony Processor which is a memory expansion for the TDPC and behaves as a mailbox for MPCC - TDPC message interchange.

The Telephony Processor

��handles all signaling functions above MTP layer 2 (except for measurement preprocessing, which is performed in the BTSE) and all application processes related to call control, radio resource management, and mobility management,

��is connected via an internal bus (Telephony System Bus) to the PPXL (for LAPD and CCSS#7 signaling),

��is protected by hot standby boards (1:1).

Line Termination

Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC

Telephony Processor

O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Periphal

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 12 Telephony processor (TDPC, MEMT)


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2.4 Administrative Processor

The Administrative Processor is comprised of two boards:

��MPCC: Main Processor Control Circuit,

��UBEX: Universal Bus Extender board which interfaces MPCC to switching network, clock, peripheral processors, and line terminations.

The administrative processor

��controls the connections of the Switching Network on the basis of the Telephony Processor messages,

��handles traffic and performance measurements,

��is responsible for hardware configuration,

��is responsible for diagnostic and maintenance management,

��performs software download,

��is protected by hot standby boards (1:1).



21

Line Termination

Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC

Telephony Processor

O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Peripheral

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 13 Administrative processor (MPCC, UBEX)


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2.5 Line Termination

The Quad Trunk Line Peripheral boards QTLP provide the connections to the

��BTSE (PCMB),

��TRAU (PCMS) and

��SGSN (PCMG)

via standard 2 Mbit/s digital lines (coaxial or 4-wire copper).

QTLP is used together with SNAP (or SN16).

QTLP are n:1 protected (2:1 in base, 7:1 in extension shelf, hot standby).


Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

XX

B

S

S

G

P

P

P

XX

B

S

S

G

P

P

P

XX

LA

P D

P

P

X

X

CC

S 7

P

P

X

X

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 14 Line termination QTLP



23

QTLP is also called LICD in the BSC database.

A QTLP features 4 ports with 2 terminals each. Thus, QTLP supports

��8 PCMx lines (PCMB, PCMS, PCMG) in star configuration,

��4 PCMB loops or

��equivalent combinations.

A port is used in transparent mode when both terminal A and terminal B are used independently. In selection mode, only one of the two terminals (A or B) is used.

QTLP

TRAU 1

TRAU 3

TRAU 2

BTSE 2

BTSE 1

BTSE 3

BTSE 4

Port 0

Port 1

Port 2

Port 3

A

A

A

A

B

B

B

B

Fig. 15 Mixed configuration of QTLP (ports 0 ... 2: transparent mode, port 3: selection mode)


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2.6 Hard Disk

The Hard Disk was originally located on the module DK40 ("Disk 40 Mbytes"). By now, the BSC's redundant hard disks are "on board" the MPCC modules.

The Hard Disk is used for storing all SBS software (incl. BTSE and TRAU software) and configuration data (BSC database) to allow a fast restart without download from the OMC.

The Hard Disk is updated every time the database is changed. For redundancy, data are written on both copies.

Note: The left DK40 module ("copy 0") is still present because it also carries the Alarm Circuit controlling the BSC Fuse and Alarm Panel.

DK 40


Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

GP

P

P

X

X

B

S

S

GP

P

P

X

X

B

S

S

GP

P

P

X

X

L

A

P

D

P

PX

X

C

C

S

7

P

PX

X

MEMT TDPC


O&M

Interface

IXLT

DK 40

to OMC

to LMT

. . . Peripheral

Processors

Hard Disk

Administrative

Processor

UBEX

MPCC

Hard Disk

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 16 Hard Disk



25

Directories

The Hard Disk contains a directory tree.

For software and database download (e.g. in case of upgrade), the following directories are used:

��SWH_DIR/RSUSWLH/n: for storing the software load "n",

(e.g. n=0 for BSC, n=1 for BTSE, n=2 for TRAU etc).

��SWH_DIR/RSUDB/m: for storing the database file "m",

(note: binary database files are named DBFILE.DBA)

TRACE_CTR

TRACE_IMSI

SWH_DIR/RSUDB/0

SWH_DIR/RSUSWLH/2

SWH_DIR/RSUSWLH/1

SWH_DIR/RSUSWLH/0

REMINV

READY_MEAS

READY_CTR

BSC Event Log Files

Perform. Measurem. (active)

CTR Measurements (for upload)

Cell Traffic Records

IMSI Traces

And more . . .

BSC database

Remote Inventory Files

BSC software

BTSM software

TRAU software

Perform. Measurem. (for upload)

MEASURE_DIR

LOG

. . .

. . .

Fig. 17 System directories on Hard Disk


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2.7 O&M Interface

The Interface X.25 and Local Maintenance Terminal IXLT connects the administrative processor to the operation and maintenance center OMC-B and to the local maintenance terminal LMT.

IXLT is protected by a (cold) standby module.


Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC

Telephony Processor

O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Peripheral

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 18 O&M interface on IXLT



27

The proprietary interface between LMT and BSC (T interface) is based on X.21/V.11 using LAPB and HDLC protocol.

MSC

BTSE

BSC

LMT

IXLT

X.21/V.11

TRAU

SBS

Fig. 19 Connection BSC - LMT


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The connection to the OMC can be realized either by

��a dedicated link through a X.25 packet data network PSDN or by

��a 64 kbit/s time slot on PCMA/PCMS (nailed-up connection through the MSC).

Two independent O-Links are supported (active-cold standby).

BTSE

BSC

IXLTTRAU

MSC

SIEMENS

NIXDORF SIEMENS

NIXDORF SIEMENS

NIXDORF

PSDNX.25 Line

nailed-up

connection

OMC-B

SBSNo transcoding

64 kbit/s

64 kbit/s

64 kbit/s

Fig. 20 Connection BSC - OMC



29

2.8 Clock Unit

The Phase Locked Loop High Performance PLLH clock:

��is based on a high stability quartz oscillator that provides all of the system timing

��works in free running mode, or synchronized to external clock sources

��relies on two identical redundant boards PLLH working in master/slave configuration.


Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

S

S

G

P

P

P

L

D

B

S

S

G

P

P

P

X

X

B

S

S

G

P

P

P

X

X

L

A

P

D

P

P

X

X

C

C

S

7

P

P

X

X

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . . Peripheral

Processors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 21 Clock PLLH


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2.9 Packet Control Unit

The Packet Control Unit required for GPRS is located in the BSC.

The main PCU functions are

��Radio channel management and

��Protocol conversion between standard BSS GPRS protocol BSSGP (over Frame Relay, on Gb) and proprietary Abis protocol.

While the Gb interface has multivendor capabilities, the Abis interface is proprietary using a PCU frame format (an extension of existing TRAU frames). The PCU frames have a uniform length of 320 Bit and are transferred every 20 ms via the Abis interface (16 kbit/s).

Thus, the PCU performs statistical multiplexing and routing.

The PCU load is automatically distributed between the available PPXX modules working as PPXU (extension shelf only). If a PPXU fails, the GPRS load is automatically distributed between the remaining PPXU modules.

History

In BSC "classic", 2 PPCU modules operating in cold standby make up one PCU. 2 PCU (4 modules in total) can be equipped in extension shelf. Distribution of packet traffic from GPRS cells between the PCU is statically configured (BR5.5).

SGSN

BSC

PCU

PCU tasks

• Management of GPRS radio resources

• Protocol conversion (packet data interworking)

• Tasks comparable to “classical” BSC

• Remote (until now BTS tasks): PC, TA,...

Gb:

standard interface

BTSE

Abis:

proprietary

i/fi/f

Fig. 22 PCU functions



31

BSC

PCU

PPCUPeripheral Packet

Control Unit

Providing

Service

PPCU

Cold

Standby

PCU

PPCU

Providing

Service

PPCU

Cold

Standby

max. 2 PCUs

cell 1

cell 2

cell 3

cell n· · ·

cell n+1

cell n+2

cell n+1

cell n+x· · ·

Fig. 23 PCU implementation with PPCU

Cell A

Cell B

Cell C

Cell D

Cell E

Cell F

PPXU-0 PPXU-1 PPXU-2

• GPRS traffic is automatically distributed among (working) PPXU

„well balanced“

• in case of failure, packet traffic is automatically redistributed

among the remaining PPXU (load sharing)

To SGSN

Fig. 24 Load sharing between PPXU


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2.10 Bus Systems

Three bus systems are implemented on the BSC backplane:

��Telephony System Bus:

Connects the peripheral processors PPXX (PPCC and PPLD, PPCU) with the TDPC.

��Administrative System Bus:

Connects the TDPC to the MPCC and the MPCC to the IXLT.

��Administrative Extended Bus:

Used as an O&M connection between MPCC (via UBEX) and PPXX (PPCC, PPLD and PPCU), SNXX, PLLH and XTLP.


Line Termination

Line Termination

Switching

Network

SNAP

Clock

PLLH

Line Termination

Line Termination

Line Termination

B

SS

GP

P

PX

X

B

SS

GP

P

PX

X

B

SS

GP

P

PX

X

L

AP

D

P

P

X

X

C

CS

7

P

P

X

X

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

UBEX

MPCC

to OMC

to LMT

. . .

Telephony

System Bus

Administrative

System Bus

Administrative

Extended Bus

Administrative

Extended Bus

QTLP

QTLP

QTLP

QTLP

QTLP

Fig. 25 Bus systems



33

3 Rack Configuration


MN1780EU09MN_0001

© 2001 Siemens AG

34

3.1 Hardware Compatibility

The following hardware configurations are supported:

BR5.5 BR6.0

DTLP QTLP QTLP QTLP

SN64 SN16 SN16 SNAP

PPLD PPLD PPLD PPXX ("PPXL")

PPCC PPCC PPCC PPXX ("PPXL")

PPCU PPCU PPCU PPXX ("PPXU")

PWRS PWRS PWRS PWRS and EPWR

Note

PPXX boards cannot be mixed with PPLD, PPCC and PPCU boards in the same BSC.

From BR6.0 onwards, the combination DTLP / SN64 is no longer supported.

Hardware Configuration Capacity (per BSC, fully equipped)

DTLP / SN64 / PPCU not supported with BR6.0 (512 kbit/s)

QTLP / SN16 / PPCU 2 Mbit/s

QTLP / SNAP / PPXX 24 Mbit/s

The combination SNAP/PPXX is known as BSC High Capacity 1st Step.



35

3.2 Rack Layout

The BSC consists of the Base and Expansion Subracks located in the same rack:

��The Base Subrack represents the minimum configuration.

��The Expansion Subrack provides additional link interface modules QTLP and the PCU for GPRS (modules PPXX in "PPXU" function).

Lamp Panel

Q

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7

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14

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0

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0

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40

0

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0

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1

6

0

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D

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6

1

U

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E

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1

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L

T

1

D

K

40

1

Expansion

Fuse and Alarm

Panel

Base

Fig. 26 BSC rack (BSC "classic", without PCU)


MN1780EU09MN_0001

© 2001 Siemens AG

36

Lamp Panel

Q

T

L

P

8

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7

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6

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P

C

U

0

P

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C

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1

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C

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3

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3

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2

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4

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3

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2

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1

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0

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1

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0

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1

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40

0

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6

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6

1

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1

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L

T

1

D

K

40

1

Expansion

Fuse and Alarm

Panel

Base

Fig. 27 BSC rack (BSC "classic", fully equipped with PPCU)

PCU0 (PCU1) is made up of modules PPCU0&1 (PPCU2&3).



37

Lamp Panel

Q

T

L

P

8

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7

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7

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6

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3

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2

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2

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0

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1

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0

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0

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0

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N

A

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0

T

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0

M

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C

C

1

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E

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T

1

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1

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1

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B

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1

I

X

L

T

1

Expansion

Fuse and Alarm

Panel

Base

Fig. 28 BSC rack (BSC High Capacity 1st Step)



39

3.3 Base Subrack

For reliability, certain modules are duplicated (1:1 redundancy), combined to a pool with one spare module (n:1 redundancy) or work in load sharing (1+1).

Module Redundancy Quantity Numbering

QTLP n:1 3 XTLP-0,-1; XTLP-S0

PPXX 1+1 2 PPXX-0, PPXX-1 ("PPXL")

(PPCC) 1+1 2 PPCC-0,-1

(PPLD) n:1 3 PPLD-0,-1,-2

PLLH 1:1 2 PLLH-0,-1

PWRS 1:1 2 PWRS-0,-1

(DK40) 1:1 2 DK40-0,-1

IXLT 1:1 2 IXLT-0,-1

SNAP 1:1 2 SNAP-0,-1

(SN16) 1:1 2 SN16-0,-1

Telephony Processor

1:1 2 TDPC-0,-1

MEMT-0,-1

Administrative Processor

1:1 2 MPCC-0,-1

UBEX-0,-1

Notes

In BSC High Capacity 1st Step, only the Alarm Circuit is used on DK40-0 (hard disk is now located on MPCC).

Modules in brackets are only used in BSC "classic" but not in BSC HC 1st Step.


MN1780EU09MN_0001

© 2001 Siemens AG

40

IXLT is the only module with cold standby protection (beside PPCU).

The base subrack accommodates two power supplies PWRS-0 and PWRS-1:

��input voltage: -48 V

��output voltage: +5.3 V and +12.3 V

The two power supplies PWRS-0/PWRS-1 provide power to the following modules:

��PWRS-0 is responsible for all of the modules on side 0 and all XTLP, PPCC, and PPLD.

��PWRS-1 is responsible for all of the modules on side 1 and all XTLP, PPCC, and PPLD.

P

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0

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0

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4

0

0

Fig. 29 DC power distribution in the base subrack



41

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4

0

0

Fig. 30 DC power distribution in the base subrack (BSC High-Capacity 1st Step)


MN1780EU09MN_0001

© 2001 Siemens AG

42

3.4 Expansion Subrack

The expansion subrack has additional space for link modules and peripheral processors:

��7 + 1 QTLP

��12 PPLD or 4 PPLD + 4 PPCU (BR6.0 early drop) or 6 PPXX ("PPXU", BR6.0 late drop)

��2 EPWR (new hardware with BR6.0 late drop).

Module Redundancy Quantity Numbering

QTLP n:1 7+1 QTLP-2...-8

QTLP-S1

PPXX 5+1 6 PPXX-2 ... 7

(PPLD) n:1 12 PPLD-3...-14

(PPCU) 1:1 2 x (1+1) PPCU-0...-3

EPWR 1:1 2 EPWR-0,-1

Each EPWR supplies all of the modules in the subrack.

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11

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10

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D

9

Fig. 31 DC power distribution in the expansion subrack (no PCU, BSC "classic")



43

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15

Fig. 32 DC power distribution in the expansion subrack (2 PCU, BSC "classic")

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13 12

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11 10

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915

Fig. 33 DC power distribution in the expansion subrack (fully equipped with PCU, BSC HC 1st Step)



45

4 Exercises



47

��Name the major functions of the BSC.

��List the processors used in the BSC.

��What is the function of the PCU?

��What is the function of the switching network?

��How are the LAPD signaling channels to BTSE called? How many time slots are required / possible?

��What is the name for the LAPD signaling to the TRAU? How many time slots are required?

��Where is software and the BSC database stored?

��In which directory is the running software stored?

��Which directory is used for the download of new software?

��What is the function of the IXLT?

��What is the function of the PLLH?

��What is the function of the QTLP?

��Does the same QTLP support PCMB, PCMS and PCMG (and if yes, how many)?

��Which different functions do PPXX modules handle?

��How is the number of PPXX modules required for LAPD/CCSS#7 signaling determined?

��Why does the bandwidth desired for GPRS determine the number of PPXX modules in expansion shelf?

��Which type of redundancy do PPXX modules support?

��Which type of redundancy applies to MPCC operation?

��If MPCC-1 becomes defective, will the entire BSC be out of service?

��If EPWR-1 becomes defective, which modules will not be powered?

��What happens if IXLT breaks down? Is there an interruption of service?

��What is the effect of the second IXLT also breaking down?

��Which modules in base and expansion subracks can be hot-plugged?

��How many QTLP, PPXX (PPCC and PPLD) are used in the base subrack?

��How many QTLP, PPXX (PPCC and PPLD) are used in the expansion subrack?

��What is the BSC capacity in terms of PCMx lines, LAPD channels?

��Which GPRS bandwidth does the BSC support?

02 mn1780eu09mn 0001 bsc architecture

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