CODE GENERATION

CODE GENERATION IN A NUTSHELL

This phase takes as input the intermediate representation (IR)produced by the frond end of the compiler, along with the relevantsymbol table information, and produces as output a semantically

equivalent target program

CODE GENERATION: IS IT THE END?

Compilers that need to produce efficient target programs, include anoptimization phase prior to code generation.

- In general, the IR passes through the back end of acompiler (code-optimization and code-generation phases) multipletimes before generating the target program

TASKS

1. Instruction selection

- involves choosing appropriate target-machine instructions toimplement the IR statements

2. Register allocation and assignment

- involves deciding what values to keep in which registers

3. Instruction ordering

- involves deciding in what order to schedule the execution ofinstructions

ISSUES IN THE DESIGN OF THE CODE GENERATOR

1. Input to the Code Generator

2. The Target Program

3. Instruction Selection

4. Register Allocation

5. Evaluation Order

1. INPUT TO THE CODE GENERATOR

PUT THE BLAME ON THE INPUT

oFirst, the IR of the source program is the input to the code generator.

oSecond, the many choices for the IR include three-addressrepresentations, virtual machine representations, linear representationsand graphical representations. Example of these representations, like

the three-address code, trees and DAGs are discussed in Chapter 6

PUT THE BLAME ON THE INPUT

Therefore, we assume that the front end has scanned, parsed andtranslated the source program into a relatively low-level IR. Also,we assume that all syntactic and static semantic errors have been

detected, necessary type checking has taken place, and type-conversion operators have been inserted when needed.

2. THE TARGET PROGRAM

GETS NA BANG YUNG TARGET [PROGRAM]?

o Most common target-machine architectures:

1. RISC (reduced instruction set computer)

2. CISC (complex instruction set computer)

3. Stack based

GETS NA BANG YUNG TARGET [PROGRAM]?

o If an absolute machine-language program is produced as theoutput, it will be advantageous as it can be placed in a fixedlocation in memory and immediately executed thus programs can

be compiled and executed quickly.

o If a relocatable machine-language program is produced as theoutput, it will allow subprograms to be compiled separately.

o If an assembly-language program is produced as output, theprocess of code generation will be easier.

3. INSTRUCTION SELECTION

ANG AKSYON SA MGA INSTRUCTION

o The code generator must map the IR program into a codesequence that can be executed by the target machine complexityof the said mapping is determined by:

The level of the IR

The nature of the instruction-set architecture

The desired quality of the generated code

ANG AKSYON SA MGA INSTRUCTION

-> redundant since it loads that has just been stored

For example:

ANG AKSYON SA MGA INSTRUCTION

o Rule of thumb (or not): quality of the generated code is usuallydetermined by its speed and size

For example, the three-address statement a = a + 1 may beimplemented more efficiently by INC a

INC a VS

ANG AKSYON SA MGA INSTRUCTION

o Instruction costs should also be studied to design good codesequences. However, cost information is difficult to obtain. Decidingwhich machine-code sequence is best for a given three-address

construct may also require knowledge about the context in whichthat construct appears.

4. REGISTER ALLOCATION

TER, KUMUSTA IMONG REGISTER?

o Use of registers is subdivided into two subproblems:

1. Register allocation we select the set of variables that will reside in registers at each point in the program

2. Register assignment we select the specific register that a variable will reside in

TER, KUMUSTA IMONG REGISTER?

Register-pairs (an even and next odd-numbered register)

Example:

M x, y - x is the even register, y is odd, product occupies the entire even/odd register pair

D x, y - x is the even register, y is odd, remainder occupies the even register, quotient occupies the odd one

TER, KUMUSTA IMONG REGISTER?

5. EVALUATION ORDER

WAITER, PACHECK NG ORDER

o Some computation orders require fewer registers to holdintermediate results than others this can affect the efficiency ofthe target code.