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VHDL

Simulation & Synthesis

FSM

• 状态机分类• Moore 型状态机设计• 状态机复位• Moore 型状态机信号输出方法• Mealy 型状态机• 状态机容错设计

FSM 应用• FSM 通过状态图描述状态转换过程• FSM ：数字系统控制单元的建模• 数字系统：

– 受控模块：功能模块，设计较易– 控制模块实现

• CPU• FSM

– 执行耗费时间，执行时间的确定性方面， FSM 优于 CPU

FSM 构成FSM 用来解决一般时序逻辑电路问题，包括

同步 / 异步时序逻辑• 状态寄存器

– 当前状态（现态）寄存器• 组合逻辑电路

– 下一状态（次态）组合逻辑– 输出组合逻辑

FSM 分类• Moore 型：输出信号仅与现态相关• Mealy 型：输出信号与现态和输入相关

DFFs

OutputComb. Logic

FeedbackComb. Logic DFFs

OutputComb. Logic

FeedbackComb. Logic

Moore Mealy

现态

次态 输入

输出

现态

次态

输出

输入

vhdl 语言描述 FSM 的建立过程跟据具体要求分析控制过程，建立状态转移图后：• 1 。定义枚举类型的信号描述状态• 2 。建立第 1 个进程，描述次态组合逻辑，现态

和输入信号作为敏感量，• 3 。在进程中定义状态转移

– CASE WHEN 语句的一条表示一个状态，状态转移通过 IF THEN ELSE 语句实现

• 4 。对于双进程 FSM ，建立第 2 个进程，现态寄存器描述进程， CLK ， RST 为敏感量；对于单进程 FSM ，则在一个进程中完成同步状态转移。

Stmch1.vhdlibrary ieee;

use ieee.std_logic_1164.all;

entity stmch1 is

port(clk, in1, rst: in std_logic; out1: out std_logic);

end stmch1;

architecture behave of stmch1 is

type state_values is (sx, s0, s1);

signal state, next_state: state_values;

begin

process (clk, rst)

begin

if rst = '1' then

state <= s0;

elsif rising_edge(clk) then

state <= next_state;

end if;

end process;

process (state, in1) begin -- set defaults for output and state out1 <= '0'; next_state <= sx; -- catch missing -- assignments to -- next_state case state is when s0 => if in1 = '0' then out1 <='1'; next_state <= s1; else out1 <= '0'; next_state <= s0; end if; when s1 => if in1 = '0' then out1 <='0'; next_state <= s0; else out1 <= '1'; next_state <= s1; end if; when sx => next_state <= sx; end case; end process;end behave;

Comb Logic

DFFs

in1

state clkrst

out1

next_state

s0/0

s1/1input=0

Reset=1 input=0

input=1

input=1

statmach.vhdLibrary IEEE ;

use IEEE.std_logic_1164.all ;

ENTITY statmach IS

PORT( clk : IN BIT;

input : IN BIT;

reset : IN BIT;

output : OUT BIT);

END statmach;

ARCHITECTURE a OF statmach IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE;BEGIN PROCESS (clk,reset) BEGIN IF reset = '1' THEN state <= s0; ELSIF (clk'EVENT AND clk = '1') THEN CASE state IS WHEN s0 => state <= s1;

WHEN s1=> IF input = '1' THEN state <= s0; ELSE state <= s1; END IF;

END CASE; END IF; END PROCESS; output <= '1' WHEN state = s1 ELSE '0';END a;

s0/0

s1/1input=1

input=0

Reset=1

Fsm2.vhdlibrary ieee;

use ieee.std_logic_1164.all;

ENTITY fsm2 IS

PORT(clock,x : IN BIT; z : OUT BIT);

END fsm2;

-------------------------------------------------

ARCHITECTURE using_wait OF fsm2 IS

TYPE state_type IS (s0,s1,s2,s3);

BEGIN

PROCESS

VARIABLE state : state_type := s0;

BEGIN

WAIT UNTIL (clock'EVENT AND clock = '1'); CASE state IS WHEN s0 => IF x = '0' THEN state := s0; z <= '0'; ELSE state := s2; z <= '1'; END IF; WHEN s2 => IF x = '0' THEN state := s2; z <= '1'; ELSE state := s3; z <= '0'; END IF; WHEN s3 => IF x = '0' THEN state := s3; z <= '0'; ELSE state := s1; z <= '1'; END IF; WHEN s1 => IF x = '0' THEN state := s0; z <= '0'; ELSE state := s2; z <= '0'; END IF; END CASE; END PROCESS;END using_wait;

s0s1

s2

s3

0/0

1/10/1

1/00/0

1/1

0/0

1/0

FSM 的复位• 同步复位

– 双进程状态机• 在第 1 个进程的开始处用 IF THEN 语句判断 RESET ，在其

后的 ELSE 语句里用 CASE 语句定义状态转换• 或者在第 2 个进程里定义同步复位

– 单进程状态机• 进程里定义同步复位

• 异步复位– 双进程状态机

• 在第 2 个进程里定义异步复位– 单进程状态机

• 进程里定义异步复位

CASE_WHEN IF …THEN ELSE

PROCESS 1

CLK’EVENTAND CLK=‘1’

PROCESS 2

次态

现态

输入 输出

Moore 型 FSM 信号输出方法• 由状态编码位经组合译码后输出• 并行输出寄存器的译码输出• 状态位里的编码输出• 一位有效编码方式

FSM 输出方法 1

• 由状态编码位经组合译码后输出 delay

FSM 输出方法 2

• 并行输出寄存器的译码输出

FSM 输出方法 3

• 状态位里的编码输出– 缩短输出延时– 要求状态位编码与输出信号要求的值相结合

Moore1.vhdlibrary ieee;use ieee.std_logic_1164.all;

entity moore1 is port( clk, rst: in std_logic; id: in std_logic_vector(3 downto 0); y: out std_logic_vector(1 downto 0));end moore1;

architecture archmoore1 of moore1 is type states is (state0, state1, state2, state3, state4); signal state: states;beginmoore: process (clk, rst)

… …End process--assign state outputs concurrently;y <= "00" when (state=state0) else "10" when (state=state1 or state=state3) else "11";end archmoore1;

moore: process (clk, rst) --this process defines the next state only begin if rst='1' then state <= state0; elsif (clk'event and clk='1') then case state is when state0 => if id = x"3" then state <= state1; else state <= state0; end if; when state1 => state <= state2; when state2 => if id = x"7" then state <= state3; else state <= state2; end if; when state3 => if id < x"7" then state <= state0; elsif id = x"9" then state <= state4; else state <= state3; end if; when state4 => if id = x"b" then state <= state0; else state <= state4; end if; end case; end if; end process;

DFFs

OutputComb. Logic

FeedbackComb. Logic

Moore2.vhdlibrary ieee;use ieee.std_logic_1164.all;

entity moore2 is port( clk, rst: in std_logic; id: in std_logic_vector(3 downto 0); y: out std_logic_vector(1 downto 0));end moore2;

architecture archmoore2 of moore2 is signal state: std_logic_vector(2 downto 0);-- State assignment is such that 2 LSBs are outputsconstant state0: std_logic_vector(2 downto 0) := "000";constant state1: std_logic_vector(2 downto 0) := "010";constant state2: std_logic_vector(2 downto 0) := "011";constant state3: std_logic_vector(2 downto 0) := "110";constant state4: std_logic_vector(2 downto 0) := "111";beginmoore: process (clk, rst) … end process;

--assign state outputs (equal to state std_logics)

y <= state(1 downto 0);end archmoore2;

moore: process (clk, rst) begin if rst='1' then state <= state0; elsif (clk'event and clk='1') then case state is when state0 => if id = x"3" then state <= state1; else state <= state0; end if; when state1 => state <= state2; when state2 => if id = x"7" then state <= state3; else state <= state2; end if; when state3 => if id < x"7" then state <= state0; elsif id = x"9" then state <= state4; else state <= state3; end if; when state4 => if id = x"b" then state <= state0; else state <= state4; end if; when others => state <= state0; end case; end if; end process;

DFFsFeedback

Comb. Logic

No output comb. Logic, no race or

hazard

FSM 输出方法 4

• ONE HOT 编码• 使用 N 位状态寄存器表达具有 Ng 状态的 FSM ，

每个状态具有独立的寄存器位。任意时刻只有 1位寄存器为 1 ，即 hot point 。此为 one hot 。

• One hot 编码方程用简单的次态方程驱动，减少了状态寄存器之间的组合逻辑级数，因此提高了运行速度。同时是以牺牲寄存器逻辑资源和提高成本为代价的。

• 目标器件具有较多寄存器资源，寄存器之间组合逻辑较少时比较适用。

FSM 的容错设计• 枚举型数据状态编码在综合时转换为矢量信号，状态位数

目 =log2N ， N ：状态数• 若 log2N 不为整数，存在未定义状态，非法状态。• 不考虑非法状态则可减少设计的逻辑数目，考虑非法状态

则可降低系统容错性• 原因：干扰，噪声，电源变化等引起触发器翻转误入非法

状态，造成死锁。• 处理：转入空闲态；转入指定态；转入预定义的错误处理

告警状态– When others => State<= idle; --- 转入空闲态；– When others => State <=“XXXXX”; --- 忽略；

• 对 one hot 型 FSM ，可编写检错程序，判断是否同时又多个状态寄存器为 1 ，，若有做相应出错处理。

Mealy 型 FSM

DFFs

OutputComb. Logic

FeedbackComb. Logic

Mealy

现态

次态

输出

输入

Mealy1.vhdlibrary ieee;

use ieee.std_logic_1164.all;

entity mealy1 is port(

clk, rst: in std_logic;

id: in std_logic_vector(3 downto 0);

y: out std_logic_vector(1 downto 0));

end mealy1;

architecture archmealy of mealy1 is

type states is (state0, state1, state2, state3, state4);

signal state: states;

begin

Mealy_proc: process (clk, rst)

…

…

end process;

end archmealy;

Mealy_proc: process (clk, rst) begin if rst='1' then state <= state0; y <= "00"; elsif (clk'event and clk='1') then case state is when state0 => if id = x"3" then state <= state1; y <= "10"; else state <= state0; y <= "00"; end if; when state1 => state <= state2; y <= "11"; when state2 => if id = x"7" then state <= state3; y <= "10"; else state <= state2; y <= "11"; end if; when state3 => if id < x"7" then state <= state0; y <= "00"; elsif id = x"9" then state <= state4; y <= "11"; else state <= state3; y <= "10"; end if; when state4 => if id = x"b" then state <= state0; y <= "00"; else state <= state4; y <= "11"; end if; end case; end if; end process;

DFFs

OutputComb. Logic

FeedbackComb. Logic