seattle pacific university ee 1210 - logic system designmux-decoder-1 multiplexers two alternative...

Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-1

Multiplexers

Two alternative formsfor a 2:1 Mux Truth Table

Functional form

Logical form

I 1 0 0 0 0 1 1 1 1

I 0 0 0 1 1 0 0 1 1

S 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

S 0 1

Z I 0 I 1

A digital n-to-1 switch is called a multiplexer (or a selector)

Z = S' I0 + S I1

I 0

I 1 Z

S

S=0

S=1

2:1Multiplexor


Multiplexers

Z SI SI 0 1

Z S S I S S I S S I S S I 1 0 0 1 0 1 1 0 2 1 0 3

Z S S S I S S S I S S S I S S S IS S S I S S S I S S S I S S S I

2 1 0 0 2 1 0 1 2 1 0 2 2 1 0 3

2 1 0 4 2 1 0 5 2 1 0 6 2 1 0 7

I 0

S2

I 1 I 2 I 3

S1

Z 8:1 mux

S0

I 4 I 5 I 6 I 7

I 0

S1

I 1 I 2 I 3

S0

Z 4:1 mux

2:1 mux

I 0

I 1

S

Z


VHDL MuxesLIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY mux4to1 ISPORT( data: IN STD_LOGIC_VECTOR(3 downto 0);

sel : IN STD_LOGIC_VECTOR(1 downto 0); z : OUT STD_LOGIC);

END mux4to1;

Remember the IEEE library!

ARCHITECTURE behavior OF mux4to1 ISBEGINPROCESS(data,sel)BEGIN

CASE sel ISWHEN "00" => z <= data(0);WHEN "01" => z <= data(1);WHEN "10" => z <= data(2);WHEN "11" => z <= data(3);WHEN others => z <= 0;

END CASE;END PROCESS;END behavior;

Inputs: data[3..0],sel[1..0]Output: Z

Set up as a CASE statement

WHEN OTHERS – Use this even if there aren’t any others

If Data or Sel change, output (Z) can change


Cascading MuxesLarge multiplexers can be implemented by cascaded smaller muxes

Control signals S1 and S0 simultaneouslychoose one of I0-I3 and I4-I7

Control signal S2 chooses which of theupper or lower MUX's output to gate to Z

Alternative 8:1 Mux Implementation

0

1 S

0

1 S

0

1 S

0

1 S

0

1

S0

2

3 S1

S2 S1

S0

Z

I0 I1

I2 I3

I4

I5

I6

I7

S0

S0

S0

4:1 mux

4:1 mux

8:1 mux

2:1 mux

0 1 2 3

0 1 2 3

S

S 1 S 0

S 1 S 0

S2S0S1

I0

0

1

I1 I2 I3

I4 I5 I6 I7

Z


Using Muxes as logic blocks

2n-1:1 multiplexer can implement any function of n variablesn-1 control variables; remaining variable is a data input to the mux

F(C,B,A) = m0 + m2 + m6 + m7

Lookup Table

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

8:1 MUX

1 0 1 0 0 0 1 1

0 1 2 3 4 5 6 7 S2 S1 S0

C B A

F

0 1 0

1


Optimized LUTs

F(C,B,A) = m3 + m4+ m6 + m7

C B

S1 S0

4:1 MUX

0 1 2 3

A0

1A

F

We can fit a function of n variables into a 2n-1:1 mux by using this trick (note: may require one inverter)

C0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

F 0 0 0 1 1 0 1 1

A

0

1

A

CB=00; F=0

CB=01; F=A

CB=10; F=A’

CB=11; F=1


Using a multiplexor as a switchConsider a computer system with CPU, memory, I/O devices, etc.

Each one needs to be able to communicate with the others…

Memory

CPU

Disk

Keyboard

4:1 x 32bit Mux

32

32

32

32

32

Control

Pros:• Conceptually simple

Cons:• Lots of wires…• Each device needs separate output and input ports• 32-bit mux is a large device

Example: Read a value from memory into CPU

00


Using a BusBus – Bidirectional, Driven by one device at a time

Memory

CPU

Disk

Keyboard

32

Control

32

32

32

32

Critical issue: We’re connecting multiple outputs together. Bad Idea!

A few (2-3) control lines to each device Pros:

• Much fewer wires• Simpler wiring• Expandable• One data port per device

Cons:• More complex electrically• Must manage bus

Example: Read a value from memory into CPU


Smoke Happens…

OK to connect one output to multiple inputs

Not OK to connect outputs together!

+5V

0

+5V

1

Direct connection from power to ground – smoke!


Tri-State Inverter

In Out

En=1

In Out

En=0

In Out

En

High-Impedance(Hi-Z) state

Modify an inverter…

Tri-state Inverter

Out

5V

0V

In

Enable

En Out0 Z1 In’


Using tri-state gatesGoal: Connect three selectable inputs to a common output

Whenever a select signal is asserted,that input is connected to the output

Must make sure that there is always exactly one driver turned on!

in0

sel0

in1

sel1

in2

sel2 out


Demultiplexers

Demultiplexer: One data input, n control inputs, 2n outputs

1:2 Demultiplexer:

O0 = G • S; O1 = G • SGS

O0

O1G

S

O0

O1

Control inputs (called selects) - Binary index of output to which the input is connected

Data input usually called “enable” (‘G’ or ‘E’)


Larger Demultiplexers/Decoders

1:4 Demultiplexer

1:8 Demultiplexer

O0 = G • S1 • S0

O1 = G • S1 • S0

O2 = G • S1 • S0

O3 = G • S1 • S0

O0 = G • S2 • S1 • S0

O1 = G • S2 • S1 • S0

O2 = G • S2 • S1 • S0

O3 = G • S2 • S1 • S0

O4 = G • S2 • S1 • S0

O5 = G • S2 • S1 • S0

O6 = G • S2 • S1 • S0

O7 = G • S2 • S1 • S0

GS1 S0

O0

O1

O2

O3 G

S2 S1 S0

O0

O1

O2

O3

O4

O5

O6

O7

2:4 Decoder

3:8 Decoder

If we view the ‘G’ signal as an enable, then a demultiplexer simply decodes the binary select signal into a unary output signal Decoder

Decoder: • Enable=0 all outputs are 0• Enable=1 output is unary representation of binary select input


Decoders In VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY Decoder2to4 IS

PORT( s : IN STD_LOGIC_VECTOR(1 downto 0); en : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR(3 downto 0));

END Decoder2to4;ARCHITECTURE logicfunc OF Decoder2to4 ISBEGIN

PROCESS(s,en)BEGIN

IF (en=‘1’) THENCASE (s) IS WHEN “00” => y <= “0001”; WHEN “01” => y <= “0010”; WHEN “10” => y <= “0100”; WHEN “11” => y <= “1000”; WHEN OTHERS => y <= “0000”;END CASE;

ELSE y <= “0000”;END IF;

END PROCESS;END logicfunc;

Sensitive to changes in s or en

Only consider when en = ‘1’

If en = ‘0’, then output “0000”

Go through cases for all possible inputs


EncodersEncoders are the opposite of decoders

Unary input w[7..0] – exactly one of the eight inputs is ‘1’

Binary output y[2..0] – Corresponds to the index of the input that is ‘1’

For an 8-3 encoder, there should be 256 rows in the truth table

Only rows with exactly one ‘1’ are valid Eight valid rows

w0

w1

w2

w3

w4

w5

w6

w7

y0

y1

y2

8-3Encoder


Priority EncodersWhat if more than one input to and encoder is ‘1’?

Invalid input Output is undefined

Priority Encoder:If more than one input is ‘1’, more significant bit has priorityAdd a ‘z’ output true when no inputs are ‘1’

w0

w1

w2

w3

w4

w5

w6

w7

y0

y1

y2

8-3Priority

Encoder

z

01001010

110

0

Hig

her P

riorit

y

6

w7 w6 w5 w4 w3 w2 w1 w0 y2 y1 y0 z0 0 0 0 0 0 0 0 x x x 10 0 0 0 0 0 0 1 0 0 0 00 0 0 0 0 0 1 x 0 0 1 00 0 0 0 0 1 x x 0 1 0 00 0 0 0 1 x x x 0 1 1 00 0 0 1 x x x x 1 0 0 00 0 1 x x x x x 1 0 1 00 1 x x x x x x 1 1 0 01 x x x x x x x 1 1 1 0


VHDL Priority EncoderLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY Priority8 IS

PORT( w : IN STD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(2 downto 0); z : OUT STD_LOGIC);

END Priority8;

Remember the IEEE library!

ARCHITECTURE behavior OF Priority8 ISBEGINPROCESS(w)BEGIN

IF (w(7)=‘1’) THEN y <= “111”; z <= ‘0’;ELSIF (w(6)=‘1’) THEN y <= “110”; z <= ‘0’;ELSIF (w(5)=‘1’) THEN y <= “101”; z <= ‘0’;ELSIF (w(4)=‘1’) THEN y <= “100”; z <= ‘0’;ELSIF (w(3)=‘1’) THEN y <= “011”; z <= ‘0’;ELSIF (w(2)=‘1’) THEN y <= “010”; z <= ‘0’;ELSIF (w(1)=‘1’) THEN y <= “001”; z <= ‘0’;ELSIF (w(0)=‘1’) THEN y <= “000”; z <= ‘0’;ELSE y <= “000”; z <= ‘1’;END IF;

END PROCESS;END behavior;

Input: w[7..0]Outputs: y[2..0], Z

Case statement would require 256 rows…

Use cascaded IFs

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