© prepared by: razif razali 1 chapter four central processing unit

© Prepared By:Razif Razali 1

CHAPTER FOURCHAPTER FOUR

CENTRAL PROCESSING UNITCENTRAL PROCESSING UNIT

© Prepared By:Razif Razali

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ContentsContents

• CPU Organization.CPU Organization.

• Register organisationRegister organisation

• Instruction cycleInstruction cycle

• Addressing Modes Addressing Modes

• StackStack

INTRODUCTIONINTRODUCTION

• Computer architecture means CPU components which are visible to machine programming language, including register, instruction format, addressing trend and memory organization.

• A computer’s micro architecture means, internal instruction of CPU, including visible components to programmer ( architecture ) and those which are invisible to programmer ( others CPU internal components ).

• CPU is generally a single microprocessor made from a wafer of semi-conducting material, usually silicon, with millions of electrical components on its surface.

• The main function of the CPU is to perform arithmetic and logical operations on data taken from memory or on information entered through some device, such as a keyboard, scanner, or joystick.


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CPU ORGANIZATIONCPU ORGANIZATION

To understand the organization of the processor, let us consider the requirements placed on the processor, the thing it must do:•Fetch instructions

– The CPU reads an instruction from memory (register, cache, main memory)•Interpret instructions

– The instruction is decoded to determine what action is required•Fetch data

– The execution of an instruction may require reading data from memory or an I/O Module.

•Process data– The execution of an instruction may require performing some arithmetic or logical

operation on data.•Write data

– The results of an execution may require writing data to memory or an I/O Module


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CPU WITH SYSTEM BUSCPU WITH SYSTEM BUS

• The major components of the processor are arithmetic and logic unit (ALU) and control unit (CU).

• The ALU does the actual computation or processing of data.

• The control unit controls the movement of data and instruction into and out of the processor and controls the operation of the ALU.

• In addition, the figure shows a minimal internal memory, consisting of a set of storage location called registers.


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CPU WITH SYSTEM BUSCPU WITH SYSTEM BUS• Figure shows a slightly more detailed

view of processor.

• The data transfer and logic control paths are indicated, including an element labeled internal processor bus.

• This element is needed to transfer data between the various registers and the ALU because the ALU operates only on data in the internal processor memory.

• It also shows typical basic elements of the ALU.

• Component of CPU:– ALU– CU– Registers


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Arithmetic & Logic Unit (ALU)

• Performs arithmetic and logical operations on data• Does the calculations• Everything else in the computer is there to service this unit• Handles integers• May handle floating point (real) numbers


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Control Unit (CU)

• The control unit of a processor performs two task:• It cause the processor to execute micro-operations in the proper

sequence, determined by the program being executed• It generates the control signals that cause each micro-operation to

be executed.• The control signals generated by the control unit cause the

opening and closing of logic gates, resulting in the transfer of data to and from register and the operation of the ALU.


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Registers

• CPU must have some working space (temporary storage) called registers.

• Number and function vary between processor designs.• One of the major design decisions.• Top level of memory hierarchy.• Register in the CPU perform 2 (TWO) roles:

– User-Visible Register• Enable the machine or assembly language programmer to minimize

main memory references by optimizing use of registers.• Control And Status Register

• Used by the control unit to control the operation of the processor and by privileged, operating system programs to control the execution of programs


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USER VISIBLE REGISTERUSER VISIBLE REGISTER

• Refer to as a mean of the machine language that the processor executes.

• Can be categorized as:


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General Purpose Register

• Can be assigned to a variety functions by the programmer• It can contain the operand for any op-code• Often, however, there are restrictions. • For example, there may be dedicated registers for floating-point

and stack operation• May be used for addressing function.


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Data Register & Address Register

• Data registerData register– May be used only to hold data and cannot be employed in

the calculation of an operand address.

• Address registerAddress register– May themselves be somewhat general purpose, or they may

be devoted to a particular addressing mode– Example include : segment pointers, index registers, stack

pointer


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Condition codes register (or Condition codes register (or flagsflags) )

• Condition codes are bits set by the processor hardware as the Condition codes are bits set by the processor hardware as the result of the operations.result of the operations.

• For example: For example: – an arithmetic operation may produce a positive, negative, zero or

overflow result. • In addition to the result itself being stored in a register or In addition to the result itself being stored in a register or

memory, a condition code is also set. memory, a condition code is also set. • The code may subsequently be tested as part of a conditional The code may subsequently be tested as part of a conditional

branch operation.branch operation.


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Control and status register

• They are variety of processor registers that are employed to control the operation of the processor.

• Most of these on most machine, are not visible to the user.• Some of them may be visible to machine instruction executed in a control or

operating system mode.• Four (4) registers are essential to instruction to be fetched:

– Program Counter (PC)• Contains the address of an instruction to be fetched.

– Instruction Decoding Register (IR)• Contains the instruction most recently fetched.

– Memory Address Register (MAR)• Contains the address of a location in memory.

– Memory Buffer Register (MBR/MDR)• Contains a word of data to be written to memory or the word most recently read.


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Register Organization


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INSTRUCTION CYCLE

• The function of a computer is to execute programs. • The operation of a computer, in executing a program, consists of a sequence of

instruction cycle, with one machine instruction per cycle. • Each instruction cycle can be considered to be made up of a number of smaller

units. • One subdivision that found convenient :

– Fetch– Indirect– Execute – Interrupt, with only the fetch and execute cycles always occurring.

• In fact, we will see that each of the cycles involves a series of steps, each of which involves the CPU registers.

• We will refer to these steps as micro-operations. • The prefix micro refers to the fact that each step is very simple and accomplishes

very little.


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INSTRUCTION CYCLE

• To summarize, the execution of a program consists of the sequential To summarize, the execution of a program consists of the sequential execution of instructions. execution of instructions.

• Each instruction is executed during an instruction cycle made up of Each instruction is executed during an instruction cycle made up of shorter subcycles (e.g., fetch, indirect, execute, interrupt). shorter subcycles (e.g., fetch, indirect, execute, interrupt).

• The performance of each subcycle involves one or more shorter The performance of each subcycle involves one or more shorter operations, that are micro-operations. operations, that are micro-operations.


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The Fetch Cycle

• Fetch cycle occurs at the beginning of each instruction cycle and causes Fetch cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory. an instruction to be fetched from memory.

• Four registers are involved :Four registers are involved :

– Memory Address Register (MAR) :

• Is connected to the address line of the system bus. It specifies the address in memory for a read or write operation.

– Memory Buffer Register (MBR) :

• Is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from memory.

– Program Counter (PC) :

• Holds the address of the next instruction to be fetched.

– Instruction Register (IR) :

• Holds the last instruction fetched.


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Sequence of events (Fetch)Sequence of events (Fetch)• At the beginning of the fetch cycle,

the address of the next instruction to be executed is in the program counter (PC); in this case the address is 1100100.

• The first step is to move that address to the memory address register (MAR), since this is the only register connected to the address lines of the system bus.

• The second step is to bring in the instruction. The desired address (in the MAR) is placed on the address bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the memory buffer register (MBR).


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Sequence of events (Fetch - Cont…)• We also need to increment the PC by

1 to get ready for the next instruction. Since these two actions (read word from memory, add 1 to PC) do not interfere with each other, we can do them simultaneously to save time.

• The third step is to move the contents of the MBR to the instruction register (IR). This frees up the MBR for use during a possible indirect cycle.


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Sequence of events (Fetch - Cont…)• The simple fetch cycle actually consists of three steps and four micro-operations. The simple fetch cycle actually consists of three steps and four micro-operations. • Each micro-operation involves the movement of data into or out of a register. Each micro-operation involves the movement of data into or out of a register. • So long as these movements do not interfere with one another, several of them So long as these movements do not interfere with one another, several of them

can take place during one step, saving time. can take place during one step, saving time. • Symbolically =, we can write this sequence of events as follows :Symbolically =, we can write this sequence of events as follows :

tt1 1 : MAR : MAR (PC) (PC)

tt2 2 : MBR : MBR Memory Memory

tt3 3 : PC : PC (PC) + 1 (PC) + 1

IR IR (MBR) (MBR)• First time unitFirst time unit : Move contents of PC to MAR: Move contents of PC to MAR• Second time unitSecond time unit : Move contents of memory location specified by MAR to MBR. : Move contents of memory location specified by MAR to MBR.

Increment by 1 the contents of the PC.Increment by 1 the contents of the PC.• Third time unitThird time unit : Move contents of MBR to IR: Move contents of MBR to IR


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Indirect Cycle

• Once an instruction is fetched, the next step is to fetch source operands.

• Continuing our simple example, let us assume a one-address instruction format, with direct and indirect addressing allowed.

• If the instruction specifies an indirect, then an indirect cycle must precede the execute cycle. The data flow are follows:

t1 : MAR (IR (Address))

t2 : MBR Memory

t3 : IR (Address) (MBR (Address))


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Sequence of event (Indirect)

• The address field of the instruction is transferred to the MAR. This is then used to fetch the address of the operand. Finally, the address field of the IR is updated from the MBR, so that it now contains a direct rather than an indirect address.

• The IR is now in the same state as if indirect addressing had not been used, and it is ready for the execute cycle. We skip that cycle for the moment, to consider the interrupt cycle.


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The Interrupt Cycle

• At the completion of the execute cycle, a test is made to determine whether any enabled interrupt have occurred.

• If so, the interrupt cycle occurs. • The nature of this cycle varies greatly from one machine to

another. • Sequence of events are as follows:

t1 : MBR (PC)

t2: MAR Save-address

PC Routine-address

t3 : Memory (MBR)


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Sequence of event (Interrupt)• In the first step, the contents of the PC are In the first step, the contents of the PC are

transferred to the MBR, so that they can be transferred to the MBR, so that they can be saved for return from the interrupt. saved for return from the interrupt.

• Then the MAR is loaded with the address at Then the MAR is loaded with the address at which the contents of the PC are to be saved, which the contents of the PC are to be saved, and the PC is loaded with the address of the and the PC is loaded with the address of the start of the interrupt-processing routine. start of the interrupt-processing routine.

• These two actions may each be a single These two actions may each be a single micro-operation. However, since most CPUs micro-operation. However, since most CPUs provide multiple types and/or levels of provide multiple types and/or levels of interrupts, it may take one or additional micro-interrupts, it may take one or additional micro-operations to obtain the save-address and the operations to obtain the save-address and the routine-address before they can be transferred routine-address before they can be transferred to the MAR and PC, respectively. to the MAR and PC, respectively.

• In any case, once this is done, the final step is In any case, once this is done, the final step is to store the MBR, which contains the old value to store the MBR, which contains the old value of the PC, into memory. The CPU is now ready of the PC, into memory. The CPU is now ready to begin the next instruction cycle.to begin the next instruction cycle.


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Sequence of event (Execute)

• The fetch, indirect and interrupt cycle are simple and predictable.

• Each involves a small, fixed sequence of micro-operations and, in each case, the same micro-operations are repeated each time around.

• This is not true of the execute cycle.

• For a machine with N different op codes, there are N different sequences of micro-operations that can occur.

• Let us consider several hypothetical examples.

• First consider an add instruction :

ADD R1, X

• which adds the contents of the location X to register R1. which adds the contents of the location X to register R1.

• The following sequence of micro-operations might occur :The following sequence of micro-operations might occur :

t1 : MAR (IR (Address))

t2 : MBR Memory

t3 : R1 (R1) + (MBR)


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Sequence of event (Execute)

• We begin with the IR We begin with the IR containing the ADD containing the ADD instruction. instruction.

• In the first step, the In the first step, the address portion of the address portion of the MBR is loaded into the MBR is loaded into the MAR. MAR.

• Then, the referenced Then, the referenced memory location is read. memory location is read. Finally, the contents of R1 Finally, the contents of R1 and MBR are added by the and MBR are added by the ALU. ALU.


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Addressing Modes• The address field or fields in a typical instruction format are quite limited. We would like to be The address field or fields in a typical instruction format are quite limited. We would like to be

able to reference a large range of locations in main memory or for some system, virtual able to reference a large range of locations in main memory or for some system, virtual memory. memory.

• To achieve this objective, a variety of addressing techniques have been employed. To achieve this objective, a variety of addressing techniques have been employed. • In this section, we examine the most common addressing techniques :In this section, we examine the most common addressing techniques :

– Immediate– Direct– Indirect– Register– Register Indirect– Displacement– Stack

• We use the following notation :We use the following notation :

A A = contents of the (an) address field in the instruction. = contents of the (an) address field in the instruction.

EAEA = actual (effective) address of the location containing the referenced operand. = actual (effective) address of the location containing the referenced operand.

(X) = contents of location X.(X) = contents of location X.


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Immediate Addressing

• The simplest form of addressing is immediate addressing, in which the The simplest form of addressing is immediate addressing, in which the operand is actually present in the instruction.operand is actually present in the instruction.

• e.g. ADD 5e.g. ADD 5

– Add 5 to contents of accumulator

– 5 is operand

• Advantage : No memory reference to fetch dataAdvantage : No memory reference to fetch data

• FastFast

• Disadvantage : Limited rangeDisadvantage : Limited range


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Direct Addressing

• A very simple form of addressing is direct addressing, in which the A very simple form of addressing is direct addressing, in which the address field contains the effective address of the operand.address field contains the effective address of the operand.

• e.g. ADD Ae.g. ADD A

– Add contents of cell A to accumulator

– Look in memory at address A for operand

• Single memory reference to access dataSingle memory reference to access data

• No additional calculations to work out effective addressNo additional calculations to work out effective address

• Disadvantage : Limited address spaceDisadvantage : Limited address space


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Indirect Addressing• The problem with direct addressing is that the length of the address field is The problem with direct addressing is that the length of the address field is

usually less than the word length, thus limiting the address range. usually less than the word length, thus limiting the address range.

• One solution is to have the address field refer to the address of a word in One solution is to have the address field refer to the address of a word in memory, which in turn contains a full-length address of the operand. memory, which in turn contains a full-length address of the operand.

• Memory cell pointed to by address field contains the address of (pointer to) Memory cell pointed to by address field contains the address of (pointer to) the operandthe operand

• e.g. ADD (A)e.g. ADD (A)

– Add contents of cell pointed to by contents of A to accumulator

• Advantage: Large address space Advantage: Large address space

• 22nn where n = word length where n = word length

• Disadvantage : Multiple memory accesses to find operandDisadvantage : Multiple memory accesses to find operand

• Hence slowerHence slower


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Register Addressing

• Operand is in register, which resides within the CPU. Instruction can be Operand is in register, which resides within the CPU. Instruction can be executed within the CPU without the need to refer to memory for executed within the CPU without the need to refer to memory for operand.operand.

• Similar to direct addressingSimilar to direct addressing

• The only difference is that the address field refers to a register rather The only difference is that the address field refers to a register rather than a main memory address EA = Rthan a main memory address EA = R

• Operand is held in register named in address filedOperand is held in register named in address filed

• Limited number of registersLimited number of registers

• Very small address field needed Very small address field needed

– Shorter instructions

– Faster instruction fetch

• No memory accessNo memory access

• Very fast executionVery fast execution

• Very limited address spaceVery limited address space


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Register Indirect Addressing

• Instruction specifies a register in the CPU whose contains give the Instruction specifies a register in the CPU whose contains give the address of the operand in memory. address of the operand in memory.

• A reference to the register is then equivalent to specifying a A reference to the register is then equivalent to specifying a memory address.memory address.

• Is analogous to indirect addressingIs analogous to indirect addressing

• Operand is in memory cell pointed to by contents of register ROperand is in memory cell pointed to by contents of register R

• Large address space (2n)Large address space (2n)

• One fewer memory access than indirect addressingOne fewer memory access than indirect addressing


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Displacement addressing• Combination of direct and indirect addressing.• To execute the instruction two ways are used to refer to register and directly refer

to memory.• Later pointer will combine the instruction from both ways and finally operand in

memory will be accessed. • A very powerful mode of addressing combines the capabilities of direct addressing

and register indirect addressing• Address field hold two values

– A = base value– R = register that holds displacement– or vice versa


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Stack• A stack is an ordered set of elements, only one of which can be accessed A stack is an ordered set of elements, only one of which can be accessed

at a time.at a time.

• The point of access is called the top of the stack.The point of access is called the top of the stack.

• The number of elements in the stack, or length of stack, is The number of elements in the stack, or length of stack, is variablevariable..

• The last element in the stack is the The last element in the stack is the basebase of the stack. of the stack.

• Items may only be added to or deleted from the top of the stack.Items may only be added to or deleted from the top of the stack.

• A PUSH operation appends one new item to the top of the stack. A POP A PUSH operation appends one new item to the top of the stack. A POP operation removes the top item from the stack.operation removes the top item from the stack.

• In both cases, the top of the stack moves accordingly.In both cases, the top of the stack moves accordingly.

• Stack Basic Operation;Stack Basic Operation;


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Expression evaluation

• Mathematical formulas are usually expressed in what is known as Mathematical formulas are usually expressed in what is known as infixinfix notation. notation. • In this form, a binary operation appears between the operand (e.g. a + b). In this form, a binary operation appears between the operand (e.g. a + b). • For complex expressions, parentheses are used to determine the order of evaluation For complex expressions, parentheses are used to determine the order of evaluation

of expression. of expression. • For example, a + (b x c) will yield a different result than (a + b) x c.For example, a + (b x c) will yield a different result than (a + b) x c.• To minimize the use of parentheses, operations have an implied precedence. To minimize the use of parentheses, operations have an implied precedence. • Generally, multiplication takes precedence over addition. So that a + b x c is Generally, multiplication takes precedence over addition. So that a + b x c is

equivalent to a + (b x c).equivalent to a + (b x c).• An alternative technique is known as reverse Polish or An alternative technique is known as reverse Polish or postfixpostfix, notation., notation.• In this notation, the operator follows its two operands. For example:In this notation, the operator follows its two operands. For example:

a + b becomes a b +

a + (b x c) becomes a b c x +

(a + b) x c becomes a b + c x


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Expression evaluation (Cont…)• Note that, regardless of the complexity of an expression, no parentheses Note that, regardless of the complexity of an expression, no parentheses

are required when using reverse Polish.are required when using reverse Polish.

• The advantage of postfix notation is that an expression in this form is The advantage of postfix notation is that an expression in this form is easily evaluated using a stack.easily evaluated using a stack.

• For each element of the expression, the following rules are applied:For each element of the expression, the following rules are applied:

– If the element is a variable or constant, push it onto the stack.

– If the element is an operator, pop the top two items of the stack, perform the operation and push the result.

• After the entire expression has been scanned, the result is on top of the After the entire expression has been scanned, the result is on top of the stack.stack.

• Use of Stock to compute f = (a – b) / (d x e + cUse of Stock to compute f = (a – b) / (d x e + c


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© prepared by: razif razali 1 chapter four central processing unit

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