© H. Heck 2008 Section 2.5 1

Module 2: Transmission Line BasicsTopic 5: Modeling & Simulation

OGI ECE564

Howard Heck

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Where Are We?

1. Introduction

2. Transmission Line Basics1. Transmission Line Theory

2. Basic I/O Circuits

3. Reflections

4. Parasitic Discontinuities

5. Modeling, Simulation, & Spice

6. Measurement: Basic Equipment

7. Measurement: Time Domain Reflectometry

3. Analysis Tools

4. Metrics & Methodology

5. Advanced Transmission Lines

6. Multi-Gb/s Signaling

7. Special Topics

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Contents

Overview Transistor Level Models Non-linear Models Linear Models Simulation Tools Summary

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Overview

Accuracy Device Interconnect Speed

Highest TransistorsFrequency Dependent

Slowest

Non-linear Behavioral

Lossy

Lowest Linear Lossless Fastest

Which should we choose to use? Depends on our needs… If we need to simulate large numbers of nets (can be 1000’s),

speed is critical. If we are trying to design a new feature into a buffer, such as

automatic impedance control, we may wish to sacrifice speed for accuracy.

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Transistor Level I/O Models

Example: GTL Driver

V

Vin

Vout

VTT

RTT

CC

P1

N1

N2

N4

N3 Model Requirements: I/O circuit schematic Silicon process files Device dimensions

Sources: Silicon suppliers (databooks, Spice models) Simulation tool suppliers also supply some libraries.

Drawbacks: Many silicon suppliers are unwilling to divulge process model

data. Some use internal Spice variants with proprietary model types.

Conversion to standard Spice formats, they sacrifices accuracy. If the vendor improves the process or design, the model must be

updated. Simulations can take a lot of time to prepare and run.

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Model Requirements:

Iout vs. Vout curves for high

and low states

Vout vs. time curves for

rising & falling transitions Test load used for I-V & V-t curve generation

Sources: Silicon suppliers (databooks, IBIS models) Simulation and/or experimental measurements.

Many tools now have the capability to simulate the behavior of buffers using non-linear models. HSPICE accepts IBIS (I/O Buffer Information Specification) models. PSPICE has an analog behavioral modeling feature. Board simulators, such as XTK by Quad Design, use non-linear

models.

Example: I-V curves

Non-Linear I/O Models

0.0 0.5 1.0 1.5 2.0 2.5

Vout [V]

-100

-80

-60

-40

-20

0

20

40

60

80

100

I out

[m

A]

nMOSpMOS

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Non-Linear I/O Models #2 Models can be quite complex, including many features, such as:

Multi-stage output drivers Receiver “clamping” Simultaneous switching effects

Advantages: Can be nearly as accurate as transistor models, but run faster. Suitable for worst case analysis & “sensitivity” analysis. They provide a way to develop buffer requirements by exploring the

effects of changing the behavioral characteristics.

Drawbacks: Datasheets may not contain all desired information. Some tools may not support all available features.

When to use: They can be used at any time during the design cycle, but may not be

worth the effort in the early stages of the design, when several design variables are being explored & defined.

Non-linear behavioral models are the most widely used model type for designing boards.

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Linear I/O Models

Example: our Thévenin equivalent circuit with a linear rise/fall time.

Requirements: Supply voltage(s) and effective output resistance. Note that

the high and low resistances can be different. Rise and fall times

Advantages: fast Disadvantages: limited accuracy When to use:

Early in the design cycle when you are trying to bound your buffer and interconnect requirements.

For learning the basics of interconnect & transmission lines.

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Transmission Lines There are different approaches and different algorithms. PSpice uses discrete circuit elements (as near as I can tell).

Not very effective for high frequency designs.

HSpice solves Maxwell’s equations. Uses a quasi-static approximation. That is, it assumes that the line is

purely TEM – all fields perpendicular to the direction of propagation. Not strictly true for lossy lines.

Models frequency dependent losses using the following:Ro = DC resistance matrix

Rs = skin effect matrix

Go = shunt current due to free electrons

Gd = loss due to rotation of dipoles under the alternating field

fgd = cut-off frequency

20

0

1

1

gd

D

S

ff

fGGG

fjRRR

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Tools Requirements:

An accurate, fast transmission line engine The ability to handle non-linear models Features for helping the design engineer understand what is

happening in the system.

Types: General circuit simulation tools (Spice): Used by nearly

everyone at some point, but rarely for post-layout, full board simulations. Full versions cost several $K.

Dedicated transmission line simulators (Quad design, Interconnectix). Widely used by board designers for both pre- and post-layout simulation. They cost even more.

Complex field solvers (Speed2000, Ansoft HFSS). These typically use FDTD or TLM methods.

We’ll use some variant of Spice.

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Circuit Elements

We’ll need to use the following circuit elements:Transmission lines: lossless, lossy, coupledVoltage & current sources: pulse and/or PWLResistorsCapacitors InductorsGround

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Summary

I/O circuit models can be structural (transistor) or behavioral. Each has advantages and drawbacks and may be applicable in the design process.

Non-linear behavioral models are widely used. IBIS is the industry standard format for behavioral

modeling. We’ll use linear models and Spice in this class.

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References

S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.

H. Johnson and M. Graham, High-Speed Signal Propagation: Advanced Black Magic, Chapter 13, Prentice Hall, 2003, 1st edition, ISBN 0-13-084408-X.

Avant! Corporation, True-HSpice™ Device Models Reference Manual, Release 2001.4, Revision A, December 2001, Chapter 6, pp. 6-1 to 6-66.

D. Kuznetsov, “Optimal Transient Simulation of Transmission Lines,” IEEE Trans., Circs. Syst., vol. 43, pp. 110-121, February 1996.

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References

J. Powell, “Spice or IBIS: How and When to Choose Between These SI Simulation Modeling Approaches,” Printed Circuit Design, pp. 12-17, May 1999.

K. Felton and T. Westerhoff, “High-Speed PCB Simulation: Is it Time for a Change,” Printed Circuit Design, pp. 42-45:63, June 1999.

L. Green, “Models for Signal Integrity Simulation: What You Need to Know About SPICE and IBIS,” Printed Circuit Design, pp. 22-24, October 1999.

G. Aldrich, “Designing PC Motherboards: Little Margin for Error Printed Circuit Design, March 1999.

D. Duehren, et. al., “I/O-Buffer Modeling Spec Simplifies Simulation for High-Speed Systems,” September 1994, http://www.eia.org.eig/ibis/intel.htm.

P.W. Tuinenga, A Guide To Circuit Simulation & Analysis Using Pspice, Prentice-Hall, Englewood Cliffs, NJ, 1988.