© fraunhofer ims version 6.1. image sensor design and technology development at fraunhofer ims dr....
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© Fraunhofer IMS
Version 6.1.
Image Sensor Design and Technology Development at Fraunhofer IMSDr. Sascha Weyers
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Fraunhofer IMSInfrastructure – CMOS Fab
Total area: 1300 m2
Clean room class: 10
Wafer size: 200 mm (8 inch; 0.35 µm)
Staff: working in 4 shifts / 7 days a week
Capacity: > 70.000 Wafer p.a.
Excellence of the CMOS-Line Complete CMOS process line plus integrated
sensors (SOI, imager, pressure, mixed signal) ICs from a few 100 ASICs to few million
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Fraunhofer IMSInfrastructure – Microsystem Lab&Fab
Total area: 600 m² Clean room class: 10Wafer size: 200 mm
Mission Extending the application areas of CMOS (“More
than Moore”) by post processing on CMOS wafers.
Development Activities Adding layers, structures, devices onto
preprocessed “intelligent substrates” (CMOS wafers) to create integrated sensor systems.
Examples: micro bolometer arrays for IR imaging, biosensors, opto sensors.
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Fraunhofer IMSInfrastructure – CMOS Backend
Total area: 300 m² Clean room class: 100 - 1000
Wafer size: 200 mm
Mission Test
Wafer & device tests for pilot series Application specific tests Sensor characterisation
Assembly Wafer grinding and dicing Die and wire bonding Encapsulation with glob-top or lids solder
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Service and Know-how - Optoelectronic Devices
In the field of „Optoelectronic Devices” Fraunhofer IMS is providing:
Service and Support
Development of novel optoelectronic devices
Use of standard CMOS processes: 0.5µm, 0.35µm, and foundry processes
Device modeling and optimization with advanced simulation tools
Characterization of „test inserts“ to extract and monitor device parameters (capacitance, dark current, spectral response, etc.)
p-sub
p-Epi
p-well p-well
n-well
p+ n+
Transfergate
STI
Floatingdiffusion node
d1
d2
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Service and Know-how - Optical CMOS Sensors
In the field of „Optical CMOS Sensors” Fraunhofer IMS is providing:
Service and Support
Design of customized image sensors and dedicated optical sensors
Wafer fabrication in Fraunhofer IMS fab (L035-OPTO) or foundries
Electro-optical test on wafer and device level
Device qualification Full service from design to fabrication
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Technology - CMOS 0.35µm Process “Opto”
The IMS 0.35µm CMOS process “Opto” is providing:
Opto Process Features Stitching Planarization UV transparent silicon nitride
passivation Salicide-blocking Color filter deposition & microlenses
Opto Devices Pinned photodiodes (low noise, low
dark current) High temperature photodiodes Dot array photodiodes Lateral Drift-Field Photodetectors
(LDPD) Single-Photon Avalanche Diodes
(SPADs) Embedded Charge Coupled Devices
(CCD)
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LDPD-Pixel DevelopmentStarting Point for Lateral Drift-field Photo Diode
cross sectional view (across the X-X’ axis)
metal shield
p- epitaxial layer
p+-substrate
Poly 1
p+
metal shield
»»
CG bulk
»»
Poly 2
TGn FDn
radiation ( hn )
bulk
p+
to readoutcircuit
top view
z-axis
x-axis
y-axis
x-axis
p-well p-well
FOX FOX FOXn+
LDPD n-well
increasing doping concentration
»»
CG
FD
n
TG
n
LDPD n-well
DG
DD
»»
L LCG
X X’
p+Y
Y’
LTG LFD
Key Features
CMOS Technology Low Noise / High
Sensitivity (high SNR) Non Destructive
Readout Time-Dependent
Charge Separation Random Reset Multiple Shutter Multiple Window
Integration Correlated Double
Sampling Feature
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LDPD-Pixel DevelopmentProcess Simulation for Doping Level Gradient
0 200
X (µm)
Pixel 1 Pixel 2
Implantation Dose 1
Implantation Dose 2
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LDPD-Pixel DevelopmentDevice Simulation
0 10 20 30 40 50 60 70 80-0,5
0,0
0,5
1,0
1,5
2,0
2,5
3,0
Pot
entia
l [V
]
Distance [µm]
TG open
CG
TG
CG=1.8VFD=2.3VTG=0V / 2.0V
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metal shield
p- epitaxial layer
p+-substrate
Poly 1p+
metal shield
»»
CG bulk
»»
Poly 2
TX3 FD3
radiation ( hf )
cross sectional view
p+
bulk
p+
to readoutcircuit
top viewCG F
D3
TX
3
FD1
TX1
FD2
TX2
z-axis
x-axis
y-axis
x-axis
p-well p-well
FOXFOX FOX FOXn+
LDPD n-well
increasing doping concentration
DD
TX
4
PPD n-well
Key Elements of the LDPD ToF-Pixel
LDPD-Pixel as basic element
Charge Collection (CG)-Electrode: MOS-capacitor with gate oxide
4 Transfer Gates (TX1…4): MOS-capacitor with oxide-nitride- oxide (ONO) isolation stack
4 Floating Diffusions (FD1…3,DD): n+-diffusion areas
LDPD-Pixel ApplicationTime-of-Flight Pixel
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LDPD-Pixel ApplicationSensor Architecture
Key Elements of the LDPD ToF-Sensor
Pixel Matrix with in-pixel accumulation functionality => reduction of readout noise
TX Level-Shifter and driver high speed driver for high speed charge transfer in the pixels (ns)
CDS stages background light subtraction and/or accumulation => reduction of readout noise
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CDS stages
128x96pixel matrix
pixel driver
LDPD-Pixel ApplicationRealization
Example: Cadence® Layout
A 3D image obtained using the ToF camera
Chip Photography
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Embedded CCDTechnology Option Development
Project ECTICISEmbedded CCD Based Time Delay Integration CMOS Image Sensor
CMOS/CCD TDI sensor for earth observation and high resolution scanning
Eureca / DLR
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Embedded CCDCharge Transport
Cross Section of Test Structure
Device Simulation for Test Structure
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Embedded CCDResults: Charge Transport
Time [µs]
Ou
tpu
t [V
]
Output
Output Gain = 0.91 V
Charge Transfer Efficiency
CTE128 = 99.95 % (for 128 pixels)
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CMOS-SPAD Development
EU Seventh Framework Programme (FP7, 2007-2013)Grant agreement n° 257646.
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CMOS-SPAD DevelopmentIntegration of SPAD Device in 0.35 µm CMOS Technology
Implementation in CMOS technology
Extension of the standard 0.35 µm CMOS technology
Layout for primitive SPAD device
Schematic Cross Section of SPAD Device
Layout of SPAD Devices for different Diameters
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CMOS-SPAD DevelopmentIntegration of SPAD Device in 0.35 µm CMOS Technology
Process Simulation of SPAD Device (Doping Density)
Electrical Device Simulation of SPAD Device (Electrical Field)
0 20 40 60 80 1001E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
A1 UBT
= 96 V
A2 UBT
= 90 V
I
[A]
U [V]
Type3
0 5 10 15 201E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
Chip A1 U
BT= 9.4 V
A2 UBT
= 9.5 V
I [A
]
U [V]
Type7
Characterization of Test Structures for Process Simulation
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CMOS-SPAD DevelopmentCharacterization of integrated SPAD Device
Dark Count Rate for different Excess VoltagesBreakdown Voltage for different Diameters
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CMOS-SPAD DevelopmentTiming Response
• FWHM < 100 ps (Ø = 10 µm)
• FWHM < 140 ps (Ø = 20 - 30 µm)
• Small wavelength influence
(%DFWHM < 5)
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CMOS-SPAD DevelopmentDark Count Rate Cumulative Distribution Function
• 30 µm SPAD 64 x 32 pixel array
• 50 µm SPAD 32 x 1 pixel array• 100 µm SPAD 32 x 16 pixel
array
tHOLD = 300 ns
< 5% hot SPADs20 µm SPAD (64 x 32) 2048-pixel array
Smart Pixels (pitch = 150 µm)
Active quenching circuit Shaping electronic Time to digital converter Counter Memory Buffer 3.14% fill factor for 30 µm
SPAD
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CMOS-SPAD DevelopmentBack-SPADs 3D Integration
1) Wafer-Processing
3) Back-Thinning
Standard CMOS-Wafer
BackSPADSOI-Wafer
GrindingEtching with stop
on BOX
4) Back Contacts
VIA through BOXMetal Padsfor Bonding
2) SLID-Bonding
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CMOS-SPAD DevelopmentBack-SPAD Process Variants
Fully-Depleted (HV) BackSPADsPartially-Depleted (LV) BackSPADs
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CMOS-SPAD DevelopmentBack-SPAD Dark Count Rate
0 1 2 3 4 5 6 7 8 9 10 11103
104
105
106
r = 49µmr = 48.6µm
r = 45.6µmr = 46.9µm
r = 48µm
Me
dia
n D
CR
SPAD Distance to Trench [µm]No Trenches
Above 1 µm SPAD to Trench Distancethere are no major differences in the DCR
r = 49µm
Comparison with CMOS SPAD
Fill FactorBackSPAD > 70%DCRBackSPAD ≈ 40 x DCRCMOS SPAD
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CMOS-SPAD DevelopmentBack-SPAD 3D Integration
Pads and SPADs on wafer bonded BackSPADs
Cross section of SOI wafer after waferbonding and backthinning
4 µm thick Si/SiO2 film
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Image Sensor Design and Technology Development at Fraunhofer IMS
Thank you for your Attention