컴퓨터구조론 교수 채수환. 교재 computer systems organization & architecture john d....
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컴퓨터구조론
교수 채수환
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교재
Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley
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평가방법
중간고사 40%학기말 고사 40%레포트 및 출석 20%계 100%
단 결석 ¼ 이상은 F 학점
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What must you do as a junior student
Improve your grade up to at least 3.5/4.5. Cultivate your English ability.Make good relationship with your friends.Think your future seriously.Be an expert in your field.Be flexible.
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Chapter 1 Digital Logic Fundamentals
Boolean AlgebraBasic Combinatorial LogicMore Complex Combinatorial ComponentsCombinatorial Circuit DesignBasic Sequential ComponentsMore Complex Sequential ComponentsReal World Example: PLD
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1.1 Boolean Algebra
Basic FunctionsAND NANDOR NOR NOTXOR XNOR (or Equivalence)Table 1.3: All possible binary Boolean
functions
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1.1 Boolean Algebra( 계속 )
Manipulation of Boolean AlgebraDeMorgan’s LawMintermKarnaugh map(K-map)
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1.1 Boolean Algebra( 계속 )
DeMorgan’s Law It allows a digital designer to convert an AND
function to an equivalent OR function and vice versa.
(ab)’=a’+b’ (a+b)’=a’b’
Example: (xy’+yz)’=(xy’)’(yz)’=(x’+y)(y’+z’)
=x’y’+x’z’+yy’+ yz’ = x’y’+x’z’+ yz’
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1.1 Boolean Algebra( 계속 )
MintermEach possible AND set of input values If there are two input values, x and y,
there are four possible minterms: x’y’, x’y, xy’, xy
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1.1 Boolean Algebra( 계속 )
K-map (Karnaugh-map)A useful device for minimizing logic
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Figure 1.1 K-maps
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1.1 Boolean Algebra( 계속 )
K-mapThe ordering of K-map inputs: Gray
codeA Gray code is a reflected code.
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Figure 1.2 Gray code sequence generation
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1.1 Boolean Algebra( 계속 )
Grouping on K-mapPrime Implicants(PI)Essential Prime Implicants(EPI):
groups which include cells that covered by only one group.
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Figure 1.3 (xy’+yz)’
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Figure 1.4 More complex function
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1.1 Boolean Algebra( 계속 )
Don’t careWhen some patterns of input values
will never occur, it is called don’t care condition.
We can treat the don’t care values as either 0 or 1, whichever makes it easier to group the minterms.
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Figure 1.5 A 7-segment LED driver
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1.2 Basic Combinatorial Logic
Gates: digital components that implement the logic functions. AND OR NOR NOT NAND NOR XNOR
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Figure 1.6 Logic Symbols
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1.2 Basic Combinatorial Logic(continued)
The gates can be combined to realize more complex functions.There are some realization ways for a given complex functions depending on the conditions.
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Figure 1.7 Two realization of the function wx’+x’z’+w’xyz
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1.2 Basic Combinatorial Logic(continued)
Buffers: Buffers do not perform any operations on its input.Regular buffer: to boost the current of
input to a higher level Tri-state buffer: it has a data input,
just like the regular buffer, but also an enable input, E.If E is disable state, it produces a high
impedance output.
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Figure 1.8 Logic symbols for buffers
Buffers:
Regular buffers(simply buffers): for boosting the current
Tri-state buffers: enable, high-impedance
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1.3 More Complex Combinatorial ComponentsMultiplexer(MUX) It chooses one of its data inputs and
passes it through to its output.Select signals are needed for select a
data input
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Figure 1.9 (a) Internal configuration of 4-to-1 MUX
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Figure 1.9 (b) Schematic representation with an active high enable signals
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Figure 1.9 (c) Schematic representation with an active low enable signals
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Figure 1.10 A 4-to-1 MUX constructed using 2-to-
1 MUXs
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1.3 More Complex Combinatorial Components(continued)
Decoder It accepts a value and decodes it. It has n inputs and 2n outputs,
numbered from 0 to 2n–1.
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Figure 1.11 Internal Configuration of a 2-to-4
decoder
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Figure 1.11 (b) Schematic representation with an active high enable signals
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Page 19, Figure 1.11 (c) Schematic representation with an active low enable signals
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1.3 More Complex Combinatorial Components(continued)
Encoder It is the exact opposite of the
decoder. It receives 2n inputs and outputs an n-
bit value corresponding to the input value.
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Figure 1.12 (a) Internal Configuration of
a 4-to-2 encoder
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Figure 1.12 (b) Schematic representation with an active high enable signals
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Figure 1.12 (c) Schematic representation with an active low enable signals
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1.3 More Complex Combinatorial Components(continued)
Priority encoderThe encoder works if zero or one
inputs are active, but fails.A priority encoder works just like a
regular encoder, with one exception, Whenever more than one input is active, the output is set to corresponding to the highest active input.
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Figure 1.13 (a) A 4-to-2 priority encoder
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Figure 1.13 (b) and (c) The other 4-to-2 priority encoder and its truth table
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1.3 More Complex Combinatorial Components(continued)
Comparator It compares two n-bit binary values to
determine which is greater, or if they are equal.
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Figure 1.14 1-bit comparator
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Figure 1.15 1-bit comparator with propagated inputs
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Figure 1.16 n-bit comparator constructed using 1-bit comparators with propagated inputs
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1.3 More Complex Combinatorial Components(continued)
AdderAdders are most commonly used, not
only to perform addition, but also to perform subtraction, multiplication, and division.Half adderFull adderRipple adderCarry lookahead addeer
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Figure 1.17 A half adder
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Figure 1.18 a full adder
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Figure 1.19 4-bit adder constructed using full adders
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1.3 More Complex Combinatorial Components(continued)
Full subtracterA full subtracter(Figure 1.20)Two’s complement addition
By doing this, a CPU may use a parallel adder for addition and subtraction.
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Figure 1.20 A full subtracter
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1.3 More Complex Combinatorial Components( 계속 )
Memory It is a group of circuit used to store
data.Address inputsData linesClasses of memory chips depending on
volatilityROMRAM
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Figure 1.21 ROM and RAM
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1.4 Combinatorial Circuit Design
BCD to 7-Segment Decoder
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Figure 1.22 A 7-Segment LED display
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Figure 1.23 (a) K-maps for designing segments
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Figure 1.23 (b) Circuits to implement segments b and c
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Figure 1A : LEDS (a) active high (b) active low
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1.4 Combinatorial Circuit Design(continued)
A sorter
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Figure 1.24 (a) A two-input compare-and –swap module
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Figure 1.24 (b) four-input data sorter
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1.5 Basic Sequential Components
The most fundamental components are latch and flip-flop Latch: level-triggered Flip-Flop: edge-triggered Triggering
Positive Negative
Clock It is used to synchronize the flow of data in
a digital system
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Figure 1.25 clock sequence
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1.5 Basic Sequential Components(continued)
D latch and D F-F It has one input, D, and a clock input. The value of D becomes output, Q,
after some delay. LD signal: It must be high as the clock
changes from 0 to 1 in order for the data to be loaded into the F-F.
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Figure 1.26 (a) Positive-edge triggered D F-F
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Figure 1.26 (b) Positive-level triggered D latch
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Figure 1.27 Positive level triggered D latch with set and clear
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Figure 1.28 SR latch
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1.5 Basic Sequential Components(continued)
JK-FF It resolves the problem of undefined
when SR=11
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Figure 1.29 J-K F-F
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Figure 1.30 T F-F
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1.5 Basic Sequential Components(continued)
Flip-flops and latches may be combined in parallel to store data with more than one bit.
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Figure 1.31 4-bit D F-F
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1.6 More Complex Sequential Components
Counters It stores a binary value and, when
signaled to do so, arithmetically increases or decreases its value.
Ripple counterUp/down counter
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Figure 1.32 4-bit Counter
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Figure 1.33 4-bit up/down counter
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1.6 More Complex Sequential Components
Shift registers it can shift data one bit position to
the right or left. It is particularly useful for certain
hardware multipliers and dividers.
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Figure 1.34 4-bit left-shift register
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1.7 Real World Example
PLAPALPLDFPGA
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Figure 1.35 PLA programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0
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Figure 1.36 PAL programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0