컴퓨터의 개념과 실습
DESCRIPTION
컴퓨터의 개념과 실습. Assembly Example. Python vs. Assembly. Python. Assembly. f = (g + h) – ( i + j ). ADD R5, R1, R2 ADD R6, R3, R4 SUB R0, R5, R6. f is mapped to R0 g is mapped to R1 h is mapped to R2 i is mapped to R3 j is mapped to R4. Python vs. Assembly. Python. - PowerPoint PPT PresentationTRANSCRIPT
Memory/Storage Architecture Lab
컴퓨터의 개념과 실습
Assembly Example
Memory/Storage Architecture Lab 22
Python vs. Assembly
Python Assembly
f = (g + h) – (i + j) ADD R5, R1, R2 ADD R6, R3, R4 SUB R0, R5, R6
f is mapped to R0 g is mapped to R1 h is mapped to R2 i is mapped to R3 j is mapped to R4
Memory/Storage Architecture Lab 33
Python vs. Assembly
Python Assembly
g = h + A[i] ADD R4, R2, R3 LDR R5, [R4] ADD R0, R1, R5
g is mapped to R0 h is mapped to R1 R2 contains the base address of array A[]. i is mapped to R3.
Memory/Storage Architecture Lab 44
Python vs. Assembly
Python Assembly if (i == j):
f = g + h else:
f = g – h
CMP R3, R4 BNE ELSE ADD R0, R1, R2 B EXIT ELSE: SUB R0, R1, R2 EXIT:
f is mapped to R0 g is mapped to R1 h is mapped to R2 i is mapped to R3 j is mapped to R4
Memory/Storage Architecture Lab 55
Python vs. Assembly
Python Assembly
while (save[i] == k):i = i + j
LOOP: ADD R4, R0, R3 LDR R5, [R4] CMP R2, R5 BNE EXIT ADD R0, R0, R1 B LOOP EXIT: i is mapped to R0
j is mapped to R1 k is mapped to R2 R3 contains the base address of array save[].
Memory/Storage Architecture Lab 66
Example Assembly Code & ISA
<Python>sum = 0list = [11, 13, 16]for i in range(0,3): sum = sum + list[i]
<Assembly> MOV R0, #0 MOV R2, #6L: ADD R2, R2, #1 LDR R1, [R2] ADD R0, R0, R1 CMP R2, #9 BNE L MOV R2, #10 STR R0, [R2]
<R egister & Memory>
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 0
PSR 0
R0 32
R1 43
R2 5
R3 13
R4 2
R5 7
R6 99
R7 8
Register Memory
Memory/Storage Architecture Lab 77
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
MOV R0, #0
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 0
PSR 0
R0 32
R1 43
R2 5
R3 13
R4 2
R5 7
R6 99
R7 8
PC 1
PSR 0
R0 0
R1 43
R2 5
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 88
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
MOV R2, #6
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 1
PSR 0
R0 0
R1 43
R2 5
R3 13
R4 2
R5 7
R6 99
R7 8
PC 2
PSR 0
R0 0
R1 43
R2 6
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 99
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R2, R2, #1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 2
PSR 0
R0 0
R1 43
R2 6
R3 13
R4 2
R5 7
R6 99
R7 8
PC 3
PSR 0
R0 0
R1 43
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1010
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
LDR R1, [R2]
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 3
PSR 0
R0 0
R1 43
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
PC 4
PSR 0
R0 0
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1111
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R0, R0, R1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 4
PSR 0
R0 0
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
PC 5
PSR 0
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1212
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
CMP R2, #9
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 5
PSR 0
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
PC 6
PSR 0x8000
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
31 30 29 28
1 0 0 0 …
N Z C V
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1313
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
BNE L
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 6
PSR 0x8000
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
PC 2
PSR 0x8000
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1414
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R2, R2, #1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 2
PSR 0x8000
R0 11
R1 11
R2 7
R3 13
R4 2
R5 7
R6 99
R7 8
PC 3
PSR 0x8000
R0 11
R1 11
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1515
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
LDR R1, [R2]
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 3
PSR 0x8000
R0 11
R1 11
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
PC 4
PSR 0x8000
R0 11
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1616
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R0, R0, R1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 4
PSR 0x8000
R0 11
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
PC 5
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1717
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
CMP R2, #9
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 5
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
PC 6
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
31 30 29 28
1 0 0 0 …
N Z C V
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1818
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
BNE L
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 6
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
PC 2
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 1919
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R2, R2, #1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 2
PSR 0x8000
R0 24
R1 13
R2 8
R3 13
R4 2
R5 7
R6 99
R7 8
PC 3
PSR 0x8000
R0 24
R1 13
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 2020
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
LDR R1, [R2]
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 3
PSR 0x8000
R0 24
R1 13
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
PC 4
PSR 0x8000
R0 24
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 2121
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
ADD R0, R0, R1
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 4
PSR 0x8000
R0 24
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
PC 5
PSR 0x8000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 2222
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
CMP R2, #9
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
PC 5
PSR 0x8000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
PC 6
PSR 0x4000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
31 30 29 28
0 1 0 0 …
N Z C V
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
Memory/Storage Architecture Lab 2323
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
BNE L
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 6
PSR 0x4000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 7
PSR 0x4000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
Memory/Storage Architecture Lab 2424
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
MOV R2, #10
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 7
PSR 0x4000
R0 40
R1 16
R2 9
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 8
PSR 0x4000
R0 40
R1 16
R2 10
R3 13
R4 2
R5 7
R6 99
R7 8
Memory/Storage Architecture Lab 2525
Instruction Set Architecture
Register Memory
Before Register and Memory After Register and Memory
Register Memory
STR R0, [R2]
Assumptions 32 bit ISA # of registers = 8 + PC (Program Counter)
+ PSR (Program Status Register) Memory size = 176KB
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 0
︙0xAFFF
PC 8
PSR 0x4000
R0 40
R1 16
R2 10
R3 13
R4 2
R5 7
R6 99
R7 8
0x8000 MOV R0, #0
1 MOV R2, #6
2 L: ADD R2, R2, #1
3 LDR R1, [R2]
4 ADD R0, R0, R1
5 CMP R2, #9
6 BNE L
7 MOV R2, #10
8 STR R0, [R2]
︙0x80FF
︙0xA000
︙7 11
8 13
9 16
10 40
︙0xAFFF
PC 9
PSR 0x4000
R0 40
R1 16
R2 10
R3 13
R4 2
R5 7
R6 99
R7 8