© 2013 ieee ieee international solid-state circuits conference 12.5:a 128gb 3b/cell nand flash...

©2013 IEEE ©2013 IEEE IEEE International Solid-State Circuits Conference

12.5:A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology 1 of 32

A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology

Speaker : Naso Giovanni – Micron Flash Design Center Avezzano Italy

ISSCC 2013 paper 12.5



Micron Flash Design Center Italy :G. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D’Alessandro, L. De santis, D. Di Cicco, W. Di Francesco, M.L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, M. Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, T. Vali

Micron Flash Design Center S. Jose (California) : :M. Helm, R. Ghodsi

Micron Flash Product/Process Engineering Boise (Idaho) : :R. Meyer, A. Goda, B. Filipiak

Design team



Agenda

Device features and architecture

Planar NAND cell

Ramped sensing for read and program verify

Techniques to mitigate distributions shift and widening

Typical single page uncycled time0 distributions

Summary



Technology 20nm Planar - 3 metals

Cell size0.0018 um2 (select gates included)

128 WLs per string

Chip size/capability 146.5 mm2 – 128Gb at 3bits/cell

Organization8192 Bytes per page x 2 (even/odd) x 384 pages x 1368 blocks x 2 planes x 8 IO

ECC 1104 Bytes per page

Array read time (us) 98 typ for 3bits/cell

Program time (ms) 2.3 typ for 3bits/cell

Erase time (ms) 3 typ for 3 bits/cell

Clock cycle time 6 ns ONFI3

Supported multiple bit/cell

1 bc – 2 bc – 3 bc (dynamic configuration)

Device features



Dynamic bits per cell configurationNumber of bits per cell can be dynamically set by the user to 1, 2, 3 using a command.

Program and read algo are optimized for the different bit percell configurations to achieve maximum performance and margins.

Pages addressing is automatically adjusted based on bits per cell configuration.

Typ/max 3 bits per cell 2 bits per cell 1 bit per cell

tBERS (ms) 3/10 2/10 2/10

tPROG (ms) 2.3/10 1.4/2 0.45/1

tR (us) 90/100 90/100 55



3bits/cell throughput

2 bytesCK = data DDR = = 333 MB/s 6 nsec

8192 Bytes x 2Sustain IN throughput = min(CK ; ) = 7.1 MB/s (dual plane) 2.3 msec

8192 Bytes x 2Sustain OUT throughput = min(CK ; ) = 182 MB/s (dual plane) 90 usec



Sustainable throughput

MB/sec 3 bits per cell 2 bits per cell 1 bit per cell

IN 7 11 36

OUT 182 182 297



Control logic

pumpsDatapath

Blo

ck s

ele

cto

rs

Pads

Plane 0 Plane 1

Device architecture

2 planes

8 I/O

128 Gbitat 3bitsper cell

146.5mm2

Page buffers Page buffers

Coredrive

Coredrive

LV



Device photo

array

String drivers

Pagebuffers

Blockselectors

Data path

2nd sensing

padscontroller Coredrive

pumpsLVanalog

Coredrive



Pla

ne

Plane organization

13

68

blo

cks

12

8 a

ctiv

e W

L p

er

blo

ck

Bytes : 8192 regular + 1104 ECC

48 Mbit at 3bc

384

page

s at

3 b

cPage buffers

block



Previous 25nm WRAP technology

IPD

F.G.

C.G.

A.A.

Gate OxideField Oxide

F.G.

22n

At 25nm and below, the WRAP technology does not allow to extend the Control Gate (C.G.) down to the Field Oxide.

Floating Gates (F.G.) have an interface area that produces coupling.



Planar NAND CellControl gate wrap-around design has a gap filling issue between floating gates as cell dimension further shrinks beyond 2X nm.

HfO2 High-K inter-gate dielectric (IGD) is used to achieve the improved cell coupling factor which is decreased in planar floating gate cell.(HfO2 dielectric constant is about 6x greater than SiO2 dielectric constant).

Planar technology has a reduced poly floating gate (FG) thickness to minimize cell-to-cell interference.

Metal control gate (W tungsten with Ta/HfO2 interface) is used to engineer the work function preventing the erase saturation and balancing program and erase capability. It also allows to reduce the control gate resistivity which is an important factor when geometries are very small.

Air gap isolation between word lines and bit lines is used to reduce cell cross-talk.



Planar NAND Cell

High K dielectricMetal control gatesAir gap for cell gates and BL

planar

wrap

Thin poly floating gate tomitigate FG-Fg interference

control gate



Planar NAND Cell airgap

Between word lines Between bit lines



Ramped sensing concept

Digital progressive values are generated by a counter and :1)Fed into all page buffers (PB)2)Converted into analog ramp by a digital to analog converter (DAC) and applied to Word Line (WL)Sensing /verify is performed at each ramp step

N bitscounter

WLDAC

Page buffers PB(0) PB(i)

WL

DAC

PBDAC

outinoutin



Ramped sensing to read threshold VT

PB(i)PBDAC

out

SABL

WLen

en

saout

BL charged -> saout =0BL discharged -> saout =1

At each WL step the Bit Line (BL) is pre-charged andthe current flowing into string is sensed by Sensamp (SA). If it is greater than a limit the digital value (PBDAC) is stored into each Page Buffer PB(i) and available at the output (out) and subsequent sensings are disabled.

strin

g



Ramped sensing for program verify

PB(i)PBDAC

in

SABL

WL

mat

ch

en

saout

strin

g

BL charged -> saout =0BL discharged -> saout =1

en

inhibit L

diff

BL is pre-chargedSense is enabled (en)

if BL is discharged, then no inhibitif BL stay charged, then

if match, then inhibitif no match, then no inhibit

1

2

a

b



Ramped sensing to evaluate distribution

PB(h)PBDAC

out_h

saou

t_h

L

VTxdiff

PB(k)

out_k

saou

t_k

L

diff

count

An embedded circuit allows to evaluate with a single rampsensing operation how many cells have a specific threshold value VTx.

After a complete ramp sensing operation is performed, each page buffer contains the VTvalue associated to its cells.

These VT’s can be compared with a specific value VTx andcounted



Analog circuits for ramped sensingWL (Volt)

time

Finalvalue

Initialvalue

Initial and final values of the ramp can be adjusted for temperature compensation.

Uniform or non-uniform compensation is provided.

nominal

non uniform compensation

uniform compensation



Analog circuits for ramped sensing

Register_2

Temperaturecompensation

DAC_2

Mem

ory

cont

rolle

r

Register_1

Register_0

DAC_1

DAC_0

Band gapreference

Mem

ory

core

resi

stor

WL

Initialvalue

Finalvalue

1) DAC_1 and DAC_2 to change start/end points of the ramp2) DAC_0 to generate ramp steps



Techniques to mitigate distributions shift and widening

1) Pre compensation to mitigate FG-FG interference in program operation

2) Corrective read to mitigate FG-FG interference in read operation

3) Channel calibration to rebalance the read levelsby detecting the actual distributions separation.This technique minimizes the Bit Error Rate (BER)

due to cycling/retention



Pre compensation to mitigatefloating gate to floating gate interference

Pre-compensation is a technique that can be applied during a program operation of a page and is performed internally to the chip.

Its purpose is to mitigate the floating-gate to floating-gate interference on the actual page to be programmed coming from next surrounding pages in a stream.

The external controller must provide the content of nextpages to be programmed in order to account for possibleaggressions on the actual page.




Pre compensation can take into account interference coming either from adjacent bit lines (odd page programmed after even page) or from adjacent word lines to be programmed next.

Cells that will not be aggressed are programmed at their target value.

Cells that will be aggressed are programmed at lower level in a way that they will be read at the target value after the aggression.



bl0 bl1

WLn

WLn+1

even

odd

bl2 bl3

VT

VT*

no FG-FG

max FG-FG

goal for target cells on WLn

bef

ore

aggr

esso

r pr

ogra

maft

er a

ggre

ssor

pr

ogra

m

Cells that willnot be aggressed

Cells that willbe aggressed


Page

buff

er

Page

buff

er



Corrective read to mitigatefloating gate to floating gate interference

Corrective read is a feature having the purpose to perform data correction needed to compensate floating-gate tofloating-gate interference after data (both victims and aggressors) have been programmed.

Different flavors of corrective read are possible : aggression from upper WL, from single or both adjacent BLs.

The corrective read features is activated by the external controller when error level is greater than the ECC capability and it is performed internally to the NAND.



Corrective read to mitigatefloating gate to floating gate interference

VTVT

globaldistributionglobaldistribution

non aggressed cellsnon aggressed cells aggressed

cellsaggressed cells

tt

- 2nd read ramp on selected WL.- only not aggressed cells are enabled to be sensed

- 2nd read ramp on selected WL.- only not aggressed cells are enabled to be sensed

tt

- 3rd read with shifted ramp on selected WL- only aggressed cells are enabled to be sensed

- 3rd read with shifted ramp on selected WL- only aggressed cells are enabled to be sensed

tt

1st read ramp on adjacent WL to detect the aggressors

1st read ramp on adjacent WL to detect the aggressors



Channel calibration to minimize BER

Purpose of Channel Calibration is to detect a read level corresponding to the maximum separation (minimum overlap)between two consecutive distributions.

It can mitigate overlaps due to different reasons :1)Retention (down shift on upper distributions)2)Cycling (distributions sigma widening : upper tail shift)3)Temperature

Channel Calibration is performed upon user request when the BER (Bit error Rate) level is considered too high for theselected ECC technique.



Channel calibration to minimize BERChannel Calibration is organized in two phases :1)Optimum read level detection2)Calibrated read using the optimized levels

The optimum read level detection can be performed in two ways (they have different accuracy and different performing penalties) :1) Single optimum read level detection (usually between two consecutive higher distributions). In this case, all the remaining read levels are rebalanced using a model to account for optimum read levels of the lower distributions.2) Multiple optimum read level detection : the optimum value

is detected for all the read levels

Channel Calibration can be performed once per block and usedfor all the pages of the block.



Start read ramp to detect VT of each cell

Original valley(start value)

count # cells associated to start VT value

Select VT corresponding to min count

Actual valley

Perform a read levelrebalance

Perform a read operation using the new read levels

calib

ratio

n se

arch

calib

rate

d re

adChannel calibration to minimize BER

count # cells associated to lower VT values

Threshold VT

Time penalty for each optimum search :40% of tread in case 500 bytes and 8lower levels are used.



Typical single page uncycled time0 distributions

Threshold VT (arbitrary unit)

sig

ma



Press release



Summary

A 3bit/cell 128Gb NAND Flash at 20nm planar NANDtechnology was presented.

The planar NAND technology allows to perform a shrink in word line and bit line directions while reducing floating gate to floating gate interference compared to the WRAPtechnology.

Design techniques :- Pre conditioning- Read compensation- Channel calibration allow to minimize the Bit Error Rate due to interference,cycling, endurance.

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