© 2010 Altera Corporation—Public

Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth

2010 Technology Roadshow

© 2010 Altera Corporation—Public

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Agenda

The need for bandwidth The challenge Introducing 28-nm Stratix V FPGAs and

HardCopy V ASICs Key innovations and benefits Summary

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Expanding Bandwidth Demands

Mobile Internet

Estimated 1.7B users by end of

2013

Fiber to the Home

Estimated ~130M

connections by end of 2013

Cloud Computing

Hosted mobile applications estimated to reach 998M

users by 2014

Mobile Backhaul

Estimated 90,000 Gbps of capacity required by end

of 2013

3G Networks

Expected to be 38% of worldwide market by end of

2013

LTE/WiMAX (4G)

~5.6M users expected by end

of 2013

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Market Dynamics for High-End Systems

Mobile Internet driving bandwidth at 50% annualized growth rate

Fixed footprints Existing power

ceilings 40G/100G system

deployment with 200G/400G on the horizon

Communications Broadcast Military Computer & Storage

Worldwide proliferation of HD/1080p

Move to digital cinema and 4K2K

Fixed power budget

Heightened intelligence and defense needs

More sensors, higher precision driven to decision points faster

Power and uptime critical

Demand for Higher Bandwidth in Same Footprint at Same or Lower Power and Cost

Higher bandwidth, performance and lower latency

New interface standards with PCI Express Gen3 and QPI

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Increasing Bandwidth with Strict Power and Cost Budgets

How to Increase Bandwidth, Without Increasing Cost or Power?

Bandwidth

Price/Power

Time

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TSMC’s High-Performance 28-nm Process 28-nm process advantages

2X the capacity 35% higher performance than alternative

process options Analog performance advantages enable

faster and more power efficient transceivers Enables 30% lower total power

Altera’s patented process innovations address yield, performance, and power Redundancy Programmable Power Technology Customized extra-low leakage devices

17-year relationship, with joint development

First to 40 nm, First to 28 nm

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Innovations to Address the Challenge

28-nm high-performance process

Embedded HardCopy Blocks

Partial reconfiguration

12.5-Gbps transceivers

28-Gbps transceivers

Highest IntegrationUltimate Flexibility

Highest Bandwidth

Stratix V FPGAs and HardCopy V ASICs: A New Class of Devices, Ready for the

Challenge

HardCopyBlock

Enhanced Fabric with Partial Reconfiguration

HardCopyBlock

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Stratix V FPGAs – Built for BandwidthHighest Bandwidth

Hard IP and Flexibility

IP Solutions andEcosystem

Highest bandwidth 66 transceivers capable of 12.5 Gbps and

7 x72 800-MHz DDR3 interfaces Devices with 28-Gbps transceivers

Unprecedented level of integration Embedded HardCopy Blocks supporting PCI

Express Gen3 and 40G/100G Ethernet High-performance, high-precision DSP Enhanced logic fabric with 1,100K LEs,

53 Mb RAM, and 3,680 18x18 multipliers Ultimate flexibility

Fine-grain and easy-to-use partial reconfiguration Configuration via PCI Express

50% higher system performance and 30% lower power

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HardCopy V ASICs – Risk-Free Path to ASIC

Risk-free path to lower cost and up to 50% lower power with HardCopy V ASIC

Up to 2X core performance improvement

One design, one IP set, one tool delivers both FPGA and ASIC implementations

Low NRE, with fast and predictable turnaround times

Guaranteed first-time right

Highest Bandwidth at Lowest Cost and Power

No-Risk Path to Volume Production

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Stratix V Device Family Variants Stratix V GT FPGA

Optimized for applications requiring ultra-high bandwidth and performance with 12.5-Gbps and 28-Gbps transceivers

Stratix V GX FPGA For high-performance, high-bandwidth

applications with transceivers up to 12.5 Gbps

Stratix V GS FPGA Optimized for ultra-high performance DSP,

high-bandwidth applications with transceivers up to 12.5 Gbps

Stratix V E FPGA For highest density, high-performance

applications

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Stratix V High-Bandwidth Transceivers Up to 66 identical, continuous-range,

low-power, backplane-capable transceivers running at 150 Mbps to 12.5 Gbps

Devices with 28-Gbps transceivers Sub-picoseconds jitter for best eye

opening and system BER performance

Dynamic reconfiguration of transceiver settings

On-die instrumentation – EyeQ eye viewer per transceiver channel

12.5- and 28-Gbpstransceivers

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Stratix V FPGA On-Die Instrumentation View receiver signal margin with Altera’s EyeQ eye viewer Complete vertical/horizontal reconstruction of eye opening Engage in live debug while fine-tuning for ideal

equalization

Minimize Board Bring-Up/Debug Time with Dynamic Reconfiguration and EyeQ

Tx Rx

Lossy Medium

Pre-Emphasis EQ CDR

EyeQ

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Extending Transceiver Leadership

2X the transceiver bandwidth at the same power

50% lower power per transceiver channel

200 mW per 28-Gbps transceiver or ~7mW/Gb

Stratix V FPGAs168 mW/Ch

@ 12.5 Gbps

0

50

100

150

200

250

6.5 Gbps 8.5 Gbps 10.3 Gbps 11.3 Gbps 12.5 Gbps

Po

we

r (m

W)

Pe

r C

ha

nn

el

(PM

A)

Stratix V Transceivers:Highest Bandwidth and Power Efficiency

28 Gbps

Transceiver PMA Power Per Channel

0

10

10

15

20

mW

Pe

r G

iga

bit

(G

b)

- 50% from 40 nm

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Highest memory bandwidth with up to 7 x72 DDR3 DIMMs with multi-rank support Half the latency with the new UniPHY Hard I/O FIFOs and read/write paths High system reliability through duty cycle

correction, calibration algorithms, and VT compensated deskew delays

Sharing of PLLs and DLLs across multiple interfaces

Guaranteed timing closure and focus on user productivity and ease of use

Delivering Highest Memory and I/O Performance and Bandwidth

Stratix V Memory and I/O Performance

InterfacePerforman

ce

DDR3 800 MHz

DDR2 400 MHz

QDR II 333 MHz

QDR II+ 550 MHz

RLDRAM II 533 MHz

LVDS 1.6 Gbps

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The New Embedded HardCopy Block Used to harden standard or

logic-intensive functions Reduces system cost and

faster time to market Provides 2X performance

enhancement 3-6 months turn-around time

for new variants to address targeted applications

14M ASIC Gates/700K LEs withup to 65% Lower Power than Soft

Implementation

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Partial Reconfiguration in Stratix V FPGAs Ultimate flexibility enabled by

partial and dynamic reconfiguration No system downtime with

dynamic updates Faster reconfiguration Reduces cost and power

through integration Built on proven methodology using

LogicLock™ and incremental compile

A1 C1

D1 E1 F1

B1

A2 C2

D1 E1 F1

B1

A2 C2

FP

GA

Co

reF

PG

A C

ore

Partial Reconfiguration for the Core

Tra

nsc

eiv

ers

Tra

nsc

eiv

ers

Dyn

amic

Rec

on

fig

ura

tio

nfo

r T

ran

scei

vers

#1 in Productivity and Performance

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Configuration Via PCI Express (CvPCIe) Initialize or update FPGA fabric via PCI

Express (PCIe) Three steps for using CvPCIe

Program the PCIe hard IP (HIP) via serial SPI flash device

Program autonomous HIP before FPGA CvPCIe completes programming of FPGA

Always meet PCIe link bring-up time < 100ms

Lower cost by using cheaper configuration file memory

Faster configuration and enhanced system flexibility

4 pins

ConfigurePCIe HIP

PCIe LinkGen1/2/3x1, x2, x4, x8

Load FPGA Image

via PCIe Link

Serial SPIFlash

PC

Ie H

ard

IP

E

nd

po

int

HostPC

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Altera Leads the Way Again in Fabric Innovation

Higher Logic Efficiency and System Performance

Reg

FullAdder

12345678

AdaptiveLUT

Reg

Reg

Reg

FullAdder

Reg

FullAdder

12345678

AdaptiveLUT

Reg

Reg

Reg

FullAdder

Reg

FullAdder

12345678

AdaptiveLUT

Reg

Reg

Reg

FullAdder

Reg

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12345678

AdaptiveLUT

Reg

Reg

Reg

FullAdder

Enhanced adaptive logic module (ALM) with 4 registers 5.5X more routing connections than competing devices Enhanced embedded memory structure for more

memory bits and ports with M20K Faster MLAB blocks and support for wide shallow FIFOs High-resolution clock synthesis with up to 32 fractional

PLLs More clock sources and networks with the ability to

power down unused logic

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The Need for Variable Precision in DSP Addresses the key challenge of supporting multiple

precision requirements of various systems

9x9 12x12 18x18 18x36 27x27 36x36 54x54

DSP SYSTEM PRECISION

VIDEO

WIRELESS, MEDICAL

MILITARY, TEST, HP COMPUTING

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First Variable-Precision DSP BlockDSP Precision Modes

Three independent 9x9 One complex 27x27 (four cascaded blocks)

Two independent 18x18 (32-bit resolution) One complex 18x25 (three cascaded blocks)

One independent 27x27 Sum of two 18x18

One independent 18x36 Sum of four 18x18 (two cascaded blocks)

One independent 36x36 (two cascaded blocks) Sum of two 18x36 (two cascaded blocks)

One independent 54x54 (four cascaded blocks) Sum of two 27x27 (two cascaded blocks)

Additional features for more efficient implementation of DSP algorithms

1. 18-/26-bit pre-adder2. Internal coefficient storage3. 64-bit accumulator4. 64-bit cascade bus

3

1

2

4

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Highest System Performance on 28 nm TSMC’s high-performance

process 50% increase in memory

interface performance 1.6-Tbps serial switching

capability Enhanced core fabric 1,840 GMACS of signal-

processing performance Embedded HardCopy Blocks

for 2X performance vs. soft logic

800-MHz DDR3 DIMM

12.5-/28-Gbps Serial

Transceivers

Embedded Hardcopy Blocks

600-MHzMemoryBlocks

Enhanced ALM and Routing

50% Increase in System Performance

Up to 3,680 Variable-Precision DSP Blocks

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Stratix V Technologies to Control PowerPower Reduction Method

Lower Static Power

Lower Dynamic Power

28-nm process innovations Programmable Power Technology Customized extra-low leakage devices Lower core voltage (0.85 V) Extensive hardening of IP, Embedded HardCopy Blocks

Hard power-down of functional blocks More granular clock gating Partial reconfiguration DDR3 and dynamic on-chip termination Quartus II software PowerPlay power optimization

30% Lower Total Power

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A Complete SolutionA Complete Solution

DesignSoftware

Intellectual Property

SOPC BuilderAdvanced DSP

Builder

EmbeddedSoft-Core

Processors

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Highest bandwidth with 12.5- and 28-Gbps transceivers

Highest level of system integration through extensive hard IP integration and the new Embedded HardCopy Blocks

50% higher system performance at 30% lower total power

Ultimate flexibility with easy-to-use partial reconfiguration

Lowest risk path to HardCopy V ASICs Productivity advantage with Quartus II software

system solutions, tools, and IP for vertical markets

Stratix V FPGAs and HardCopy V ASICs

Built for Bandwidth

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Learn More

Download the white paper Introducing Innovations at 28 nm to Move Beyond

Moore’s Law

Download the Stratix V Device Handbook

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Thank You!

For more information visit: www.altera.com