© 2009 ying zhou - university of...
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CARBON NANOTUBE SYNTHESIS ON CMOS SUBSTRATE VIA LOCALIZED RESISTIVE HEATING
By
YING ZHOU
A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE
UNIVERSITY OF FLORIDA
2009
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© 2009 Ying Zhou
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To my parents and my dear loving husband who have always given me the greatest love, encouragement, and support
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ACKNOWLEDGMENTS
First I have to thank my advisor, Dr. Huikai Xie, for his academic guidance, support and
encouragement. I started working for Dr. Xie when I came to UF in the fall of 2007. From the
first weekly research report to the first group presentation, from the layout to the fabrication,
from the first conference abstract to the first journal manuscript, Dr. Xie taught me a lot and I
enjoyed working on the project. I would also like to thank my other two committee members,
Dr. Ant Ural and Dr. Jing Guo, for their help and guidance, and my project partner Jason Lee
Johnson. Jason and I have been working together for two years, and he did a lot for this project.
I owe a lot of gratitude to our BML lab members, especially Kemiao Jia, Lei Wu and
Sagnik Pal. Kemiao and Lei trained me to do the fabrication when I came to UF. At that time, I
had little hand-on experience. Sagnik and I discussed the microheater reliability issues together
and I appreciate the time that he gave for discussion. I would like to thank Sarah Maley from Air
Force for taking the thermal imaging. The data obtained from those images are very helpful for
temperature distribution investigation. I would also like to thank NanoHoldings LLC for
supporting this project and MOSIS Educational Program for offering us a free CMOS foundry
service.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS.................................................................................................................... 4
LIST OF TABLES................................................................................................................................ 7
LIST OF FIGURES .............................................................................................................................. 8
ABSTRACT ........................................................................................................................................ 10
CHAPTER
1 INTRODUCTION....................................................................................................................... 12
1.1 Carbon Nanotubes ................................................................................................................. 13 1.2 CNT-Based Devices ............................................................................................................. 16 1.3 CMOS-CNT Hybrid Devices ............................................................................................... 20 1.4 Thesis Outline ....................................................................................................................... 22
2 FROM MATERIAL TO INTEGRATED MICROSYSTEMS: CARBON NANOTUBES SYNTHESIS AND ASSEMBLY .................................................................... 23
2.1 Carbon Nanotubes Synthesis ................................................................................................ 23 2.2 CMOS-CNT Integration Challenges and Discussion ......................................................... 25 2.3 Synthesis Based on Localized Heating ................................................................................ 28 2.4 Summary................................................................................................................................ 30
3 THE INTEGRATION OF CNTS ON MOCK-CMOS SUBSTRATE USING LOCALIZED RESISTIVE HEATING ..................................................................................... 32
3.1 Microheaters Design ............................................................................................................. 32 3.2 Device Fabrication ................................................................................................................ 34 3.3 Microheater Characterization ............................................................................................... 37
3.3.1 Maximum Temperature Estimation .......................................................................... 37 3.3.2 Heating Experiment.................................................................................................... 39 3.3.3 High Temperature Reliability .................................................................................... 40 3.3.4 Local Temperature Distribution ................................................................................ 43
3.4 Room Temperature Carbon Nanotube Synthesis ................................................................ 45 3.5 Characterization of Carbon Nanotubes................................................................................ 47 3.6 Summary................................................................................................................................ 52
4 THE INTEGRATION OF CARBON NANOTUBES ON CMOS SUBSTRATE ................. 53
4.1 Integration Principles and Device Design ........................................................................... 54 4.2 Device Fabrication and Characterization ............................................................................ 60 4.3 On-chip Synthesis of Carbon Nanotubes ............................................................................ 67
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4.4 Characterization of Carbon Nanotubes and Circuit Evaluations ....................................... 68 4.5 Summary................................................................................................................................ 72
5 FUTURE WORK ........................................................................................................................ 74
LIST OF REFERENCES ................................................................................................................... 76
BIOGRAPHICAL SKETCH ............................................................................................................. 87
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LIST OF TABLES
Table page 2-1 MOSIS AMI C5 Technology ................................................................................................ 60
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LIST OF FIGURES
Figure page 1-1 Schematic structure of single-walled carbon nanotube and multi-walled carbon
nanotube with typical dimensions of length, width, and layer spacing in MWNTs. ......... 13
1-2 Honeycomb structure of a planar graphene sheet ................................................................ 14
1-3 The interplay of electrical, mechanical and optical properties of carbon nanotubes and possible corresponding CNT-based transducers. .......................................................... 17
1-4 The structure of NRAM at on and off states. ....................................................................... 21
2-1 Circuit schematic of the decoder consisting of NMOS and single-walled carbon nanotubes ................................................................................................................................ 26
2-2 Process flow to integrate MWNT interconnects on CMOS substrate. SEM image of one MWNT interconnect (wire and via). .............................................................................. 27
2-3 SEM images of vertically aligned CNFs grown by PECVD deposition at 500°C, 270°C, and 120°C.. ................................................................................................................ 28
2-4 Fabrication process and localized heating concept. ............................................................. 29
2-5 Schematic of the cross-sectional layout of the chip.. ........................................................... 30
3-1 Structural demonstration of mock-CMOS platinum microheater ....................................... 33
3-2 Cross-sectional view of the proposed process flow. PECVD SiO2 deposition. Pt sputtering and lift-off to form heater and pads ..................................................................... 35
3-3 SEM pictures of fabricated microheaters.............................................................................. 36
3-4 I-V characterization of microheater. Temperature estimated based on resistance change. .................................................................................................................................... 38
3-5 Microscopic images under applied voltages of 2.28 V, 2.62 V, and 3.00 V, respectively. ............................................................................................................................ 40
3-6 Embedded straight line Pt microheater I-V characteristics.. ............................................... 41
3-7 The formation and growth of holes in the 100-nm Pt/10-nm Ti thin film. After 0 hour at 900°C. After 2 hours at 900°C. After 6 hours at 900°C. After 9 hours at 900°C.. ........ 43
3-8 Thermal imaging of Design-1, Design-2 and Design-3 ....................................................... 44
3-9 Dense film of CNTs over micro-hotplate surface (Design-1) ............................................. 45
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3-10 Localized synthesis of CNTs suspended across the trench, showing good CNT alignment ................................................................................................................................ 46
3-11 I-V characteristics of SWNTs contacted by Pt electrode. It was measured on the same device shown in Fig. 3-10c .......................................................................................... 48
3-12 Demonstration of the types of nanotube nano-to-micro contacts ....................................... 49
3-13 I-V characteristics of CNTs contacted by Pt electrode ........................................................ 50
3-14 Response curve to oxygen vs. time ....................................................................................... 51
3-15 Measured resistance vs. temperature relationship. ............................................................... 51
4-1 The 3-D schematic showing the concept of the CMOS integrated CNTs .......................... 55
4-2 A typical heater design with stripe-shaped resistor.............................................................. 57
4-3 Schematic layouts showing a 3 μm × 10 μm microheater with a paralleled bridge as the secondary wall and four configurable input pads, a 6 μm × 20 μm microheater with multiple tips as landing walls, and a microheater with opposing sharp tips . ............ 58
4-4 Schematic layouts of the chip, including test circuits and 13 embedded microheaters ..... 59
4-5 Mastless post-CMOS MEMS fabrication process flow: CMOS chip from foundry. SiO2 dry etch. Al etch. ........................................................................................................... 61
4-6 The CMOS chip photograph (1.5 × 1.5 mm2) after foundry process ................................. 63
4-7 I-V characterization of a 6 μm × 20 μm microheater ........................................................... 66
4-8 Localized synthesis of carbon nanotubes grown from the 3 μm × 3 μm microheater and the 6 μm × 6 μm microheater, suspended across the trench and connecting to the polysilicon tip/wall ................................................................................................................. 68
4-9 I-V characteristics of the as-grown CNTs. The I-V curve is measured between two polysilicon microstructures contacting the CNTs. ............................................................... 69
4-10 DC electrical characteristics of single transistors before and after CNT growth ............... 69
4-11 SEM images showing the catalyst layers on silicon dioxide surface , platinum microheater surface, and polysilicon microheater surface .................................................. 71
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Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Master of Science
CARBON NANOTUBE SYNTHESIS ON CMOS SUBSTRATE VIA LOCALIZED RESISTIVE HEATING
By
Ying Zhou
August 2009 Chair: Huikai Xie Major: Electrical and Computer Engineering
Since their discovery, the unique properties of carbon nanotubes (CNTs) have drawn great
attention, and a lot of applications have been demonstrated, such as CNT-based transistors,
circuitry interconnection and different types of sensors. Although CNTs exhibit extraordinary
performance, fabricating CNTs with precise control at a very large scale integration to constitute
a complete component library is still very difficult. Therefore, substantial efforts have been made
to develop CMOS-CNT hybrid devices that can take the advantages of both the maturity of the
CMOS technology and the unique properties of CNTs.
To fabricate such hybrid devices, the CMOS-CNT integration faces several challenges due
to the incompatibility between the CNT growth process and the post-CMOS processing. Among
several proposed methods, synthesis based on localized heating is one of the most promising
solutions, which satisfies both the high temperature requirement for CNT growth and the low
temperature limitation of post-CMOS processing. The growth is performed in a
room-temperature chamber, and the resistive heating of the microheater provides the local high
temperature to activate the growth just on the microstructure. This localized heating approach
solves the temperature incompatibility and eliminates the post-growth assembly steps. But a
simple and reliable fabrication process has not been developed for CMOS-CNT integration.
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The novel monolithic CMOS-CNT integration approach proposed in this work
incorporates the localized heating concept and maskless post-CMOS MEMS fabrication process
to solve the remaining problems. It uses the gate polysilicon to form the heaters for localized
heating and use the maskless post-CMOS fabrication to form micro-cavities for thermal
isolation. The polysilicon microheaters are fabricated with the gates of the transistors in the
foundry processes, so they can be simultaneously interconnected to each other without any need
of post-growth clamping or connection steps.
To accomplish this monolithic integration, mock-CMOS substrates are first investigated
for the process development and basic conceptual verification. Three types of platinum
microheaters have been designed, fabricated and characterized, demonstrating an ideal
temperature distribution profile. CNTs have been locally synthesized on Pt microheaters and
they show excellent alignment and reliable ohmic contacts with Pt electrodes. Then, CMOS
chips with testing circuits and embedded polysilicon microheaters have been designed and
fabricated through MOSIS foundry processes, followed by the microheater release using the
proposed maskless post-CMOS fabrication process. Room temperature localized synthesis of
CNTs on CMOS substrates has been realized, and the electrical characteristics of the neighboring
CMOS transistors have been proven unchanged after the CNT synthesis, indicating a successful
monolithic CMOS-CNT integration.
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CHAPTER 1 INTRODUCTION
Carbon Nanotubes (CNTs) have drawn great interest for their unique thermal, mechanical,
electrical, chemical and optical properties in recent years. Since their discovery in 1991 by
Iijima [1], various CNT-based applications have been demonstrated, ranging from composite
materials, molecular electronics, nano-probes and sensors, biomedical sensing to energy storage
and many others.
The demand for carbon nanotubes is increasing rapidly. A decade ago, carbon nanotubes
were very expensive and sold in small quantities for research purpose. However, the massive
production has driven price down substantially to below $100 per kilogram for multi-walled
carbon nanotubes [2], making them attractive for various commercial applications such as CNT
composite materials that can be added in polymers to improve their performance. After a
moderate annual growth rate of 40% till 2004-2005, the global CNTs market is expected to soar,
exceeding $1.9 billion by 2010 [3, 4]. Electronics, automotive and aerospace/defense industries
are three major end users. Among them, electronics devices are forecasted to be the largest
end-use sector in terms of dollar value, and composite materials in automotive industry to be the
largest sector in terms of volumes in the next few years [5].
Among intensive explorations on CNTs, this thesis is focused on the development of a
simple and reliable method of integrating CNTs with commercial foundry CMOS circuits. The
goal of this chapter is to give readers an introduction. First a brief description of CNT structure
will be given. Second, special properties of CNTs and the corresponding applications will be
discussed. Then, the emerging CMOS-CNT hybrid integration efforts will be presented. Finally,
a thesis outline describing the content of each chapter will be given.
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1.1 Carbon Nanotubes
Carbon nanotubes can be considered as the result of rolling up honeycomb graphene sheets
into hollow carbon cylinders. As shown in Fig. 1-1 [6], there are two basic types: single-walled
carbon nanotubes (SWNTs), which consist of a single graphene sheet, and multi-walled carbon
nanotubes (MWNTs), which are composed of several such sheets with one cylinder inside
another.
Figure 1-1. Schematic structure of A) SWNT and B) MWNT with typical dimensions of length,
width, and layer spacing in MWNTs [6].
The nanotube properties are extremely structure-sensitive, strongly dependent on the
nanotube diameter and chirality. By unwrapping a nanotube along its axis, the chirality can be
determined from the planar graphene sheet as shown in Fig. 1-2 A [7]. The two dashed tube axes
coincide with each other. One carbon bonding site on the left tube axis is chosen as the origin
point (0, 0) and the point C on the right tube axis corresponds to the same point on the nanotube.
The sheet is rolled until these two points coincide to form a SWNT. The chiral vector C is
formed by connecting the origin point (0, 0) to the point C, and it is specified by a pair of
integers (n, m) that relate C to two unit vectors 1a and 2a ( C = n 1a + m 2a ) [7]. The unit
vectors 1a and 2a are expressed as:
A) B)
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Figure 1-2. A) Honeycomb structure of a planar graphene sheet. A carbon nanotube indicated by
indices (11, 7) is formed by rolling up a single graphene sheet along the wrapping vector C, such that the origin (0, 0) coincides with point C [7]. Some SWNTs with different chiralities: B) armchair structure C) zigzag structure and D) chiral structure [8].
3( , ),2 2
aa=1a 3( , )2 2
aa= −2a (1-1)
in which a is the lattice constant of graphene sheet, n and m are the nanotube indices obtained
along vectors 1a and 2a , respectively. As shown in Fig. 1-2 A, the point (11,0) is in the direction
of 1a and its length is 11 times of the lattice constant, so n equals to 11 and m equals to 0.
A)
B) C) D)
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Similarly, we can obtain the value of other vectors such as (0,7) and (11,7). The chiral vector C
is equivalent to the circumference of the nanotube’s circular cross section. Thus the diameter of
such tubes can be calculated as:
2 2
a n m nmdπ+ +
= (1-2)
The typical diameter for single-walled carbon nanotubes is 1-1.5 nm [9]. In contrast, multi-
walled nanotubes have different numbers of walls and different separation distances between the
graphene layers, so their diameters vary typically from 5 nm to hundreds of nanometers [10].
The chiral angle θ, as shown in Fig. 1-2 A, is defined as:
12 2
1
2 2
C a n mcosC a n m nm
θ ⋅ += =
+ + (1-3)
If n and m are equal (Fig. 1-2 B), the nanotube is called “armchair”, with a chiral angle of
30°. If m equals zero (Fig. 1-2 C), the tube is called “zigzag”, with a chiral angle of 0°. All other
nanotubes having a configuration with 0° < |θ| < 30° are of “chiral” type (Fig. 1-2 D) [7, 8]. The
electronic properties of a nanotube depend on its atomic structure. It is theoretically predicted
that the armchair nanotubes are metallic with the bands crossing the Fermi level [11]. For all
other tubes, they can either be metallic or semiconducting. If n – m = 3N (where N is an integer),
such nanotubes are expected to be metallic. Otherwise, if (n – m) is not a multiple of 3, such
nanotubes are semiconducting with an energy gap of the order of approximately 0.5 eV [7]. For
semiconducting nanotubes with the same chirality, the energy band gap is only dependent on the
tube diameter, with an inversely proportional relation as:
02 c cgap
aEd
γ −= (1-4)
in which 0γ is the C-C tight-binding overlap energy, c ca − is the nearest neighbor C-C distance
(0.142 nm) and d is the diameter [7]. The theoretical analysis discussed so far regarding the
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chiral angle and the energy band gap is only applicable to SWNTs. The analysis is more
complicated for MWNTs due to the different number of walls and different structures of each
layer.
As we can see from the above discussion, the electrical properties of nanotubes are
strongly dependent on the nanotube diameter and chirality. The variegated atomic structures
bring perhaps the most extreme diversity and richness among nanomaterials. The interplay of
electrical, mechanical, and chemical properties of nanotubes further promises a wide range of
applications. Various CNT-based devices will be discussed in the next section.
1.2 CNT-Based Devices
Compared to SWNTs, MWNTs are generally easier to produce at large scale and thus less
expensive. Revenues generated from MWNTs were dominant for last few years, with an
estimated market of $290 million in 2006 [3]. Since MWNTs are usually used as composite
materials for their high thermal conductivity and to add mechanical strength and electrical
conductivity to polymers in products such as vehicle chassis and sports goods [4], their wide
variations in length, width and number of walls are not concerns at present. However, more
advanced uses of CNTs as functional devices demand SWNTs with specific types. This is an
area that is growing rapidly and provides the stage for nanotubes to show their fascinating,
unique talents.
C. Hierold et al. summarized possible CNT-based electrical, mechanical and optical
transducers and their applications in the matrix as shown in Fig. 1-3 [12]. Different inputs such
as electrical, mechanical and optical signals are listed in the first column of the matrix, and
different output signals are listed in the upper row. Each crisscrossed cell indicates the
corresponding transduction principle converting signal in one domain to another.
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Figure 1-3. The interplay of electrical, mechanical and optical properties of carbon nanotubes
and possible corresponding CNT-based transducers [12].
The upper left cell (electrical-electrical) represents the nano electronic device category, and
carbon nanotube field effect transistors (CNFETs) are the key focus of ongoing studies. Due to
the fundamental scaling limits of traditional silicon-based integrated circuits [13, 14], molecular
electronics as one of the new miniaturization strategies has drawn great attention. The
remarkable electrical properties of carbon nanotubes, such as a large current density exceeding
109 A/cm2 [15] and a high-mobility of 9000 cm2/V•s [16], make them ideal candidates for novel
molecular nanoelectronics, which has been intensively explored in recent years. Carbon
nanotube field effect transistors were first demonstrated using a back-gate configuration with one
semiconducting SWNT connected to two metal electrodes and Si substrate as a back-gate [17,
18]. The as-prepared semiconducting SWNTs with metal electrodes always exhibit p-type field
effect transistor (FET) behaviors at room temperature: negative gate voltages lead to an “on”
state of the CNFETs as a result of an accumulation of holes and an increasing conductance,
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whereas positive gate voltages deplete the holes and lower the conductance, leading to an
insulating “off” state. Under the electrostatic gating, the electrical conductance can vary by more
than 5 orders of magnitude [18]. This hole-doping characteristic has been reported by many
groups [17-19], and its mechanism was found to be attributed to the charge transfer between
SWNTs and adsorbed oxygen molecules [20-23], known as chemical gating effect. After
removing the oxygen, the extrinsically induced p-type FET behavior vanishes and the nanotubes
approaches an intrinsic semiconducting behavior [23]. The complementary n-type CNFETs can
be realized via chemical doping methods, such as charge-transfer doping with alkali metals and
SWNT sidewall functionalization with polymers [24-27]. Following the successful
demonstration of basic individual CNFET components, several research groups stepped towards
the integration of such nanotube FETs onto the same chip to form logic circuits ranging from
inverters, NAND and NOR gates to ac ring oscillators [28, 29]. Semiconducting CNFETs
promise very fast (THz) transistors [30], and metallic CNTs with excellent electrical
conductivity may enable the realization of electronic systems where both active components and
interconnection use the same material. However, so far large scale integration with predictable
performance and precise control has not been realized yet, primarily due to the lack of reliable
ways to directly produce large amounts of CNTs with identical desired type.
The upper center and center left cells cover the conversion between electrical signal and
mechanical deformation, and its potential applications as electromechanical transducers.
Tombler et al. [31] studied the effects of mechanical deformations on the electrical properties of
carbon nantubes by the AFM tip pushing experiment and demonstrated that increased bending
leads to decreased conductance by more than two orders of magnitude. Cao et al. [32] reported
piezoresistive gauge factors 0 0( / ) /( / )R R l lδ δ as much as 600 to 1000 under axial strains,
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compared to 200 of commonly used p-doped silicon [33]. Significant σ-π electron hybridization
effects resulting from the increased curvature produced by high-angle bending are proposed to be
the cause of the conductance decrease [34]. Based on the remarkable and reversible electrical
response to a mechanical load, a variety of different electromechanical sensors have been
demonstrated, some of which are listed in the center left cell. Electromechanical actuation
devices (upper center) operate in the opposite way: it utilizes the mechanical responses of carbon
nanotubes to electrical signals based on electrostatic [35] and piezoelectric effect [36, 37].
Applications include nano relays, nano tweezers and CNT-based mechanical memory cells,
etc. [38-40]. Photoelectronic transducers are based on photon emission and absorption.
Illuminated nanotube p-n junctions under bias can convert incident photon energy into electrical
energy. Current-voltage characteristics and power efficiency are functions of photon energy and
the energy conversion rate increases with decrease of nanotube diameters [41, 42].
Another important category, which is not listed in Fig. 1-3, is the CNT-based chemical/bio
sensors. Although CNTs are highly stable and chemically inert, the electrical properties of
semiconducting SWNTs (S-SWNT) are found to be extremely sensitive to charge transfer
between SWNTs and molecules adsorbed via non-covalent forces [8, 20]. This serves as the
basis for chemical sensors. Owing to their unique structure (nanometer range diameters and all-
on-surface atoms), nanotubes are suitable for miniaturization and chemical coating for high
selectivity. Such sensors exhibit faster response, smaller size, substantially higher sensitivity, and
no need to heat, but slower recovery time to gases, compared to existing metal-oxide-based gas
sensors. It has been reported that the electrical resistances of S-SWNTs changed dramatically by
several orders of magnitude when exposed to 200 ppm NO2 and 1% NH3 [20]. The sensing
mechanism is similar to the way that the conductance of silicon-based transistors being
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modulated by doping n- or p-type impurities (such as boron and phosphorus). NO2 is a strong
oxidizer with an unpaired electron, and can be regarded as p-type impurity. When exposed,
electron-withdrawing NO2 molecules increase the hole carriers in the as-grown p-type SWNTs,
leading to the modulation of the Fermi level in the semiconducting tubes towards valence band,
and thus a higher conductivity is induced [20]. In the opposite way, NH3 has a lone electron pair
to donate and will shift the Fermi level away from the valence band, resulting in hole depletion
and reduced conductance. The S-SWNT-based chemical sensors is applicable to other molecules
with electron-donating or withdrawing capabilities, such as oxygen and polymers [21, 24, 43].
Surface modification and functionalization, along with other methods, allow nanotubes to
interact with specific biochemical species, and can be used for biomedical applications, such as
protein-nanotube sensors, DNA detection sensors and active biomarkers [44-46].
1.3 CMOS-CNT Hybrid Devices
Although CNTs have been explored for various applications and exhibit extraordinary
performance as discussed in the previous section, fabricating CNTs with precise position,
chirality and performance control at a very large scale integration (VLSI) to constitute the
necessary library of components (transistors, diodes, resistors, capacitor, etc.) on a single
substrate has not been realized. Meanwhile, owing to the maturity of the standard silicon
technology and the unique properties of CNTs, substantial efforts have been made on the
development of CMOS-CNT hybrid integration technology that takes the advantages of both
CMOS and CNTs.
For nanoelectronics applications, high-performance carbon nanotube field effect transistors
can be integrated with conventional CMOS circuits that can provide power regulation, load
capacitors, and other peripheral devices. The CNT memory device is one of the numerous
examples. Since the further scaling of silicon-based memories is expected to approach the limits
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in the near future as the capacitor charge and writing/erasing voltages cannot be scaled down
[47], a highly scalable hybrid CMOS-molecular non-volatile memory has been widely explored,
where CNT-based memories are connected to the readout CMOS logic circuitry [48, 49]. A
nanotube random-access memory (NRAM) used in [49] is shown in Fig. 1-4. It is a non-volatile,
high-density, high-speed and low-power nanomemory developed by the company Nantero and it
is claimed to be a universal memory chip that can replace DRAM, SRAM, flash memory, and
ultimately hard disk storage [49, 50].
Figure 1-4. The structure of NRAM at A) on and B) off states [51].
For sensing applications, research groups have investigated the use of CMOS VLSI as
advanced system control and powerful signal processing for CNT sensor output to achieve
so-called “smart sensors”. Such CMOS interface architectures for resistive sensors can be used
to regulate the sensing temperature [52], widen the dynamic range [53], improve the
measurement accuracy [54], and provide multiple readout channels to realize electronically
addressable nanotube chemical sensor arrays [55]. Various sensors based on such CMOS-CNT
hybrid systems have been demonstrated [56-58].
Other attempts have been made to use MWNTs as CMOS interconnect for high
frequency applications [59], apply CNT-based nano-electromechanical switches for leakage
reduction in CMOS logic and memory circuits [60], to name a few.
B)
Interconnects
CNT ribbons
Electrode A)
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1.4 Thesis Outline
As discussed in Sections 1.3, the integration of carbon nanotubes with microelectronics
can make use of advantages of both. However, owing to the immature nanofabrication
techniques, most of the CMOS-CNT systems have been realized either by a two-chip solution or
complicated CNT manipulations. Integration challenges, such as temperature incompatibility,
will be discussed in detail in Chapter 2. The objective of this thesis is to develop a simple and
scalable monolithic CMOS-CNT integration technique, and our solution will be presented in
Chapter 3 and 4. Here we just give an outline of this thesis.
There are five chapters in this thesis. The first chapter gives an introduction and motivation
of this project. Chapter 2 first presents the CNT growth mechanism and the synthesis methods.
Then, the monolithic CMOS-CNT integration technique using localized resistive heating, as well
as other integration methods, will be discussed and compared in detail. In Chapter 3, three
microheater designs will be presented and analyzed by thermal imaging. Localized synthesis of
CNTs on this mock-CMOS substrate will be presented to demonstrate the concept of resistive
heating integration. Chapter 4 will focus on the monolithic CMOS-CNT integration. First, the
device design, including test circuits and embedded microheaters within a single chip, and some
design concerns will be presented and discussed. Then, a novel maskless post-CMOS surface
micromachining processing will be introduced, followed by the on-chip synthesis and
after-growth CNT characterization and circuit evaluations. Chapter 5 will discuss the future work
on this research topic.
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CHAPTER 2 FROM MATERIAL TO INTEGRATED MICROSYSTEMS: CARBON NANOTUBES
SYNTHESIS AND ASSEMBLY
Carbon nanotubes are the basic building blocks. This chapter will discuss the CNT growth
mechanism and the synthesis methods first. Then, in order for CMOS-CNT hybrid devices to be
efficiently and reliably functional, a robust CMOS-CNT integration process that is simple and
compatible with the mainstream foundry CMOS processes is of vital importance. Several
integration methods have been developed and will be discussed in this chapter, and the
room-temperature localized synthesis using Joule heating is of particular interest.
2.1 Carbon Nanotubes Synthesis
The mechanism of carbon nanotube formation is not completely understood. Although
great efforts have been made to investigate the growth mechanism, it is still shrouded in
controversy. Based on transmission electron microscope (TEM) observation, Yasuda et al.
proposed that CNT growth starts with rapid formation of rod-like carbons, followed by slow
graphitization of walls and formation of hollow structures inside the rods [61].
There are three main methods for carbon nanotubes synthesis: arc-discharge [62-64], laser
ablation [65-67], and chemical vapor deposition (CVD) [68-71]. The first two methods involve
evaporation of solid-state carbon precursors and condensation of carbon atoms to form
nanotubes. The high temperature involved (thousands of degrees Celsius) ensures perfect
annealing of defects, and hence these two methods produce high quality nanotubes. However,
they tend to produce a mixture of nanotubes and other byproducts such as catalytic metals, so the
nanotubes must be selectively separated from the byproducts. This requires quite challenging
post-growth purification and manipulation.
In contrast, the CVD method employs a hydrocarbon gas as the carbon source and involves
heating metal catalysts in a tube furnace to synthesize nanotubes. It is commonly accepted that
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the synthesis process starts with hydrocarbon molecules adsorbed on the catalyst surface. Then
the carbon is decomposed from the hydrocarbon and diffuses into the catalytic particles. Once
the superaturation is reached, carbons start to precipitate onto the particles to form carbon tubes.
After that, nanotubes can grow by adding carbons at the top of the tubes if the particles are
weakly adhered to the substrate surface. Nanotubes can also grow from the bottom if the
particles are strongly adhered [72]. The former is called the tip-growth model and the later is
called the base-growth model. Compared to the arc-discharge and laser ablation methods, CVD
uses much lower synthesis temperature, but it is still too high to directly grow on CMOS
substrates. In addition, CVD growth provides an opportunity to directly manufacture substantial
quantities of individual carbon nanotubes. The diameter and location of the grown CNTs can be
controlled via catalyst size [73] and catalyst patterning [74], while the orientation can be guided
by an external electric field [75]. Suitable catalysts that have been reported include Fe, Co, Mo,
and Ni [76].
Besides the CNT synthesis, electrical contacts need to be created for functional CNT-based
devices. It is reported that Molybdenum (Mo) electrodes form good ohmic contacts with
nanotubes and show excellent conductivity after growth, with resistance ranging from 20 kΩ to
1 MΩ per tube [77]. The electrical properties can be measured without any post-growth
metallization processing. The low resistance, however, tends to increase over time, which might
be due to the slight oxidation of the Mo in air. Other than that, electron-beam lithography is
generally used to place post-growth electrodes. Several metals, such as gold, titanium, tantalum
and tungsten, have been investigated as possible electrode materials and palladium top-contacts
are believed to be most promising [78].
25
2.2 CMOS-CNT Integration Challenges and Discussion
As mentioned in Chapter 1, a complete system with carbon nanotubes and microelectronic
circuitry integrated on a single chip is needed to fully utilize the potential of nanotubes for
emerging nanotechnology applications. This monolithic integration requires not only
high-quality nanotubes but also a robust fabrication process that is simple, reliable and
compatible with standard CMOS foundry processes. Such CMOS-compatible integration process
up to now remains a challenge, primarily due to the material and temperature limitations of
CMOS technology [79, 80].
As discussed in Section 2.1, thermal chemical vapor deposition has been widely used to
synthesize nanotubes. Research groups have been working on growing CNTs directly on CMOS
substrate using thermal CVD method. For example, Tseng et al. demonstrated, for the first time,
a process that monolithically integrates SWNTs with n-channel metal oxide semiconductor
(NMOS) FET in a CVD furnace at 875°C [81]. However, the high synthesis temperature
(typically 800-1000°C for SWNT growth [82]) would melt aluminum metallization layers and
deteriorate the on-chip transistors. Ghavanini et al. have assessed the deterioration level of
CMOS transistors when subjected to CVD synthesis techniques, and reported that one PMOS
transistor lost its function after the thermal CVD treatment (610°C, 22 min) [79]. As a result,
integrated circuits demonstrated by Tseng et al. using thermal CVD method, as shown in
Fig. 2-1, can only consist of NMOS and use n+ polysilison and molybdenum as interconnect,
which make it incompatible with CMOS VLSI foundry processes.
To address this problem, one possible solution is to grow nanotubes at high temperature
first and then transfer them to the desired positions on another substrate at low temperature.
However, handling, maneuvering, and integrating these nanostructures with CMOS chips/wafers
26
Figure 2-1. A) Circuit schematic of the decoder consisting of NMOS and single-walled carbon
nanotubes. B) Schematic of the cross-section of the decoder chip, interconnected by phosphorus-doped n+ polysiscon and molybdenum [81].
to form a complete system are very difficult. In the early stage, an atomic force microscope
(AFM) tip was used to manipulate and position the nanotubes into a predetermined location
under the guide of scanning electron microscope (SEM) imaging [83, 84]. Although this
nanorobotic manipulation realized precise control over both the type and location of CNTs, its
low throughput becomes the bottleneck for large scale assembly. Other post-growth CNT
assembly methods that have been demonstrated so far include surface functionalization [85],
liquid-crystalline processing [86], dielectrophoresis (DEP) [87-90], and large scale transfer of
aligned nanotubes grown on quartz [91, 92]. Among these methods, CMOS-CNT integration
based on DEP-assisted assembly technique has been reported, and a 1 GHz integrated circuit
with CNT interconnects and silicon CMOS transistors has been demonstrated by
Close et al. [59]. The fabrication process flow and the assembled MWNT interconnect are shown
in Fig. 2-2. The DEP process provides the capability of precisely positioning the nanotubes in a
noncontact manner, which minimizes the parasitic capacitances and allows the circuits to operate
above 1 GHz. However, to immobilize the DEP-trapped CNTs in place and to improve the
contact resistances between CNTs and the electrodes, metal clamps have to be selectively
A) B)
27
deposited at both ends of the CNTs (Fig. 2-2 A, step 3). The process complexity and low yield (~
8%, due to the MWNT DEP assembly limitation) are still the major concerns.
Figure 2-2. A) Process flow to integrate MWNT interconnects on CMOS substrate. B) SEM
image of one MWNT interconnect (wire and via) [59].
Alternatively, some other attempts have been made to develop low temperature growth
using various CVD methods [93-95]. Hofmann et al. reported vertically aligned carbon
nanotubes grown at temperature as low as 120°C by plasma-enhanced chemical vapor deposition
(PECVD) [94]. However, the decrease in growth temperature jeopardizes both the quality and
yield of the CNTs, as evident from their published results (shown in Fig. 2-3). The synthesized
products are actually defect-rich, less crystalline, bamboo-like structured carbon nanofibers
rather than MWNTs or SWNTs.
A)
B)
28
Figure 2-3. SEM images of vertically aligned CNFs grown by PECVD deposition at A) 500°C,
B) 270°C, and C) 120°C [scale bars: A) and B) 1 μm and C) 500 nm] [94].
2.3 Synthesis Based on Localized Heating
To accommodate both the high temperature requirement (800-1000°C) for high-quality
SWNT synthesis and the temperature limitation of CMOS processing (< 450°C), synthesis based
on localized heating has drawn great interest. Englander et al. demonstrated, for the first time,
the localized synthesis of silicon nanowires and carbon nanotubes based on microheater resistive
heating [96]. The fabrication processes and concepts are shown in Fig. 2-4. Operated inside a
room temperature chamber, the suspended micro-electromechanical systems (MEMS) structures
serve as microresistive heaters to provide high temperature at predefined regions for optimal
nanotube growth, leaving the rest chip area at low temperature. Using the localized heating
concept, direct integration of nanotubes at specific area can be potentially achieved in a CMOS
compatible manner, and there is no need for additional assembly steps. Attracted by this
promising technique, several research groups have followed up, and localized CNT growth on
various MEMS structures has been demonstrated [97-99]. However, the devices typically have
large sizes and their fabrication processes are not fully compatible with the standard foundry
CMOS processes. Although this concept has solved the temperature incompatibility problem
between CNT synthesis and circuit protection, the fabrication processes of microheater structures
B) C) A)
29
still have to be well designed to fit into standard CMOS foundry processes and the materials of
microheaters have to be selected to meet the CMOS compatible criterion.
Figure 2-4. Fabrication process and localized heating concept [96].
The progress towards complete CMOS-CNT system has been made. On-chip growth using
CMOS micro-hotplates was later demonstrated by Haque et al. [100]. As shown in Fig. 2-5,
tungsten was used to fabricate both the micro-hotplates (as the thermal source) and interdigitated
electrodes for nanotubes contacts. MWNTs have been successfully synthesized on the
membrane, and simultaneously connected to circuits through tungsten metallization. Although
tungsten can survive the high temperature growth process, and has high connectivity and
conductivity, Franklin et al. reported that no SWMTs were found to grow from catalyst particles
on the tungsten electrodes, presumably due to the high catalytic activity of tungsten towards
hydrocarbons [77]. Further, although the monolithic integration has been achieved, the utilization
of tungsten, a refractory metal, as interconnect metal is limited in foundry CMOS, especially for
mixed-signal CMOS processes. Tungsten is obviously not a good candidate as interconnect
metal compared with aluminum and copper. Other than the material, this approach is limited to
30
SOI CMOS substrates, requires a complex backside bulk micromachining process, and it has low
integration density.
Figure 2-5. A) Schematic of the cross-sectional layout of the chip. B) Optical image of the
device top-view, showing the tungsten interdigitated electrodes on top of the membranes, heater radius = 75 μm, membrane radius = 280 μm. [100].
2.4 Summary
From the reviews in Chapter 1, we know that a monolithic CMOS-CNT integration is
desirable to fully utilize the potential of nanotubes for emerging nanotechnology applications.
However, based on the above discussion of the existing approaches, we have the understanding
that although each method has its own merits, there is still a lack of integration technique that
can meet all the requirements and realize complete compatibility with CMOS processes.
To solve the problem, a simple and scalable monolithic CMOS-CNT integration technique
using a novel maskless post-CMOS surface micromachining processing is proposed in this
thesis. The approach is fully compatible with commercial foundry CMOS processes, and has no
specific requirements on the type of metallization layers and substrates.
Since CMOS fabrication is costly and time-consuming even through the MPW service of
MOSIS, mock-CMOS substrates will be used for the process development and basic conceptual
verification. Thus, in Chapter 3, a maskless post-CMOS MEMS process using inexpensive
A) B)
31
mock-CMOS substrates will be developed to demonstrate the localized growth of SWNTs using
platinum microheaters. Then Chapter 4 will present the demonstration of a novel
room-temperature on-chip synthesis of carbon nantobues via localized resistive heating and
maskless post-CMOS surface micromachining processing.
32
CHAPTER 3 THE INTEGRATION OF CNTS ON MOCK-CMOS SUBSTRATE USING LOCALIZED
RESISTIVE HEATING
As discussed at the end of the previous chapter, mock-CMOS substrates will be used to
demonstrate the localized heating and CNT growth in a room-temperature chamber. Room-
temperature CNT growth on real CMOS substrates will be presented in Chapter 4.
3.1 Microheaters Design
Several different materials have been investigated as the electrode material for CVD
growth of CNTs in the literature. Metals with relatively low melting temperature, such as gold,
become discontinuous as balling up during the high temperature growth process, while some
other candidates, such as Ti and Ta, tend to react with hydrogen and form volatile metal hydride
at high temperature [77]. In our experiment, platinum (Pt) has been chosen as the microheater
material due to its compatibility with CNT growth. Pt is a refractory metal with very high
melting temperature. And it has been widely used as contact electrodes in traditional CVD CNT
synthesis procedures and demonstrated good contacts with CNTs with resistance ranging from
10 kΩ to 50 kΩ [12].
The local temperature distribution and the maximum temperature are the key parameters
of the microheater structures. Since SWNT growth requires temperature as high as 800°C, the
resistivity of the heater, thermal isolation, thermal stresses, and structural stiffness must be taken
into consideration when designing the microheaters. A 3D model of the mock-CMOS
microheater is shown in Fig. 3-1 A. Suspended microstructures are created over a micro-cavity
for good thermal isolation. Platinum resistors are integrated as the heating source, and the local
electrical field (E-field) and growth temperature can be controlled by the microheater geometry
and power supply. Three types of microheaters have been designed. The first microheater design
(Fig. 3-1 B) is a micro-hotplate with a meander Pt microheater embedded. The hotplate is
33
supported by two anchored short beams. This design has a large growth area with relatively
uniform temperature distribution, and the potential as gas sensors. CNTs are expected to grow on
the hotplate surface. The second design (Fig. 3-1 C) has a serpentine shape. This design
introduces trenches between the micriheater (the red part) and the silicon dioxide secondary wall
(the blue lines) for suspended CNT growth. With the secondary wall grounded, this
configuration is also designed to study the local E-field distribution and the impact of the E-field
on the CNT alignment. The third design (Fig. 3-1 D) is further simplified into one straight line
microheater for studying temperature and CNT density distribution along the microheater. The
distribution information will facilitate the further microheater scaling. With a hot spot heater, the
minimization of heating elements offers more accurate local control of E-field, temperature and
growth rate. Thus, the position, quantity, length, direction, and properties of CNTs can be better
controlled. Moreover, smaller heating elements require less power, and lead to a higher CMOS-
CNT integration density.
Figure 3-1. A) Structural demonstration of mock-CMOS platinum microheater. B) Large
hotplate with a meander Pt microheater embedded. C) Serpentine microheater design. D) Straight line microheater design.
B) C) D)
A)
34
3.2 Device Fabrication
Based on the above microheater designs, a process flow is proposed to fabricate the
devices. Fig. 3-2 shows the cross sectional view of the process flow. The fabrication process
starts from the deposition of a 0.5 μm thick SiO2 (Fig. 3-2 A). A Cr/Pt/Cr heater film is then
sputtered and patterned using a lift-off process, in which 200 nm thick Pt is the heater and 30 nm
thick Cr is the adhesive layer for Pt (Fig. 3-2 B, Cr layer not shown). Next, another 0.5 μm top
SiO2 layer is deposited and patterned. Depending on the mask design, the top SiO2 layer can be
left there to form an oxide/Pt/oxide sandwich structure (Fig. 3-2 C), or the SiO2 over the
microheater can be etched away to form a Pt/oxide bimorph structure (Fig. 3-2 C’), in which case
direct contact between Pt electrodes and CNTs will be formed during the synthesis process. Then,
using the patterned SiO2 layer (Fig. 3-2 D) or the Pt heater itself (Fig. 3-2 D’) as the etching
mask, an anisotropic deep-reactive-ion etching (DRIE) of silicon is performed to create trenches
around the heater. Finally, isotropic silicon dry etching is performed to undercut the silicon
underneath to release the microheater hotplates (or bridges) suspended over the cavity
(Fig. 3-2 E and E’). The localized heating is realized by using DRIE silicon dry etching process
to form a cavity to obtain a good thermal isolation. In the next chapter, we will see that the
process proposed for mock-CMOS microheater fabrication is fully transferable for releasing
microheaters integrated in CMOS substrates.
Three types of microheaters that were introduced in Section 3.1 have been fabricated and
characterized. Fig. 3-3 shows the SEM pictures of fabricated microheaters. The first design
(Fig. 3-3 A) is an 87 × 87 μm2 micro-hotplate with a symmetric meander Pt heater embedded.
The second one (Fig. 3-3 B) is the serpentine microheater design. The dark region is the etch-
through openings that are patterned during the step shown in Fig. 3-2 C. It is corresponding to
35
Figure 3-2. Cross-sectional view of the proposed process flow. A) PECVD SiO2 deposition. B)
Pt sputtering and lift-off to form heater and pads. C) and C’) Top PECVD SiO2 deposition and patterning. D) and D’) Anisotropic Si dry etch. E) and E’) Isotropic Si dry etch and heater release.
the trench as shown in Fig. 3-3 D. The white region surrounding the center Pt heater in the SEM
picture is bare silicon oxide with no silicon underneath, as shown in Fig. 3-3 D. Therefore, the
white region outlines the size of micro-cavity below the microheater. Its bright color is an artifact
due to the charging effect of the sample during SEM imaging. Due to its serpentine shape, some
bare silicon oxide was left between etch openings as the extra mechanical supports. This is found
to be necessary. A test structure with similar serpentine shape but no extra mechanical supports
sagged down obviously after the release. Although it still can function as a microheater, one
could imagine the mismatch in thermal coefficient of expansion between CNT and Pt heaters and
the freedom of microstructure deformation might increase the probability of detachment of the
A) B)
D) D’)
C) C’)
E) E’)
Pt Silicon SiO2
36
CNTs from the devices. The third design (Fig. 3-3 C) is a straight-line Pt microheater. It is 5 μm
wide and 120 μm long. The top SiO2 layer is etched during the step shown in Fig. 3-2 C’, and
thus the Pt is exposed to facilitate the electrical contact with CNTs. The exposed Pt is 80 μm
long, defined as the effective length of the microheater L1. Similarly, the white bare silicon
region represents the cavity boundary, and the effective length is labeled as L2. In this design,
two extra parallel Pt lines are placed on the left and right of the heater as labeled as “A” and “C”,
respectively. They are used as the second walls for CNT landing during the growth, and as the
second electrodes for extracting electrical signals after CNT growth. The trenches are 3 μm (left)
and 6 μm (right) wide, respectively. For each microheater, there are two big pads for applying
electrical voltage to generate heating. Another pair of electrodes is designed to apply proper
E-field if necessary (as shown in Fig. 3-3, labeled as “E-field electrode”).
Figure 3-3. SEM pictures of fabricated microheaters. A) Design-1: Pt heater embedded in a
micro-hotplate, B) Design-2: Pt heater in a curved shape, and C) Design-3: Pt heater with two straight lines in parallel, labeled as “A”, “B” and “C”, respectively. L1 and L2 represent effective length of heater (80 μm) and length of cavity (about 95 μm), respectively. D) Cross sectional view of the device (line MM’ in part B).
D)
Bare Si Trench
A)
Pad
Pad
C)
L1
A
L2
B C
Pad
Pad
E-field electrode
E-field electrode
B)
M
M’
Pad
Pad E-field electrode
E-field electrode
Extra supports
37
3.3 Microheater Characterization
After device fabrication, the microheaters are characterized before performing growth
experiments. The characterization is designed to measure the following properties. First, for the
purpose of successful SWNT synthesis, the maximum temperature that can be reached by
resistive heating and the reliability of the microheaters under such high temperature conditions
are two key factors. Then, for the purpose of integrating SWNTs on CMOS chips, the local
temperature distribution is a major concern, i.e. a sharp temperature gradient is desired so that
temperature can decrease rapidly from the heater center toward the substrate.
3.3.1 Maximum Temperature Estimation
The mechanical robustness at high temperature was first tested by baking microheaters in
oven at 900°C for 20 minutes. Both the oxide/Pt/oxide and Pt/oxide bimorph structure were
expected to undergo strain incompatibility primarily due to the thermal expansion mismatch of
different materials. Although slight sag was observed, all the microheaters were survived the
high temperature treatments with no rupture occurred.
Then, the working temperature of microheaters was evaluated using micro-hotplate design.
It is reported that platinum has the optimum thermo-resistive characteristics and Pt resistance
thermometers have served as the international standard for temperature measurements
between -259.34°C and 630.75°C [101]. In a linear approximation, the relation between
resistance and temperature is given as follows:
0 (1 )TR R Tα= + ⋅∆ (3-1)
in which 0R is the initial resistance, TR is the resistance dependent on temperature, α is the
temperature coefficient of resistance (TCR) and T∆ is the temperature increment. The de facto
industrial standard value of TCR is 0.00385 /°C, but thin film platinum exhibits a coefficient that
38
tends to decrease with the thickness. The value of TCR used for our 200 nm thick Pt microheater
is about 0.00373/°C, which is obtained from Clayton’s report [101]. The microheater was
electrically connected using silver epoxy and then characterized. The experimental current-
voltage relation was plotted in Fig. 3-4 A. The resistance under each power supply can be
calculated, and the corresponding temperature can be estimated based on the change of the Pt
heater resistance and the TCR of Pt. The resistance of the micro-hotplate was about 46 Ω at room
temperature. It increased to 212.5 Ω when the applied current was increased to 14 mA. Therefore,
the maximum temperature was estimated to be above 900°C based on equation 3-1 (Fig. 3-4 B).
Figure 3-4. A) I-V characterization of microheater. B) Temperature estimated based on
resistance change.
For the temperature obtained by this method, it should be noted that the calculated
temperature is only an approximation and subject to following simplifications. First, the
resistance measurement is simplified. The resistance measured is actually the sum of the contact
resistance and the heater’s resistance: Total contact resistorR R R= + . Further, the overall heater’s
resistance resistorR should consider both the 200 nm Pt layer and the 30 nm Cr adhesive layers. At
20°C, the electrical resistivity of Cr is 125 nΩ•m, while the electrical resistivity of Pt is
105 nΩ•m [102, 103]. Second, under Joule heating, the microheater actually exhibits complex
0.0 0.5 1.0 1.5 2.0 2.5 3.002468
101214
Curre
nt (m
A)
Voltage (V)0.0 0.5 1.0 1.5 2.0 2.5 3.00
200
400
600
800
1000
Te
mpe
ratu
re (C
)
Voltage(V)
A) B)
39
temperature distribution along the heater rather than one uniform temperature. Thus the
calculated temperature is an approximation of the average. As a result of these simplifications,
what we obtained is a rough range that indicates high enough temperature for growth rather than
a specific temperature. Thermal characterization accurate to degree centigrade is desirable but
not the primary objective of this thesis.
3.3.2 Heating Experiment
During the I-V characterization presented above, red glowing of the microheaters under
different voltages was clearly observed under an optical microscope, as shown in Fig. 3-5. This
red glowing can be switched between “on” and “off” instantaneously by controlling the power
supply, indicating much shorter response time compared to traditional CVD processes. The
localized microheating combined with this fast response greatly reduces the total power
consumption and thermal budget of post-CMOS processing. In addition, we need an indicator to
determine when the microheater has reached the required high temperature so that we can stop
increasing the power supply and start the CNT synthesis process. Due to different structure
designs and/or fabrication variations between devices, individual microheaters require different
electrical powers to reach the same temperature. Thus neither current nor voltage is a good
indicative parameter unless each microheater is characterized under the growth condition and the
temperature-power relation is established for each device before the real growth. Instead, the
incandescence, the emission of visible light from a hot body due to its temperature, of platinum
microheaters observed as red glowing indicates that the heater reaches the required high
temperature. Indeed, we start flowing in synthesis gases once the red glowing is observed in our
practice.
40
Figure 3-5. Microscopic images under applied voltages of A) 2.28 V, B) 2.62 V, and C) 3.00 V,
respectively.
3.3.3 High Temperature Reliability
After assessing the maximum temperature, the reliability of the microheaters at high
temperature was then evaluated. Although bulk platinum has a high melting point
(1768°C [103]) and it is extraordinarily stable at high temperatures, the degradation of platinum
thin film at high temperature has been reported by several groups [104-107]. As shown in
Fig. 3-6 A, we observed a kink point in the curve at higher voltage, and a negative slope between
1.2 V to 1.4 V before the microheater was broken. To study the negative slope region, another
newly released platinum thin film microheater with the same design was tested. The voltage was
gradually increased from 0 to 1.5 V and then swept back to 0 V. The sweepings were repeated
from 0 to 1.5 V and from 0 to 1.8 V. As shown in Fig. 3-6 B, the negative slope only occurred
during the first 0-1.5 V voltage sweeping. After that, the electrical characteristics changed and
became repeatable as a result of a permanent change in the platinum resistance.
Briand et al. reported that the resistivity of the Pt/ Ta thin film increased after a heat
treatment of 95 minutes at 830°C, as a function of the film thickness (Fig. 3-6 D) [108].
Re-plotting the electrical characteristics we obtained (Fig. 3-6 B) as Resistance Vs. Power in
Fig. 3-6 C, we found that the resistance increased from 134 Ω to 185 Ω after the voltage
sweeping. This resistance increase is explained as the result of self-heating treatment through
C) B) A)
41
resistive Joule heating, with points A’ and B’ corresponding to points A and B in Briand’s paper,
respectively. There might be a critical point that is associated with this high temperature
degradation. This critical temperature might be different for Pt thin films with different
configurations such as thickness, structure, type of adhesion layer, etc. Firebaugh et al. reported
that the resistance of their 100-nm Pt/10-nm Ti film was well behaved up to ~900°C beyond
Figure 3-6. A) Embedded straight line platinum microheater I-V characteristics. Negative slope
was observed between 1.2 V to 1.4 V. B) Heater characteristics under repeated sweepings. C) Microheater resistance under repeated sweepings. Inset: resistance characterization of the 100-nm Pt/10-nm Ti film, reported in literature [104]. C) Sheet resistance for 205-nm Pt/15-nm Ta and 145-nm Pt/15-nm Ta thin film, (1) before and (2) after 830°C heat treatment, as reported in literature [108].
0.0 0.5 1.0 1.5 2.0 2.50
2
4
6
Curr
ent (
mA)
Voltage (V)0.0 0.5 1.0 1.5 2.00
2
4
6
0 - 1.5V 1.5 - 0V 0 - 1.5V 0 - 1.8V
Curr
ent (
mA)
Voltage (V)B) A)
C)
A
B
0 2 4 6 8100
150
200
250
300
Res
ista
nce
(Ohm
)
Power (mW)
0 - 1.5V 1.5 - 0V
A’
B’
D)
42
which holes started to form in the film and resistance increased rapidly [104] (Fig. 3-6, inset).
For our device, the critical temperature was believed to be reached at the center of the
microheater when the power supply was increased to around 6 mW, and the rest part of the
microheater later underwent the similar temperature treatment when the input power was
continuously increased to about 8 mW.
Several factors attribute to the degradation of platinum thin film, including interdiffusion
and reaction between the Pt layer and the adhesive layer, stress, and platinum silicide
formation [107], but the agglomeration of continuous thin films into islands of material is
believed to be the dominant mechanism [104]. Agglomeration involves the nucleation and
growth of holes in the film, and it is driven by the high surface-to-volume ratio of the thin films.
The surface diffusivity is dependent on the temperature, and the diffusion of metal atoms on
surface tends to reduce the surface-to-volume ratio through capillarity [109]. The sizes for the
initial holes must be larger than the thickness-dependent thermodynamic critical radius, and the
holes will then grow under the surface-diffusion-driven capillarity [110]. As reported by
Firebaugh et al.[104], holes started to form in the platinum thin film at around 900°C, and
gradually increased in size with time, resulting in the discontinuity (Fig. 3-7). Note that the hole
growth rate is slow and the film life-time is sufficient long, compared with the time required for
CNT growth. To avoid agglomeration, thin film thickness greater than 1 μm was
recommended [104]. For our 200-nm platinum microheaters, we noticed that although the film is
not sufficiently thick, all the microheaters are capable of withstanding a sufficient amount of
time required for CNT growth process.
43
Figure 3-7. The formation and growth of holes in the 100-nm Pt/10-nm Ti thin film. A) After 0
hour at 900°C. B) After 2 hours at 900°C. C) After 6 hours at 900°C. D) After 9 hours at 900°C. Reported in literature [104].
3.3.4 Local Temperature Distribution
Other than the maximum temperature and the heater reliability, the local temperature
distribution is also of vital importance. It was investigated using a QFI InfraScope. The thermal
image of the straight line microheater is shown in Fig. 3-8 A. Since the maximum working
temperature of this infrared imager is 400°C, only 0.6 V was applied to the microheater.
Fig. 3-8 D and Fig. 3-8 E show the temperature distributions along and transverse to the platinum
heater line, respectively. It is clearly shown that the temperature is near uniform at the region
±30 µm from the microheater center. This offers the optimal region for CNT growth. Meanwhile,
with the temperature as high as 400°C around the heater center, the temperature outside the
micro-cavity drops quickly to about 100°C. Note that the InfraScope stage was heated to 60°C to
facilitate accurate temperature measurement for this image. Therefore, the temperature
distribution is compatible with the post-CMOS processing even when the supply power must be
increased to provide the desired growth temperature of ~900°C. Accurately choosing the
B) A)
D) C)
44
spacing between CMOS circuits and microheaters, this localized microheating method can
integrate CNTs at a close proximity of the CMOS devices on the same chip. For design-1 and
design-2, the corners of the microheaters have slightly higher temperature due to the current
crowding effect, as evident from their thermal images (as shown in Fig. 3-8 A and Fig. 3-8 B).
Figure 3-8. Thermal imaging. A) Thermal image of Design-1 by applying 0.93 V dc voltage. B)
Thermal image of Design-2 by applying 1.2 V dc voltage. C) Thermal image of Design-3 by applying 0.6Vdc voltage. D) and E) Corresponding temperature distribution along and transverse to the microheater, indicating good thermal isolation. (The substrate temperature is 60°C).
C)
(e)
(d)
-60 -40 -20 0 20 40 60
100
200
300
400
Temperatu
re(C)
Disstance(um)
Distance (µm) - 60 - 40 - 20 0 20 40 60
Effective length of heater: L1
Length of cavity: L2
Tem
pera
ture
(°C
)
400 300 200 100
-28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24
100
200
300
400
Y Axis Title
X Axis Title
Distance (µm)
Tem
pera
ture
(°C
)
400 300 200 100
-28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24
Width of heater
D)
E)
B)
Temperature (°C) 52.9 152.1 251.3 350.5
A)
0 133.6 267.2 400.8 Temperature (°C)
45
3.4 Room Temperature Carbon Nanotube Synthesis
After device fabrication and characterization, the samples were coated with
alumina-supported iron catalyst by drop-drying. Two contact pads were connected to a
voltage-controlled power supply by clamps. And then the sample was placed into a quartz tube.
After 5 minutes argon purging, the microheater was heated up to the state that red glowing could
be observed. For example, Design-2 needs a supply voltage of 3-3.5 V. Then, a mix of
1000-sccm CH4, 20-sccm C2H4 and 500-sccm H2 was flowed into the quartz tube for CNT
growth. After a 15 minutes growth, SWNTs and MWNTs with diameters ranging from 1-10 nm
were successfully synthesized on all the three types of suspended microstructures.
Fig. 3-9 shows a dense film of CNTs grown on the micro-hotplate surface. Some
interesting coiled nanostructures, as shown in the insets in Fig. 3-9, are observed on many
samples. The orientations of these CNTs are random since there is no guiding electrical field.
Figure 3-9. Dense film of CNTs over micro-hotplate surface (Design-1). Insets: coiled
nanostructures observed in the growth.
On the other hand, for the other two designs with trenches and secondary landing walls, the
supplied voltage simultaneously introduces an E- field (about 0.1 ~ 1.0 V/μm) between the
microheater and a nearby ground electrode/oxide wall. As a result, most of the suspended CNTs
grown on these two types of microheaters exhibit a significant alignment along the E-field
100 nm
100 nm Coiled N t t
100 nm
46
perpendicular to the cold wall, as shown in Fig. 3-10. As demonstrated in our experiments, with
proper designed microheaters and trench widths, the desired temperature profile and E-field
distribution can be obtained by the same power supply. The extra pair of back-up electrodes
designed to enhance E-field was not used, and thus can be removed to simplify the design in the
future. Although the microheater corners have higher temperature and denser E-field, comparing
the SEM images (shown in Fig. 3-10 A and Fig. 3-10 B) reveals that there is no significant
difference between the growth around the corners and the rest of the microheater. When the
microheater is further simplified into one straight line (Design-3), we find that the alignment is
further improved as shown in Fig. 3-10 C and the CNT growth is uniform along the length of the
Figure 3-10. Localized synthesis of CNTs suspended across the trench, showing good CNT
alignment. A) and B) Zoom-in SEM of CNTs grown on Design-2. C) Zoom-in SEM of CNTs grown on Design-3 (from second batch, with no Cr on top). Insets: SEMs of overall microheaters.
1µm Cold wall of SiO2 B) 1µm
Cold wall of SiO2
100 nm
Cold wall of Parallel Pt
Highly aligned SWNTs
C)
A)
E-field electrode
E-field electrode
E-field electrode
E-field electrode
47
entire microheater except on the small regions next to the anchors. These results are in good
agreement with the measured temperature distribution. Hence, the microheater geometry with
either a relatively larger hotplate or a small hot-spot can be customized to control the
temperature distribution for regulating the CNT growth for various applications.
3.5 Characterization of Carbon Nanotubes
In the third design, there are three parallel Pt lines (as shown in Fig. 3-11 inset, labeled as
“A”, “B” and “C”, the one in the center is the microheater). The top SiO2 coverage has been
etched away for facilitating direct electrical contact between CNTs and the Pt lines. The Pt lines
are initially separated from each other. Once two of the Pt lines are connected by CNTs, the
resistance between them can be measured to characterize the electrical properties of the
synthesized CNTs. However, although tens or hundreds of CNTs are observed connecting the Pt
lines, the measurement shows infinite resistance, which indicates very poor electrical contacts.
After some investigation of the involved materials including palladium, molybdenum, platinum,
and chromium, it turns out that the adhesive chromium layer is easily passivated by oxygen,
forming a thin oxide surface layer, thereby increasing the contact resistance to unusable levels.
In the second batch, the same process flow was followed but the top Cr layer was
removed. The microheater consists of a structure of 200-nm Pt/30-nm Cr/0.5-μm SiO2. The SEM
image shows the similar growth result in term of the growth density, nanotube diameters, etc.,
but the I-V characterization shows that the contact resistance has been reduced significantly:
from infinite to the kΩ range, indicating good ohmic contacts between the Pt and CNTs. The
characterization between pads A and B, A and C, B and C are measured on the same sample
shown in Fig. 3-10 C (A, B and C are as labeled in Fig. 3-11 inset). The measured resistances are
shown in Fig. 3-11. The resistance RB-C between the pads C and B (6 μm wide trench) is about
85 kΩ, while the resistance RB-A between the pads A and B (3 μm wide trench) is about 12 kΩ
48
due to the denser and shorter CNT connection. Since CNTs cannot grow from the cold Pt landing
walls, there is no direct connection between lines C and A. The measured resistance RA-C
between the pads C and A is about 100 kΩ, close to the sum of the two series-connected resistors
RB-C and RB-A. Thus, we demonstrated that, by selecting a proper material as the electrodes,
suspended SWNT devices can be fabricated using this approach, and the electrical properties can
be measured without any post-growth metallization processing.
Figure 3-11. I-V characteristics of SWNTs contacted by Pt electrode. It was measured on the
same device shown in Fig. 3-10 C. Inset: a SEM image of the overall microheater.
As mentioned in Section 2.1, CNTs growth can follow two growth mechanisms: tip-
growth and base-growth. Thus two types of contacts can be consequently formed when CNTs
reach the secondary Pt lines. Jiang et al. proposed that in the tip-growth model, once the hot
catalyst particles reach the cold secondary structure, the growth process stops immediately due to
the temperature drop (Fig. 3-12 A left); in the base-growth model, since the catalyst particles
stay at the high temperature microheater surface, the growth process will continue after the CNT
landing and result in a line contact on the secondary electrode (Fig. 3-12 A right) [111]. The line
-1.0 -0.5 0.0 0.5 1.0
-80
-40
0
40
80
Curre
nt (u
A)
Voltage (V)
Resistance between pad A and C Resistance between pad B and C Resistance between pad A and B
A B C
49
contact was clearly observed from our growth results (Fig. 3-12 C), but the tip contacts were
unclear since the secondary electrode surface was covered by the catalyst layer (Fig. 3-12 B).
Franklin et al. also reported that it was the overlapping of the CNT with the Mo electrode surface
that forms the electrical contact [77]. However, so far there have been no conclusive
experimental results on which growth model would result in better contacts. Our fore-mentioned
good ohmic contacts and low resistances are the results of numerous parallel CNTs, probably
including both tip contacts and line contacts. Future investigation may try to grow one single
CNT on each device in the batch mode, and establish the relation of grow model and contact
resistance.
Figure 3-12. A) Demonstration of the types of nanotube nano-to-micro contacts. The left one
shows the tip-growth mechanism, and right one is the base-growth mechanism [111]. B) An SEM image of the possible tip contacts. C) An SEM image of the possible line contact.
100 nm B)
Secondary Pt wall
100 nm Secondary Pt wall C)
A)
Tip-growth Base-growth
50
Recall in the cases where suspended CNTs were directly synthesized between two Mo
electrodes without any post-growth metal clamps, the resistance tended to increase over time,
which was attributed to the slight oxidation of the Mo in air [112]. I-V characterization of CNTs
was performed right after the synthesis (Fig. 3-11) and the characterization was done once again
one year later for the same device. The two measured resistances were shown in Fig. 3-13. The
resistance under ± 1.0 volt was almost the same, but some nonlinearity under low input power
was occurred. It might be due to the change of the contact condition (the oxidization of the
catalyst/Pt electrode surface), or due to the property change of the CNTs themselves (absorption
of the gas molecular and mechanical deformation).
Figure 3-13. I-V characteristics of CNTs contacted by Pt electrode. One measurement was
obtained right after growth, and the other measurement was performed one year later.
Following the resistance characterization, the sensing abilities of the suspended nanotube
device were investigated as gas and thermal sensors. As a gas sensor, the resistance tended to
decrease when exposed to oxygen and increase during pure nitrogen purging. However, no
-1.0 -0.5 0.0 0.5 1.0
-80
-40
0
40
80
I (uA
)
Voltage (V)
R obtained one year later R obtained after growth
51
significant changes can be identified as the outputs seem to be dominated by the noises, as
shown in Fig. 3-14.
Figure 3-14. Response curve to oxygen vs. time. Bias voltage is 1 V. A) 1-200s: 1000-sccm N2.
200-2000s: 500-sccm N2 and 500-sccm O2. B) 0-400s: 1000-sccm N2. 400-4000s: 200-sccm N2 and 800-sccm O2.
Figure 3-15. Measured resistance vs. temperature relationship.
As a thermal sensor, we repeatedly observed that the resistance of CNTs decreased with
temperature, which coincides with the literature [113] (i.e. negative TCR). Fig. 3-15 shows the
0 500 1000 1500 2000
25
26
27
28
I (uA
)
Time (s)0 1000 2000 3000 4000
23.5
24.024.5
25.0
25.526.0
26.5
I (uA
)Time (s)B) A)
40 50 60 70 80 90
42
43
44
45
46
47
Resi
stan
ce (K
ohm
)
Temperature (° C)
52
measured temperature-resistance relationship. The temperature coefficient of resistance is about
– 0.15 % per degree Celsius. The value of TCR reported in the literatures ranges from – 0.1% to
– 0.66% per degree Celsius [56, 114-116], mainly depending on the type of CNTs and the
fabrication process.
3.6 Summary
In this chapter, room-temperature localized CVD synthesis of CNTs based on three
microheaters designs has been successfully demonstrated. Three types of platinum microheaters
have been designed, fabricated and tested, which successfully demonstrated the targeted
mechanical robustness and temperature profile. Local temperature distribution has been
investigated using a high-resolution thermal imager and later confirmed by the CNT growth
density distribution. The synthesized CNTs showed excellent alignment and good ohmic contacts
with platinum electrodes. The suspended CNT device has been demonstrated as a thermal sensor,
with the TCR value in accordance with other literature reports. Future work of this part of the
project will focus mainly on investigating the growth mechanism and the contact resistance,
improving its sensing abilities, and exploring other applications.
53
CHAPTER 4 THE INTEGRATION OF CARBON NANOTUBES ON CMOS SUBSTRATE
In the previous chapter, localized CNT synthesis on mock-CMOS substrates has been
demonstrated. We have proved that, based on the voltage-controlled localized heating, suspended
on-chip microheaters can provide both uniform high temperature for high-quality CNT growth
and good thermal isolation for CMOS compatibility requirement. Repeatable and well-aligned
CNT growth can be realized, and the simple straight-line microheater is promising for further
scaling down to a hot-spot. However, a number of vital questions have yet to be settled. First,
platinum is still incompatible with other standard CMOS materials and thus unlikely to be used
in a post-CMOS process in a commercial CMOS foundry. Second, the process flow proposed in
Section 3.2 requires two lithography steps for patterning microheaters and release-openings,
which is still too complicated for post-CMOS processes. Third, the integration presented in the
previous chapter did not involve the interconnection of CNTs with CMOS circuits in the
monolithic integration.
To address these issues, we propose a simple and scalable CMOS-CNT integration
approach in this chapter. CNTs are selectively synthesized on polysilicon microheaters
embedded aside the CMOS circuits using localized heating and maskless post-CMOS surface
micromachining techniques. There is no need of any photo-masks, shadow masks or metal
deposition to achieve the localized synthesis and the CNT-polysilicon electrical contact.
Successful monolithic CMOS-CNT integration has been demonstrated. And it is verified that the
electrical characteristics of the neighboring NMOS and PMOS transistors are unchanged after
CNT growth.
54
4.1 Integration Principles and Device Design
As illustrated in Fig. 4-1, the basic idea of the monolithic integration approach is to use
maskless post-CMOS MEMS processing to form micro-cavities for thermal isolation and use the
gate polysilicon to form the heaters for localized heating as well as the nanotube-to-CMOS
interconnect. The microheaters, made of the gate polysilicon, are deposited and patterned along
with the gates of the transistors in the standard CMOS foundry processes. Except the shape and
dimensions, the polysilicon microheaters are equivalent to the transistor gate, and thus they share
exactly the same subsequent processes, i.e. the vias, interconnects, passivation layers and I/O
pads. One of the top metal layers (i.e. the metal-3 layer as shown in Fig. 4-1 B) is also patterned
during the CMOS fabrication. It is used as etching mask in the following post-CMOS
microfabrication process for creating the micro-cavities. Finally, the polysilicon microheaters are
exposed and suspended in a micro-cavity on a CMOS substrate, while the circuits are covered
under the metallization and passivation layers, as illustrated in Fig. 4-1 B. Unlike the traditional
thermal CVD synthesis that heats up the whole chamber to above 800°C, the device with
embedded microheaters works like a miniaturized CVD array: the CVD chamber is kept at room
temperature all the time, with only the microheaters activated to provide the local high
temperature for CNT growth (Fig. 4-1 A, the red part represents the hot microheater). The top
view of a microheater design is shown in Fig. 4-1 C. The configuration is similar to the platinum
microheaters. There are two polysilicon bridges: one as the microheater for generating high
temperature to initiate CNT growth and the other for CNT landing. With the cold wall grounded,
an E-field perpendicular to the surface of the two bridges will be induced during CNT growth.
Activated by localized heating, the nanotubes will start to grow from the hotspot (i.e. the center
of the microheater) and will eventually reach the secondary cold bridge under the influence of
local E-field. Since both the microheater bridge and the landing bridge are made of gate
55
polysilicon layer and they have been interconnected with the metal layers in CMOS foundry
process, the as-grown CNTs can be electrically connected to CMOS circuitry on the same chip
without any post-growth clamping or connection steps.
Figure 4-1. A) The 3-D schematic showing the concept of the CMOS integrated CNTs. The
CVD chamber is kept at room temperature all the time. The red part represents the hot microheater that has been activated for high temperature nanotube synthesis. B) Cross-sectional view of the device. C) The schematic 3-D microheater showing the local synthesis from the hotspot and self-assembly on the cold landing wall under the local electric field.
As discussed in Section 3.1, the microheater design is of vital importance. The gate
polysilicon layer is thin and its thickness is determined by the foundry CMOS processes. For the
AMI 0.5 μm CMOS process [117] used in this work, the polysilicon thickness is 0.35 μm. Since
the serpentine design showed no meaningful advantages of the corner effect but required extra
E
Hotspot for growth Cold wall
for landing
CNTs I V
C)
A)
CMOS chip
Al
Oxid P+ P+ N N+ P N+
Gate B)
56
mechanical supports in the previous mock-CMOS synthesis experiments, a line shape
microheater is adopted for its superior mechanical robustness and simple design. A typical heater
design is shown in Fig. 4-2 A, which is basically a polysilicon resistor. Since the temperature has
to reach at least as high as 800°C for SWNT growth and to drop quickly to avoid deteriorating
the surrounding CMOS circuits, the thermal isolation, thermal stresses and structural stiffness
must be well balanced during microheater design. As we all know, short resistors tend to
dissipate heat faster so that reaching high temperature requires more power (because the center
of the resistor is closer to the anchors), while long resistors tends to have mechanical stiffness
issues. In addition, the current density limitation of the polysilicon resistors and the limitation of
the release process do not allow us to design microheaters with too narrow width. As a result of
considering all these factors, the heating unit first investigated is a 3 μm long and 3 μm wide
polysilicon resistor.
Electrothermal modeling in a multi-physics finite element method tool, COMSOL [118],
has been used to simulate and optimize the microheater design. The simulation results are shown
in Fig. 4-2 B and Fig. 4-2 C, where a typical polysilicon sheet resistance of 30 Ω/ and other
material properties are chosen according to the employed foundry process [117] (see Table 4-1).
For the simulation, the convection and radiation heating losses are neglected as the heating area
is small. The substrate bottom surface is assumed to stay at room temperature. Fig. 4-2 B shows
the temperature distribution when a 2.5 V activation voltage is applied to the heater. It shows a
good agreement with the post-growth surface pattern (Fig. 4-2, inset SEM image), which is
believed to reflect the temperature distribution during the growth. Fig. 4-2 C plots the
temperature distribution along the microheater. It shows an ideal condition for CMOS-CNT
57
integration: a very small, localized high temperature region for CNT growth and a sharp
temperature decrease toward the substrate.
Figure 4-2. A) A typical heater design with stripe-shaped resistor. B) Simulated temperature
distribution along the surface of the microheater at an applied voltage of 2.5V through the pads. The area of polysilicon microheater is 3μm×3μm, and a thickness of 0.35μm is chosen according to the CMOS foundry process. Inset: an SEM image of a microheater after CNT growth. C) The line plot of the temperature along the heater (line AA’ in part B).
Based on this 3 × 3 μm2 heating unit, a series of heater design variations have been
investigated. First, to exploit the geometry limitations (mainly the mechanical robustness and
electrothermal properties), six line-shape microheaters are designed with dimension variations.
The width ranges from 1.2 μm to 6 μm, and the length ranges from 1.2 μm to 40 μm. Second,
two types of the secondary wall are designed: one is a bridge parallel to the microheater for
A)
Polysilicon heater
-20 0 20 40 Distance to microheater center (μm)
-40
Tem
pera
ture
(°C
)
600
0
400
800
1000 C)
A A’
200
B) 900
300
100
Boundary: Temperature
500
700 A’
10 μm 10 μm
A
58
uniform E-field formation (Fig. 4-3 A), and the other is a sharp tip (or multiple tips) to form a
converged E-field (Fig. 4-3 B). The gap between the two polysilicon microstructures is typically
3-6 μm in order to obtain the proper electric field and facilitate the CNT landing. Third, opposing
sharp tips (Fig. 4-3 C) are also designed to facilitate the CNT bridge formation since CNTs tend
to attach to the nearest support boundary [119]. Finally, instead of grounding the secondary wall,
some designs have five configurable inputs. As illustrated in Fig. 4-3 A, four pads can input
different voltages to tune the electric field, and the fifth input (not shown) is connect to the
substrate as a global back gate for studying the electrical gating effect.
Figure 4-3. Schematic layouts showing A) a 3 μm × 10 μm microheater with a paralleled bridge
as the secondary wall and four configurable input pads, B) a 6 μm × 20 μm microheater with multiple tips as landing walls, and C) a microheater with opposing sharp tips .
The final CMOS chip includes test circuits and 13 embedded microheaters. The schematic
layout is shown in Fig. 4-4. Microheaters are placed around the center and they are independent
from each other. Four test circuits are placed close to the microheater with spacings ranging from
36 μm to 60 μm. The spacing is chosen based on the temperature distribution investigation
shown in Fig. 3-8. The sizes of the NMOS and PMOS transistors which are the subject of our
investigation are Wn/Ln = 3.6 μm/0.6 μm and Wp/Lp = 7.2 μm/0.6 μm, respectively. The big
square with green color in Fig. 4-4 B is the metal-3 layer. It is patterned as etching mask that
covers all the circuit area beneath but has 13 etching openings, with one opening for each
B) A) C)
heater
Pad1: 7V
Pad2: 4V
Pad3: 3V
Pad4: 0V
59
individual microheater. The etching opening as shown in Fig. 4-4 C determines the size of the
micro-cavity. The micro-cavities will be formed when the top silicon dioxide and bottom silicon
are all etched away during the post-CMOS MEMS processes, leaving only the suspended
microheaters, as shown in Fig. 4-1 A and Fig. 4-1 B.
However, there is a selective etching issue. In the cases where the microheaters are made
of platinum, specific etch chemistry can be used to etch away silicon dioxide or silicon
completely with little etching to platinum. Thus, etching protection for the heaters is not
necessary, and the platinum microheaters themselves can be used as masks once the heaters’
shapes have been patterned. When switching the heater material to polysilicon, this is no longer
the case. Both the dioxide etchant (dry etch) and silicon etchant will etch polysilicon. Recall that
the polysilicon thickness is only 0.35 μm. Thus, etching sequence needs to be carefully designed
and etching protection is essential. In our design, the metal-1 layer above the microheater is
patterned with the same shape as the microheater but with a slightly greater width, as shown in
Fig. 4-4 D. This patterned metal-1 layer will protect the microheaters during the first few steps
Figure 4-4. A) and B) Schematic layouts of the chip, including test circuits and 13 embedded
microheaters. The spacings between the microheaters and circuits vary from 36 μm to 60 μm. C) and D) Close-up views of a microheater with metal-3 as etching opening mask and metal-1 as etching protection.
B) A)
C)
D)
60
when the etchants can react with polysilicon, and then it will be removed using polysilicon-safe
etching recipes. Details will be presented in the device fabrication section.
4.2 Device Fabrication and Characterization
After the layout design, the CMOS chips are fabricated through MOSIS using the
commercial AMI 0.5 μm 3-metal CMOS process [117]. The gate oxide thickness is 13.5 nm. The
estimated layer thicknesses and other parameters are listed in Table 4-1. Several parameters have
been used in the modeling in Section 4.1. In addition, the thickness of each layer is used to
estimate the etching time in the post-CMOS fabrication processes; the current density limits have
been taken into consideration when designing the metallization.
Table 2-1. MOSIS AMI C5 Technology Structure Min Typ Max Units
N+ Poly Sheet Res 23 30 37 Ohms/sq
CMP M3 Thickness 7000 7700 8400 Å
CMP M3 to M2 Dielectric 10000 11000 12000 Å
CMP M2 Thickness 5000 5700 6400 Å
CMP M2 to M1 Dielectric 10000 11000 12000 Å
CMP M1 Thickness 5700 6400 7100 Å
Poly Thickness 3000 3500 4000 Å
Field Ox Under Poly 3500 4000 4500 Å
Via allowed current density 1.6 (85°C); 0.6 (125°C) mA/cnt
Metal allowed current density per width 2.2 (85°C); 0.85 (125°C) mA/μm Fig. 4-5 A shows the schematic cross-sectional view of the CMOS chip after the foundry
processes but before any post-CMOS MEMS fabrication. The metal-1 and metal-3 layers have
been patterned as described in the previous section. The corresponding optical microscope image
is shown in Fig. 4-6 A. The total chip area is 1.5 × 1.5 mm2. Due to this small size, individual
chips are mounted on top of a four inch carrier wafer for easy handling and processing. The
61
center big golden square is the metal-3 layer. In addition to the 13 etching openings to expose the
microheaters, there are 6 extra opening windows in the center. These are dummy structures for
etching rate control. There are 32 outer pads for microheaters and 16 inner pads for circuits.
These pads, as well as the area uncovered by the metal-3, need to be covered with photoresist for
protection before any release processes.
Figure 4-5. Mastless post-CMOS MEMS fabrication process flow: A) CMOS chip from
foundry. B) SiO2 dry etch. C) Al etch. D) Anisotropic Si dry etch. E) Isotropic Si dry etch and heater release. F) SiO2 wet etch.
The maskless post-CMOS MEMS fabrication process flow that used to release the
polysilicon microheaters is shown in Fig. 4-5. It starts with the reactive ion etching (RIE) of
silicon dioxide (Fig. 4-5 B). The metal-3 layer of the CMOS substrate is used as etching mask to
protect the CMOS circuit area, and it also defines the cavity opening size. Within the cavity, the
anisotropic etching, which uses a mixture of CHF3 and O2 as the etch chemistry, is mainly in the
Poly-Si Silicon SiO2 C)
E)
Micro-cavity
F) Poly-Si heater
Poly-Si gate
B)
Al
A) P+ P+ N+ N N+ P
D)
62
vertical direction. As a result, when the reactive ions etch down and reach the metal-1 layer,
three steep trenches are formed but the oxide under the metal-1 is almost un-attacked, i.e., the
polysilicon microheaters are entirely wrapped in a thin dioxide layer. Next, the exposed
aluminum is etched by RIE (Fig. 4-5 C), using BCl3, Cl2 and Ar. At this point, the photoresist
should be removed since the pad protection is no longer needed in the following steps and
removing it after the release step may damage the suspended microstructures. Then an
anisotropic deep-reactive-ion etching (DRIE) of silicon is performed (Fig. 4-5 D) using SF6 and
C4F8 as the etching and passivation gases, respectively, to create a roughly 6 μm-deep trench
around the heater. Next, an isotropic DRIE silicon etching using only SF6 is performed to
undercut the silicon under the microheaters (Fig. 4-5 E), resulting in suspended microheaters in
micro-cavities. In these two steps of silicon etching, polysilicon will be quickly etched away if
exposed. The silicon dioxide will also be etched but at a much slower rate. As mentioned in
Section 4.1, the metal-1 is designed slightly wider than the polysilicon microheaters. The width
difference determines the thickness of the sidewall protective dioxide. The oxide sidewall must
withstand the etching during the two silicon etching steps so that the polysilicon microheaters
will remain unattacked. The final step is to etch away the thin dioxide protective layer
surrounding the microheaters using a 6:1 buffered oxide etchant (BOE) at room temperature for
approximately five minutes to expose the polysilicon for electrical contact with CNTs
(Fig. 4-5 F). This BOE wet etch has a very high etching selectivity between silicon and silicon
dioxide. Overall, since all the required etching masks have been patterned in the foundry
processes, the post-CMOS MEMS fabrication is simple and easy to control, requiring only RIE,
DRIE and BOE etching.
63
Optical microscope images of the CMOS chip before and after the post-CMOS processing
are shown in Fig. 4-6 A and Fig. 4-6 B, respectively. A closed-up optical image of one
microheater is shown in Fig. 4-6 C. The nearby circuit, although visible, is protected under
silicon dioxide layer. Only the microheater and cold wall within the micro-cavity are exposed.
To satisfy the spacing, the microstructures are rearranged such that the microheater is closest to
the circuits and the secondary wall is on the opposite side. The polysilicon heater is connected to
Figure 4-6. A) The CMOS chip photograph (1.5 × 1.5 mm2) after foundry process. B) The
CMOS chip photograph after post-CMOS process (before final DRIE step). C) Close-up optical image of one microheater and nearby circuit. CMOS circuit area, although visible, is protected under silicon dioxide layer. Only the microheater and cold wall within the micro-cavity are exposed to synthesis gases. Polysilicon heater and metal wire are connected by vias. D) and E) Close-up SEM images of two microheaters.
20 μm
20 μm
B)
CMOS circuits
Micro-cavity Poly-Si layer
Metal layer C) Vias
E) D)
10 μm
Microheaters
A) CMOS chip from foundry 1.5 mm
1.5
mm
64
the metal interconnect by a number of vias. The quantity of the vias is determined by two factors:
the current that is required for Joule heating and the maximum current that one single via can
withstand (see Table 4-1). SEM images of two microheaters are shown in Fig. 4-6 D and
Fig. 4-6 E, with the resistances of 97 Ω and 117 Ω, respectively. The design is simple and the
released microstructures are mechanically robust. All the 13 microheaters, including the sharp-
tip design and the 40 μm-long design, survived the post-CMOS processes. Five chips have been
fabricated with a yield of 100%, indicating the robustness of the maskless post-CMOS MEMS
processes.
Similar to the mock-CMOS samples, polysilicon microheaters were also characterized
before the CNT growth experiments. The measured current-voltage relation was plotted in
Fig. 4-7 A. However, extracting the temperature dependent resistivity from the I-V
characterization and then using the resistivity to estimate the temperature becomes difficult due
to the following reasons. First, grain boundaries in polysilicon exhibit charge carrier trapping and
contribute to the temperature dependent behavior [120]. Second, dopant concentrations have a
significant impact on the temperature dependent resistivity within polysilicon. For low to
moderate dopant levels (≤ 1018 cm-3), increased temperature offers higher thermal energy that
excites more dopant electrons to the conduction band [121], resulting in a negative TCR. Such
temperature dependent behavior is undesirable since it will cause eletrothermal instability at high
temperature. For heavily doped polysilicon (≥ 1019 cm-3), if neglecting the grain boundary
effects, the temperature dependent resistivity can be defined as:
1 ( )e hp e µ µρ= + (4-1)
in which ρ is the resistivity, p is the free electron concentration, e is the magnitude of an electron
charge, and μe and μh are the electron and hole mobility, respectively [122]. Since the majority of
65
the dopant electrons in heavily-doped silicon are already in the conduction band, the free
electrons that are thermally activated from the donor no longer dominate the resistivity. Instead,
the temperature dependent behavior is dominated by the carrier mobilities at high doping levels,
resulting in a positive TCR and a linearly increased resistance within the temperature range from
300 to 800K. Lattice and impurity scattering mobility, μL and μI respectively, are found to have
significant contributions to the charge carrier mobility at high temperature [122]. The mobility
terms can be expressed in the following forms:
aL
bI
TT
µ
µ
∝
∝
2.7 1.51.5 2
ab
− < < −< <
(4-2)
and the temperature dependent resistivity can be expressed by a general equation:
31 2 T αρ α α= + (4-3)
in which the parameters α1, α2 and α3 have to be extracted empirically. For our microheaters,
based on the polysilicon sheet resistance and the thickness, the resistivity ρ is estimated to be
1.05×10-5 ohm·m, and the impurity doping level is estimated to be above 1019 cm-3 using the
equation 4-1.
Although high doping level requirement has been satisfied and a positive TCR has been
confirmed from the resistance calculation (as plotted in Fig. 4-7 B), the electrical characteristics
of the microheaters were found to be unstable at temperature beyond the polysilicon
recrystallization temperature Tcr (at roughly 870 K [123]), and the linear increase in resistance no
longer exists. Mastrangelo et al. reported that the resistance of a heavily doped polysilicon
filament decreases when the bias beyond a kink point (Fig. 4-7 inset, point P) [124]. For the
microheater we investigated, the kink point P happens around at a bias voltage of 2 V (see
66
Fig. 4-7 A and Fig. 4-7 B). Possible mechanisms reported include current-induced resistance
decrease [125, 126], filamentation [127], and the polysilicon thermal breakdown [128, 129].
Figure 4-7. A) I-V characterization of a 6 μm × 20 μm microheater. B) Resistance extracted
from the I-V characterization. C) - F) Microscopic images of a microheater: C) before applying power, D) starting to glow at 2.20 V, E) showing bright glowing at 2.38 V, and F) burnt after applying 2.47 V. Inset: filament I-V characteristics showing the kink point [124].
Continuing to increase the bias voltage, a red glowing was first observed in the dark at
2.20 V (Fig. 4-7 D), and it quickly became much brighter at 2.38 V. The heater was burnt in the
center under a bias voltage of 2.47 V, as evident from the comparison between Fig. 4-7 C and
Fig. 4-7 F. As previously discussed, the extraction of temperature above the polysilicon
recrystallization temperature is quite difficult due to its unstable electrical characteristics. Again,
the incandescence of the microheater becomes a good indication of high temperature.
Ehmann et al. carefully calibrated a microheater, which is also made of n-doped CMOS gate
polysilicon, and estimated that the average heater temperature was about 1200 K when
0.0 0.5 1.0 1.5 2.0 2.50
2
4
6
8
10
Curr
ent (
mA)
Voltage (V)0.0 0.5 1.0 1.5 2.0 2.5
120
140160
180
200220
240
Resi
stan
ce (O
hm)
Voltage (V)
C) D)
A) B)
P P
E) F)
67
incandescence was observed in the dark [130]. In addition, Englander et al., who first locally
synthesized CNTs on suspended polysilicon MEMS structures, reported that based on their
growth results, the barely glowing condition offered right temperature (850°C to 1000°C) for
maximum growth (prior-glowing was too cold while bright glowing was too hot) [96].
Therefore, the microheaters we designed and fabricated are capable of providing the high
temperature required for CNT growth, and it can withstand a sufficient amount of time under
barely glowing state. The local temperature distribution is not characterized. Instead, the
performance of test circuits and individual transistors are recorded, and will be compared with
their performance after CNT growth to assess the effectiveness of the thermal isolation.
4.3 On-chip Synthesis of Carbon Nanotubes
After the microheater release, the CMOS chips were carefully taken off from the carrier
wafer and then wire bonded to a DIP package. Next, the chips were coated with
alumina-supported iron catalyst by drop-drying on the surface [75]. The whole package was then
placed into a quartz chamber. The on-chip microheaters were turned on by applying appropriate
voltages such that bare growing was observed. The supplied voltage also introduced a local
E-field of about 0.1 ~ 1.0 V/μm simultaneously. The CNT growth was carried out using
1000-sccm CH4, 15-sccm C2H4 and 500-sccm H2 for 15 minutes, while the chamber remained at
room temperature all the time.
After a 15 minutes growth, CNTs were successfully synthesized. Two SEM images with
locally synthesized CNTs are shown in Fig. 4-8. The individual suspended CNTs in Fig. 4-8 A
are grown from the 3 μm × 3 μm microheater as shown in Fig. 4-6 E and land on the near
polysilicon tip. In the configuration with a parallel bridge as the secondary landing wall, the
growth exhibits less convergence due to the less converged E-field. Similar growth occurred on
11 out of 13 microheaters. The 1.2 μm × 1.2 μm microheater and the one with opposing sharp
68
tips were broken during the growth. The reason might be the presence of super-local heating that
causes the failure at grain boundaries.
Figure 4-8. Localized synthesis of carbon nanotubes grown from A) the 3 μm × 3 μm
microheater and B) the 6 μm × 6 μm microheater, suspended across the trench and connecting to the polysilicon tip/wall. Insets: SEM images of the overall microheater.
4.4 Characterization of Carbon Nanotubes and Circuit Evaluations
After the growth, the as-grown CNTs were characterized by measuring the resistance
between two polysilicon microstructures (the microheater and the landing wall) at room
temperature and at atmosphere. The I-V characteristic is shown in Fig. 4-9. The typical
resistances of in-situ grown CNTs are in the range of several MΩ. This large resistance is
primarily attributed to the contact resistance between the polysilicon and the CNTs. Recall that
the final step of the post-CMOS fabrication is meant to completely remove the silicon dioxide
and thus fully expose the ploysilicon surface. However, this step has been done long before the
growth process due to the subsequent steps such as wire-bonding, package, and catalyst
deposition. A thin layer of native oxide is expected to naturally grow on the polysilicon
electrode surface with a typical thickness of about 2 nm [131]. Other factors such as defects
along the CNTs might also contribute to the large resistance.
1 μm
Catalyst layer 10 μm
1 μm
10 μm
A) B)
69
Figure 4-9. I-V characteristics of the as-grown CNTs. The I-V curve is measured between two
polysilicon microstructures contacting the CNTs.
Figure 4-10. DC electrical characteristics of single transistors before and after CNT growth. A)
Drain current (Ids) versus grain voltage (Vds) for NMOS transistors under seven different gate voltages. B) Drain current (Ids) versus grain voltage (Vds) for PMOS transistors under seven different gate voltages.
After the successful on-chip synthesis of CNTs, the impact of the localized heating on the
nearby circuits was assessed. As mentioned in Section 4.1, the spacing ranges from 36 μm to
60 μm. Simple circuits, such as inverters, were first tested and verified their proper functions
after synthesis. Then, more accurate electrical characteristics were measured at the transistor
Ids (
A)
0 1 2 3 4 5 Vds (V)
0
0.5
1
1.5 × 10-3 Before After
Ids (
A)
-5 -4 -3 -2 -1 0 Vds (V)
-1.5
-1
-0.5
0 × 10-3
Before After
A) B)
Cur
rent
(nA
)
0
-0.25 0 0.25 0.5 Voltage
-50
-25
25
50
Voltage (V) -0.5
70
level. Fig. 4-10 shows the DC electrical characteristics of individual NMOS and PMOS
transistors before and after the CNT growth. The tests were performed at room temperature using
a Keithley 4200 semiconductor characterization system. The drain current versus drain-source
voltage (Ids-Vds) plots show no significant change after the synthesis, demonstrating the CMOS
compatibility of this integration approach.
It should be noted that after a short period (approximately one month), this MΩ resistance
became infinite. Recall that the synthesis on platinum microheaters exhibited kΩ resistances that
stayed almost the same after one year. These two synthesis experiments used the same catalyst
recipe and same growth procedure. The differences come from the electrode material, which
results in two types of contacts: one is polysilicon/CNTs versus Pt/CNTs, and the other is
polysilicon/catalyst versus Pt/catalyst. There might be two reasons that cause the failure. First, it
might be the result of the continuous oxidation of the polysilicon in air. Another possible reason
might be due to the weaker adhesion of the CNTs and catalyst particles to the polysilicon. In our
practice, the nanometer-scale iron catalyst particles are separated by and supported on alumina, a
thin non-conductive layer. As shown in Fig. 4-11, the catalyst on the top of the silicon dioxide
surface consists of discrete particles, with heater outline clearly visible (Fig. 4-11 A); the catalyst
on the top of the platinum surface has a fluffy appearance, with the underneath platinum
electrode partially exposed (Fig. 4-11 B).
However, the catalyst layer appears much thicker on CMOS chips, as evident from
Fig. 4-11 C-F. The catalyst layer extends over trenches (Fig. 4-11 C). A thick catalyst layer on
one of the heaters even cracks and peels off (Fig. 4-11 D). Some designed shapes (e.g. the multi-
tip landing wall) that have successfully survived the post-CMOS fabrication (Fig. 4-11 E) are
unable to be preserved after catalyst deposition (Fig. 4-11 F). The mock-CMOS devices have
71
Figure 4-11. SEM images showing the catalyst layers on A) silicon dioxide surface , B)
platinum microheater surface, and C) polysilicon microheater surface. D) An SEM image of one polysilicon microheater with thick catalyst layer peeled off. E) and F) SEM images of one polysilicon microheater before and after catalyst deposition. Multi-figure structure was completely covered by the catalyst layer. G) and H) Schematic cross-sectional views of mock-CMOS platinum heater and polysilicon heater embedded in CMOS chips.
Catalyst layer
100 nm
B)
10 μm
D)
1 μm
C)
10 μm
20 μm
E)
10 μm
F)
A)
1μm
H) G)
72
on-surface platinum microheaters (Fig. 4-11 G), while the CMOS chips have polysilicon
microheaters hidden inside the micro-cavities (Fig. 4-11 H). The topographic profiles, the
surface condition of different materials, and the further miniaturized feature size might all
contribute to the thicker catalyst layer, which in return might block the nanotube/polysilicon
contacts or result in weak adherence when CNTs reach the secondary electrode.
To improve the chemical stability and mechanical robustness, several possible solutions
are recommended for the future work. First, instead of using aluminum-supported iron catalyst
particles and drop-drying method, thin film metal catalysts can be deposited using various
techniques such as evaporation, sputtering or molecular beam epitaxy technique [132]. These
thin films will “ball up” and break up into particles during the growth as long as the film
thickness does not exceed the critical thickness [133]. In this way, the structure shape can be
preserved, and the thickness of the catalyst layer can be controlled. Second, contact activation
through electrical breakdown in the inert gas environment has been proved to be effective for
healing the 2 nm native oxide [111], which should be employed for our future contact resistance
investigations. Third, polymer deposition after the CNT growth has been reported to be capable
of stabilizing the nanotube/electrode contact resistances [134]. This coating might be helpful for
preventing the polysilicon from oxidation over time.
4.5 Summary
This chapter first presented the concept of the CMOS integrated CNTs and discussed the
integration principles in Section 4.1. FEM modeling of the 3 μm × 3 μm heating unit has been
done to estimate the working temperature. Based on the simulation result, various designs of
microheaters were presented and discussed. Then a 1.5 × 1.5 mm2 chip layout, including test
circuits and 13 embedded microheaters, was revealed. In Section 4.2, a novel maskless post-
CMOS MEMS fabrication process flow was discussed in detail. The temperature dependent
73
resistivity and the electrical characteristics of the polysilicon microheaters were theoretically
discussed. The released microheater was tested and compared with the results reported in the
literature. Then on-chip CNT synthesis process was presented in Section 4.3. Both the CNTs and
the transistors were characterized and evaluated in Section 4.4. Observed catalyst and contact
resistance problems were discussed, followed by some recommendations for future work.
This monolithic CMOS-CNT integration approach is fully compatible with commercial
foundry processes, and requires no photolithography or metal deposition steps. It has been
demonstrated that CNTs can be synthesized on specific positions determined by local
temperature and E-field distribution, without deteriorating the neighboring CMOS circuits. This
simple, scalable and low-cost integration approach opens up the possibility of integrating CNTs
with commercial foundry CMOS circuitry for emerging hybrid nanoelectronics applications.
74
CHAPTER 5 FUTURE WORK
As mentioned in Section 4.5, the monolithic CMOS-CNT integration approach proposed in
this thesis is promising for making various nano-devices and integrated micro/nano-systems.
However, the research work done so far serves primarily as a foundation and a preliminary stage
of exploration to demonstrate the possibility. To realize the large scale manufacture of the
functional CMOS-CNT hybrid devices with high yield and high performance, the most important
future work that needs to be done are the CNT synthesis control and contact improvement.
First, synthesis process could be better controlled. In future designs, thin film metal
catalysts should be investigated, and compared with drop-drying method to find out the best
recipe. A 15 minutes growth process was used in our previous attempts. In future experiments,
electrical parameters, such as the resistance between the microheater and the secondary
electrode, could be in situ monitored to indicate the accomplishment of the CNT assembly
process. The resistance will change from infinite to the resistance of the first bridging nanotube
and decrease continuously once more nanotubes are electrically connected to the secondary
electrode. Thus, the quantity of the assembled nanotubes could be counted and controlled. It will
be very helpful for individual nanotube characterization. In our previous growth experiments,
there were numerous parallel nanotubes, so the test results were the outcomes of a mixture. With
one single nanotube on each device, the properties of individual nanotube could be better
characterized under electrical gating, and the relation of grow model and contact resistance could
be further investigated.
Second, several post-growth treatments could be investigated in the future work. Contact
activation through electrical breakdown could be employed to heal the native oxide on the
surface of the polysilicon microheaters. Experiments should be done to find out the dominant
75
failure mechanism of the infinite polysilicon/nanotube contact resistance over time. For example,
one could monitor the resistances of four devices (with/without the presence of oxygen,
with/without the mechanical shake) to investigate the oxidation of the polysilicon and the
adhesive stability. Then, the affect of polymer functionalization on the contact stabilization and
on the sensing selectivity could be investigated.
Finally, in order to fabricate functional CMOS-CNT hybrid devices and take the advantage
of the standard CMOS technology, advanced signal processing circuits should be designed and
integrated with the microheaters. The microheaters and the polysilicon pads could be further
scaling down to increase the integration density. Large arrays with multiplex CNT-based sensors
could be developed, and other application as chemical and biological sensors should be explored.
.
76
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BIOGRAPHICAL SKETCH
Ying Zhou became interested in scientific research in high school and won the first prize in
the Chinese National Chemistry Olympic Contest for High School Students. After graduating
high school she enrolled at Fudan University in the fall of 2003. As an undergraduate at Fudan
University, she participated in various projects including nanoparticle-based electrochemical
DNA sensor research. In the fall of 2007, she received her B.S. in Microelectronics from Fudan
University, and then enrolled at the University of Florida and joined the Interdisciplinary
Microsystems Group (IMG) in the Department of Electrical and Computer Engineering. Her
M.S. thesis research involved the design, modeling, and fabrication of on-chip microheaters, as
well as the synthesis and characterization of CMOS-integrated carbon nanotubes. She entered a
joint master program in June 2008, and will receive her M.S. in Electrical Engineering in August
2009 and M.S. in Management in the fall of 2009. After graduation, she will continue her
education with the pursuit of the Ph.D. in business with a concentration in accounting at UF.