© 2005 altera corporation © 2006 altera corporation simulation with mentor graphics modelsim

© 2005 Altera Corporation© 2006 Altera Corporation

Simulation with Mentor Graphics ModelSim

2© 2006 Altera Corporation

ObjectivesObjectives

Students will be able to: Create working libraries in ModelSim Compile HDL files into working libraries Understand ModelSim projects Run functional simulations using both ModelSim force commands and HDL

testbenches Generate all the files in Quartus II required to perform timing simulations


PLD Design Flow ModelSim Overview Simulating with ModelSim

RTL (Functional) Simulation Gate Level (Timing) Simulation

OutlineOutline


Typical PLD Design Flow


Synthesis (Quartus II, Leonardo Spectrum, Synplify, etc.) - Translate Design into Target Technology Primitives - Optimization to Meet Required Area & Performance Constraints

Design Specification

Place & Route - Map Primitives to Specific Locations Inside Target Technology - Specify Routing Resources to Be Used - May Require Design Edits

Design Entry/RTL Coding - Behavioral or Structural Description of Design

RTL Simulation (Quartus II or ModelSim®) - Functional Simulation - Verify Logic Model (No Timing Delays) - May Require Design Edits

Typical FPGA Design Flow


Timing Analysis - Verify Performance Specifications Were Met - May Require Design Edits

Gate Level Simulation (Quartus II or ModelSim) - Timing Simulation - Verify Design Will Work in Target Technology - May Require Design Edits

PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board

Typical FPGA Design Flow


ModelSim Overview

© 2006 Altera Corporation

Developed by Mentor Graphics

One of Industry’s Most Popular Simulators

Simulates both Verilog & VHDL OEM Version allows for Verilog

simulation OR VHDL simulation

ModelSim Simulation ToolModelSim Simulation Tool


Complete Standards Support ‘87 VHDL ‘93 VHDL IEEE 1364-2001 Verilog SDF 1.0 - 3.0 VITAL 2.2b, VITAL 95, VITAL 2000

Easy-to-use Interface Common across platforms Available for PC, UNIX and Linux environments

NativeLink Quartus II can automatically invoke ModelSim after place and route is

finished

ModelSim OEM FeaturesModelSim OEM Features


On-Line Help -> ModelSim Altera Documentation Stored in <installation_directory>\docs\ Can also be accessed from Main window Help menu -> PDF

Documentation ModelSim Altera User’s Manual (oem_man.pdf)

Library / Project Management User Interface / Menus

ModelSimAltera Command Reference (oem_cmds.pdf) All ModelSim commands and valid arguments

ModelSim Altera Tutorial (oem_tutor.pdf)

Questions about ModelSim?Questions about ModelSim?


Simulating with ModelSim

© 2006 Altera Corporation

Basic Simulation Steps User Interface Functional Simulation Quartus II Output Simulation Files Timing Simulation

AgendaAgenda


ModelSim Execution MethodsModelSim Execution Methods

Graphical User Interface (GUI) Can accept menu input and command line input Main discussion of class

Interactive Command Line (Cmd) Only interface is a command line console, no User Interface

TCL Scripts and ModelSim Macros TCL – Industry standard scripting language Macros (DO files) – easily created from main window transcripts (GUI

commands write equivalent Cmd functions to main window)


Basic Simulation StepsBasic Simulation Steps

Step 1 Create library(s)

Step 2 Map library to physical directory

Step 3 Compile source code

- All HDL Code must be compiled

- Different for Verilog and VHDL

Step 4 Start simulator and load top-level design unit

Step 5 Advance simulator


Step 1 Creating ModelSim library(s)Step 1 Creating ModelSim library(s)

GUI) From within Main Window: File -> New -> Library…

Cmd) From within Main, transcript window:ModelSim> vlib <library name>Example: vlib my_work


What are ModelSim Libraries?What are ModelSim Libraries?

Directories that contain compiled design units Both VHDL and Verilog are compiled into libraries

Two Types Working (default work)

Contains the current design unit being compiled Must create a working library before compiling Only one allowed per compilation

Resource Contains designs units that can be referenced by the current

compilation Multiple allowed during compilation VHDL libraries can be referenced by LIBRARY and USE clauses


Creating New Libraries (GUI)Creating New Libraries (GUI)

Select a new library and a logical mapping to it and type library name

This command creates a library subdirectory in the local directory and then sets the mapping for it

Executing this GUI command producesthis at the command prompt transcript:ModelSim > vlib my_libModelSim > vmap my_lib my_lib


Syntax: vlib <library_name> Creates libraries Default is “work”

Library <library_name> contains

_info file

verilog_module name vhdl_unit name

_primary.dat

_primary.vhd

verilog.psm

_primary.dat

<arch_name>.dat

<arch_name>.asm Where

_info - file created so ModelSim recognizes directory as a library _primary.dat - encoded form of Verilog module or VHDL entity _primary.vhd - VHDL entity representation of Verilog ports <arch_name>.dat - encoded form of VHDL architecture verilog.asm and <arch_name>.asm - executable code files

Creating New Libraries (GUI)Creating New Libraries (GUI)


Step 2 Map Logical Library Name(s)Step 2 Map Logical Library Name(s)

GUI) From within Main Window:

File -> New -> Library…

Cmd) From within Main transcript window:ModelSim> vmap <logical_name> <directory_path>Example: vmap my_work c:\my_design\my_lib

Use to map to a library of pre-compiled design units

Select a map to an existing library and type library name

Browse to library directory


Mapping Logical Library NamesMapping Logical Library Names

Must map a Logical Library Name to Library Path (ie. location on hard drive) Files in library path must already have been compiled Relative, absolute, and soft path names supported

Needed for libraries not located in the working directory Use vmap command


Other Library CommandsOther Library Commands vdir - Displays the contents of a

specified library

vdel - Deletes an entire library or a design unit from a specified library

GUI) From Main Window “Library” tab, click + to expand

Cmd) vdir -lib library_name>

GUI) From Main Window “Library” tab, right click library or design unit and select “Delete”

Cmd) vdel -lib <library_name> <design_unit>


Step 3 Compile Source Code (VHDL)Step 3 Compile Source Code (VHDL)

GUI) Compile -> Compile… Cmd) vcom -work <library_name> <file1>.vhd <file2>.vhd

Files are compiled in the order they appear Compilation order/dependencies (next slide)

‘87 VHDL is default GUI) Use Default Options button to set ‘93 Cmd) Use -93 option (must be first argument)

Default compiles into library work Example: vcom -93 my_design.vhd

Note: Design units must be re-analyzed when the design units they reference are changed in the library.


Step 3 Compile Source Code (Verilog)Step 3 Compile Source Code (Verilog)

GUI) Compile -> Compile… Cmd) vlog -work <library_name> <file1>.v <file2>.v

Files are compiled in the order they appear Order of files or compilation does not matter

Supports Incremental Compilation Default compiles into library work

Example: vlog my_design.v

Note: Design units must be re-analyzed when the design units they reference are changed in the library.


Compile (Using GUI)Compile (Using GUI)

2). Highlight one or multiple files and click Compile

1). Choose Compile -> Compile…


Step 4 Start the SimulatorStep 4 Start the Simulator

GUI) Simulate -> Simulate… Cmd) vsim <top_level_design_unit>

VHDL vsim top_entity top_architecture

Simulates Entity/Architecture pair Can also choose a Configuration

Verilog vsim top_level1 top_level2

Simulates multiple top level Modules


Start Simulator (GUI)Start Simulator (GUI)

3). Choose simulator resolution

2). Select and expand library

4). Select top-level module or entity/architecture, click OK.

1). Choose Simulate -> Simulate…


6). Then click OK.

5). For timing simulation, select SDF tab and then Add SDO file

Start Simulator (GUI) – continued

Type hierarchical level that timing values apply to (if not top level)


vsim Command Argumentsvsim Command Arguments

Arguments -t <time_unit>

Specifies simulation time resolution Units can be {fs, ps, ns, ms, sec, min, hr} If Verilog `timescale directives are used, the minimum time

precision from all design files will be used Optional (default is ps)

-sdfmin | -sdftyp | -sdfmax <instance>=<sdf_filename> Annotates SDF file Optional Using instance names is also optional; If unused, SDF

applies to top level


vsim Command Argumentsvsim Command Arguments

Arguments -L <library_name> (Verilog)

Specifies that a particular library should be searched for design units during simulation

If multiple libraries are used, each requires the -L option Optional (default is work)

-L <library_name>.<design_unit> Specifies a particular library and design unit to simulate Library name is optional (default is work)


Step 5 Advance SimulatorStep 5 Advance Simulator

GUI) Simulate -> Run Cmd) run <time_step> <time_units>

Advances the simulator in the amount of timesteps specified


Advance Simulator (GUI)Advance Simulator (GUI)

Restart - Reloads any design elements that have been edited and resets the simulation time to zero

Cmd) restart

Choose the number of timesteps to advance the simulator


run Command Argumentsrun Command Arguments

Optional Arguments -<timesteps> <time_unit>

Specifies the number of timesteps to run Units can be {fs, ps, ns, ms, sec}

-step Steps to the next HDL statement

-over Steps to the next HDL statement Treats VHDL procedures, functions, and Verilog tasks as

single executable


run Command Argumentsrun Command Arguments

Optional Arguments -continue

Continues the last simulation after a -step, step -over or breakpoint

-all Runs simulator until no more events are scheduled Maximum simulation time is 264 timesteps


Breaking Simulation runBreaking Simulation run

Use Break Key to stop (pause) simulator while

advancing

Break Key


Simulator StimulusSimulator Stimulus

Force Commands Simple module simulation Directly from command console .DO file (macro file)

Testbench Verilog or VHDL Very complex simulation interactive simulation


force Commandforce Command

Allows user to apply stimulus to VHDL signals and Verilog nets General Syntax:

force <item_name> <value> <time>, <value> <time> Arguments

item_name The name of the HDL item to be forced Required ‘/’ indicates hierarchical levels Must be a scalar or one-dimensional array of characters

Can be an indexed array, array slice, or record sub-element as long as its of the above type

Can use wildcards as long as only one match is obtained


force Command (cont.)force Command (cont.)

More Arguments value

Value to which the item is forced Must fit item’s data type Required

time Specifies the time unit for the value Relative to current simulation time

Use @ character to specify absolute time Time units can be specified

Default is simulation resolution units Optional

Value Description

1111 character sequence

2#1111 binary radix

10#15 decimal radix

16#F hexadecimal radix


force Command (cont.)force Command (cont.)

More Arguments -r[epeat] <period>

Repeats the force command for the specified period Optional

-cancel <period> Cancels the force command after the specified period Optional


DO FilesDO Files

Macro file for automating simulation steps Library setup Compiling Simulating Forcing simulator stimulus

Can be invoked in all ModelSim modes GUI) Tools -> Execute Macro… Cmd) do <filename>.do

Can call other DO files

cd c:\mydirvlib workvcom counter.vhdvsim counterview *add wave /*add list /*do run.do


Debugging DesignsDebugging Designs

When to debug? Unsuccessful compilation Incorrect or unexpected simulation results

Example ModelSim Debugging Capabilities Signal Monitoring Breakpoints


Monitoring More SignalsMonitoring More Signals

Add additional signals or variables for tracking Select region in Structure window or the sim tab of

the main window workspace.

“drag and drop” from Source, Signals or Variables windows to:

Wave window List window


BreakpointsBreakpoints

Two types of breakpoints are supported Breakpoints on line(s) in source code window

Toggles - click again to delete existing breakpoint No limit to the number of break points Use command bp

bp <file_name> <line#>

Conditional break points when <condition> <action> when {b=1 and c/=0} Used with VHDL signals and Verilog nets and registers Use command bp also

bp <file_name> <line#> {if{$now/=100}then{cont}}


modelsim.ini filemodelsim.ini file An ASCII file used by ModelSim, controlled by the user A default file is provided in the ModelSim installation directory modelsim.ini is used by the compiler and the simulator

Stores initialization information Location of libraries location of startup file Other default settings for ModelSim

ModelSim searches for the modelsim.ini in the following order:1. Environment variable called MODELSIM which points directly to the

modelsim.ini file to be used2. A file called modelsim.ini located in the current working directory3. The default modelsim.ini file in the ModelSim software installation tree


startup.do filestartup.do file

A DO script automatically executed by vsim upon startup An example startup.do file might look like this:

view source

view structure

view wave

do wave.do To invoke a startup file, uncomment (remove the “;” from) the

following line in the modelsim.ini file and provide path to the do file:;Startup = do /<path_to_startup>/startup.do


ModelSim ProjectsModelSim Projects

Projects are a collection of entities for HDL designs under specification or test

Projects are stored as .MPF file in the project directory and contain: Root directory and subdirectories “work” library and other project libraries or references to libraries HDL source files or references to source files Compiler and simulator settings

Allows you to save current work session Used mostly with GUI Project Operations

File -> New / Open / Close / Delete


Benefits of Using Projects in ModelSimBenefits of Using Projects in ModelSim

Simplifies interaction with ModelSim Compile order of source files is maintained in project Compiler settings and switches are stored in project Allows for easy sharing of libraries without copying files to a local

directory Creating a project creates your “work” library automatically The project .MPF file contains all of the settings in the main

modelsim.ini file located in the ModelSim install directory


Applying ModelSimto the

PLD Design Flow


System Production


Typical PLD Flow

Design Entry

RTL Simulation

Design Synthesis

Gate Level Simulation

Place & Route

Timing Analysis

In-System Verification

Design Modification

ModelSim


RTL (Functional) SimulationRTL (Functional) Simulation

Pre-Place & Route Simulation Test Logical Model Perform the Basic Simulation Steps on Design

Files Exception: Using LPMs or MegaWizard

Generated Functions Must Map to Simulation Models Stored in <ModelSim_install_dir>\altera Directory


LPM Simulation Models (Verilog)LPM Simulation Models (Verilog) Pre-Compiled Simulation Models for Standard LPM Functions

ModelSim OEM Only Examples

LPM_ADD_SUB LPM_COUNTER LPM_MULT

Library 220model_ver Pre-Mapped to Directory <ModelSim_install_dir>\altera\verilog\220model

Specify Library 220model_ver when Starting Simulator

LPM_RAM_DP LPM_RAM_DQ LPM_AND / LPM_OR


Verilog LPM SimulationVerilog LPM Simulation

Cmd) vsim –L 220model_ver <design_unit>

GUI) When loading the design, click on the Libraries tab.Click Add and browse to the 220model directory:

\<ModelSim OEM install directory>\altera\verilog \220model


LPM Simulation Models (VHDL)LPM Simulation Models (VHDL) Pre-Compiled Simulation Models for Standard LPM Functions

ModelSim OEM Only Examples

LPM_ADD_SUB LPM_COUNTER LPM_MULT

User Must Map Library <Library_Name> to <ModelSim_install_dir>\altera\vhdl\220model Directory

Type LIBRARY & USE Clauses in Design File (added automatically by MegaWizard for examples above) LIBRARY <LIBRARY_NAME> ; USE <LIBRARY_NAME>.lpm_components.all:

LPM_RAM_DQ LPM_RAM_DP LPM_AND / LPM_OR


Altera Megafunction Models (Verilog)Altera Megafunction Models (Verilog)

Pre-compiled Simulation Models for Altera-Specific Megafunctions ModelSim OEM Only

Examples ALTCDR_RX or ALTCDR_TX (Clock Data Recovery) ALTQPRAM (Quad-Port RAM) ALTCAM (Content Addressable Memory) ALTCLOCKLOCK (PLL)

Library altera_mf_ver Pre-mapped to Directory <ModelSim_install_dir>\altera\verilog\altera_mf

Specify Library altera_mf_ver When Starting Simulator


Altera Megafunction Models (VHDL)Altera Megafunction Models (VHDL)

Pre-compiled Simulation Models for Altera-Specific Megafunctions ModelSim OEM Only

Examples ALTCDR_RX or ALTCDR_TX (Clock Data Recovery) ALTQPRAM (Quad-Port RAM) ALTCAM (Content Addressable Memory) ALTCLOCKLOCK (PLL)

Library altera_mf Pre-Mapped to <ModelSim_install_dir>\altera\vhdl\altera_mf

Type LIBRARY & USE Clauses in Design File (added automatically by MegaWizard for examples above) LIBRARY altera_mf; USE altera_mf.altera_mf_components.all:


Testbench Testbench

In the early days of HDLs, stimulus and verification was made through proprietary simulator methodologies Vector waveform files (Quartus II) Force Files (Mentor Graphics)

Testbench not portable between tools Using a testbench written in HDL simplified design flow and

increased portability


Three Classes of TestbenchesThree Classes of Testbenches

I. Test bench applies stimulus to target code and outputs are manually reviewed

II. Test bench applies stimulus to target code and verifies outputs functionally• Requires static timing analysis

III. Test bench applies stimulus to target code and verifies outputs with timing• Does not require full static timing analysis• Code and test bench data more complex


Class IClass I

Simplest to write (no verification code) Requires manual verification (usually visual) Original designer who fully understands code can more easily

understand waveforms and timing Different engineer may miss errors or take much longer to

understand target code to verify manually Best used for simpler target code & code not intended for re-use


Class IIClass II

Harder to write and debug initially Writing “expected results” vectors requires deep understanding of

target code and can typically help make code better by forcing engineer to do more work up front

Fallback is that errors in the “expected results” vectors can be hard to catch

Benefit is that you can “set it and forget it” (besides static timing analysis / timing simulation)


Class IIIClass III

Much harder to write and debug initially Writing “expected results” vectors requires deep understanding of

both target code and timing information – setup and hold times for clock edges checked

Can require substantial changes to both testbench and vectors every time a design or process change occurs

Most in-depth of test benches but can be overkill for most situations


ENTITY gatetest ISEND gatetest;

ARCHITECTURE stimulus OF gatetest IS

COMPONENT simplegate PORT (A,B: IN std_logic; Y: OUT std_logic); END COMPONENT; SIGNAL A,B,Y: std_logic; BEGIN NAND1: simplegate PORT MAP(A => A,B => B,Y => Y); PROCESS CONSTANT period : TIME := 40 ns; BEGIN A <= '1'; B <= '1'; WAIT FOR period; A <= '1'; B <= '0'; WAIT FOR period; A <= '0'; B <= '1'; WAIT FOR period; A <= '0'; B <= '0'; WAIT FOR period; WAIT; END PROCESS; END stimulus;

Sample VHDL Class I TestbenchSample VHDL Class I Testbench

Declare Lower-Level Design Entity

Top-Level Entity Has No Ports

Signals to Assign Values & Observe

Instantiate Lower-Level Entity

Process to Apply Stimulus

Final WAIT Keeps Process from Repeating Indefinitely


System Production


Typical PLD Flow

Design Entry

RTL Simulation

In-System Verification

Design Modification

ModelSim

Timing Analysis

Place & Route

Design Synthesis

Gate Level Simulation


Performing Post P&R (Timing) SimulationPerforming Post P&R (Timing) Simulation

1) EDA Tool Settings to ModelSim Verilog or VHDL

2) Compile Design in Quartus II to Produce Output Files

3) Create Testbench / Stimulus

- Can Use Stimulus From RTL Simulation

4) Perform Basic Simulation Steps

- Compile Quartus II Output File

- Map to ATOM Libraries

- Include SDO (SDF format) File When Loading Design


Before CompilationBefore Compilation

Assignments Menu -> EDA Tool Settings…


NativeLinkNativeLink

Automatically starts ModelSim and compiles the Quartus II output file after compilation is finished


Specify Path to SimulatorSpecify Path to Simulator

Tools Options EDA Tool Options

Double-click to specify path to simulation tool executable


Enable NativeLink SettingsEnable NativeLink Settings

None NativeLink compiles simulation models & design files

Compile test bench NativeLink compiles all files (including test bench) and starts

simulation Use script to compile test bench

NativeLink compiles simulation models & design files User specifies script to compile test bench and start simulator


Setting Up Test BenchesSetting Up Test Benches

Create test bench settings for each test bench to be simulated


Running NativeLink SimulationRunning NativeLink SimulationTools EDA Simulation Tool

Select RTL or Gate-level simulation


Post Place & Route Simulation FilesPost Place & Route Simulation Files

Compile Design in Quartus II to Produce Output Files Output Simulation Files from Quartus II

.VO - Verilog Output File .VHO - VHDL Output File .SDO - Standard Delay Format (SDF) Output File

Annotates the delay for the elements in the output files

Design files-.EDF-.VQM- .V- .VHD

.VO

.VHO

.SDO


Pre-Compiled Design Units are Provided for RTL and Post Place and Route Simulation For OEM ModelSim only For MSE and MPE, uncompiled source code is provided (with the exception

of Stratix GX libraries which are always pre-compiled)

Mapping Libraries If you create a ModelSim project, all device families’ libraries are pre-mapped

for you. Otherwise, you must map each device family individually eg. Stratix,Cyclone, etc. Device Libraries Would Be Manually Mapped

Map stratixii_ver to <ModelSim_install_dir>\altera\verilog\stratixii Map cyclone_ver to <ModelSim_install_dir>\altera\verilog\cyclone

ATOM Simulation Files (Verilog)ATOM Simulation Files (Verilog)


ATOM Simulation Files (Verilog)ATOM Simulation Files (Verilog) Specify Appropriate Library When

Starting Simulator -L stratixii_ver -L stratix_ver -L cyclone_ver -L stratixgx_ver -L apex20ke_ver

Command Line

GUI


ATOM Simulation Files (VHDL)ATOM Simulation Files (VHDL) Pre-Compiled Design Units Are Provided for RTL and Post Place & Route

Simulation For OEM ModelSim only And for MSE and MPE, uncompiled source code is provided (with the exception of

Stratix GX libraries which are always pre-compiled)

LIBRARY & USE Clauses Already Written in .VHO File LIBRARY alt_vtl; USE ALT_VTL.<device_family_components>.all

Mapping Libraries Unless you use ModelSim Projects, you must map to alt_vtl library to:

<ModelSim_install_dir>/altera/vhdl/stratixii <ModelSim_install_dir>/altera/vhdl/cyclone <ModelSim_install_dir>/altera/vhdl/stratixgx <ModelSim_install_dir>/altera/vhdl/apex20ke


SDF AnnotationSDF Annotation

Click on SDF Tab to assign timing file

Click Add button

Specify the SDO file and the Apply Region


Exercise

Please go to Exercise


Exercise SummaryExercise Summary

Functional Simulation w/ModelSim Use Pre-Compiled ModelSim Libraries Timing Simulation w/ModelSim

Quartus II EDA Tool Settings Mapping to correct simulation models


ModelSim Basic Simulation ReviewModelSim Basic Simulation Review

cd Into Working Directory Create Working Library to Compile Design Units Into (Optional) Map to Libraries of Pre-Compiled Design Units Compile All Design Units Into Library Note: must compile from bottom-up when using VHDL Add SDO File From Quartus II (If Performing Timing-Simulation) Link in Behavioural or Device-Specific Libraries As Required Load Top-Level Design (or testbench) Into Simulator and Set Simulator Resolution Open Wave Window and Add Signals You Are Interested In Apply Force Commands (If A Testbench Not Used) Advance Simulator to Generate Vectors in Wave Window Debug Your Design


PLD Design Flow ModelSim Overview Simulating with ModelSim

RTL (Functional) Simulation Gate Level (Timing) Simulation

Class Summary

© 2005 altera corporation © 2006 altera corporation simulation with mentor graphics modelsim

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