第 10 章移位暫存器 10-1 移位暫存器的基本功能 10-2 串列輸入 /...

第 10 章移位暫存器• 10-1 移位暫存器的基本功能• 10-2 串列輸入 / 輸出移位暫存器• 10-3 其他移位暫存器的線路型態• 10-4 移位暫存器計數器• 10-5 移位暫存器的應用

Figure 10--1 The flip-flop as a storage element.

Thomas L. FloydDigital Fundamentals with VHDL

Copyright ©2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

10-1 移位暫存器的基本功能

Figure 10--2 Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)




10-1 移位暫存器的基本功能

Figure 10--3 Serial in/serial out shift register.




10-2 串列輸入 / 輸出移位暫存器

Figure 10--4 Four bits (1010) being entered serially into the register.Thomas L. FloydDigital Fundamentals with VHDL




Figure 10--5 Four bits (1010) being serially shifted out of the register and replaced by all zeros.


Figure 10--6 Open file F10-06 to verify the operation.





例題 10-1

根據圖 10-6(a)指定的輸入資料與時脈脈波，試畫出五位元暫存器的位元狀態。

Figure 10--7 Logic symbol for an 8-bit serial in/serial out shift register.





Figure 10--8 A serial in/parallel out shift register.




10-3 其他移位暫存器的線路型態

Figure 10—9 4位元暫存器的狀態





例題 10-2根據圖 10-9(a) 輸入資料與時脈脈波，畫出4 位元暫存器的狀態。

Figure 10--10 A 4-bit parallel in/serial out shift register. Open file F10-10 to verify the operation.





Figure 10--11





例題 10-3試根據圖 10-11(a) 的並列輸入資料、時脈與SHIFT /LOAD 的波形，畫出 4 位元暫存器的資料輸出波形。

Figure 10--12 A parallel in/parallel out register.





Figure 10--13 Four-bit bidirectional shift register. Open file F10-13 to verify the operation.





Figure 10--14





例題 10-4試根據圖 10-14(a) 中控制輸入RIGHT /LEFT 的波形，求出再每一個時脈脈波之後，圖 10-13 移位戰存器的狀態。假設Q0=1、 Q1=1、Q2=0、 Q3=1 ，而且串列資料輸入為 LOW 狀態。

Figure 10--15 4-bit and 5-bit Johnson counters.




10-4 移位暫存器計數器

Figure 10--16 Timing sequence for a 4-bit Johnson counter.





Figure 10--17 Timing sequence for a 5-bit Johnson counter.





Figure 10--18 A 10-bit ring counter. Open file F10-18 to verify the operation.





Figure 10--19





例題 10-5如果有一個類似據圖 10-18 的環狀計數器，它的初始狀態為 1010000000，試畫出每一個輸出端 Q 的波形。

Figure 10--20 The shift register as a time-delay device.




10-5 移位暫存器的應用

Figure 10--21





例題 10-6試計算圖 10-21 中，在串列輸入端與每一個輸出端之間延遲時間。並繪出時序圖說明。

Figure 10--22 Timing diagram showing time delays for the register in Figure 10-21.





Figure 10--23 A shift register connected as a ring counter.





Figure 10--24 Timing diagram showing two complete cycles of the ring counter in Figure 10-23 when it is initially preset to 1000.





Figure 10--25 Simplified logic diagram of a serial-to-parallel converter.





Figure 10--26 Serial data format.





Figure 10--27 Timing diagram illustrating the operation of the serial-to-parallel data converter in Figure 10-25.


Figure 10--28 UART interface.





Figure 10--29 Basic UART block diagram.





Figure 10--30 Simplified keyboard encoding circuit.


Figure 10--31 Sample test pattern.





Figure 10--32 Basic test setup for the serial-to-parallel data converter of Figure 10-25.




Figure 10--33 Proper outputs for the circuit under test in Figure 10-32. The input test pattern is shown.




Figure 10--34 Logic symbol for the 74HC164.




Figure 10--35 Logic symbol for the 74HC194.




Figure 10--36 An n-bit serial in/serial out shift register.




Figure 10--37 Serial in/serial out shift register simulation waveform.




Figure 10--38 Serial in/parallel out shift register.




Figure 10--39 Typical combinational SHIFT/ logic for one D input of a parallel in/serial out shift register.




Figure 10--40




Figure 10--41 Bidirectional shift register.




Figure 10--42 Output waveform for a 4-bit bidirectional shift register.




Figure 10--43 Timing sequence simulation for the 4-bit Johnson counter.




Figure 10--44




Figure 10--45 Timing sequence simulation for the 4-bit ring counter.




Figure 10--46 Basic logic diagram of the security entry system.




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第 10 章 移位暫存器 10-1 移位暫存器的基本功能 10-2 串列輸入 /...

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第 10 章移位暫存器 10-1 移位暫存器的基本功能 10-2 串列輸入 /...