Spring 2007 Yield Management Solutions44

The CD error (CDE) is the sum of edge placement errors in the first and second patterning steps, including intra-layer mis-registration or overlay error (OLE). In dense patterns, overlay error can produce lines that are alternately too large and too small (Figures 1-2). This is the first major objection to DPL.

The second major objection is cycle time, which increases due to the extra photo and etch steps. The revenue loss (∆R) arising from increased cycle time (∆t) is expressed in this modified Leachman model:

( ) ( ) ( ) ( )dttPtDdtttPtDRTT

∫∫ −∆+=∆00

Here, D is the rate of good die out and P is the average selling price at time (t) over the interval (T). If P were constant, rev-enue loss would be zero; but, for products like flash memory, price can decline 50% in a year, resulting in extreme sensitiv-ity to cycle time variation.

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immer-sion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. This article discusses interim solutions for control of DPL.

Double patterning usually consists of a first exposure step, fol-lowed by a hard-mask etch. A second exposure with a different reticle is followed by another hard-mask etch. At this point, CD and overlay error combine in the resulting pattern, so that

OLECDECDECDE ±+= 21 21

21

Enabling Double Patterning at the 32nm Node Kevin M. Monahan – KLA-Tencor Corporation

The use of double patterning lithography (DPL) at the 32nm node poses several challenges. The sum of edge placement

errors in multiple patterning steps (CD error) can make DPL significantly more sensitive to overlay error. And the increase

in cycle time, with two photo and etch steps, can result in lower throughput and higher cost. Implementing grating-based

overlay technology can improve accuracy and minimize overlay model residuals, while grating-based scatterometry

can be used to measure shape and profile parameters that support direct feedback of focus and exposure corrections

to the litho cell.

Etch Layer OLE=0

HM1

PR2 PR2

HM1

Figure 1: Abbreviated DPL process with zero overlay error. The challenge is to match the etch CD from resist and hard mask structures.

Etch Layer OLE>0

HM1HM1

PR2 PR2

Figure 2: Abbreviated DPL process with non-zero overlay error. The chal-lenge is to control intra-layer overlay error to reduce the overall CD error.

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45

Enabling Overlay Control for DPL

DPL is up to three times more sensitive to overlay error due to the interaction of overlay with critical dimension. Conse-quently, overlay metrology must represent in-die misregistra-tion accurately to enable the higher-order corrections required for DPL. To improve accuracy, overlay will be measured in the die using small grating-based targets (Figures 3 and 4) embedded in dummy-fill structures (logic) or in DFM-opti-mized areas (memory). This will result in more representative sampling, reduction in model residuals, and improved overlay correction. The yield benefits of in-die overlay metrology are already evident in the current generation of semiconductor technology, and these benefits are expected to increase mono-tonically as the industry approaches the 32nm node1.

Note that state-of-the-art immersion lithography tools have dual stages, so that dry metrology and wet exposure can be performed in parallel. Within the wafer, exposure uses alternating scan directions. These operations can produce wafer-to-wafer and field-to-field overlay error, respectively. In addition, immersion typically requires a water dispensing system with an air curtain for droplet containment. Rapid motion of the wafer under the lens may create inhomogeneous thermal conditions, resulting in unmodeled overlay error. Notwithstanding, overlay specifications for the most advanced 45nm lithographic technology are about 6nm for a single tool (26x33mm field). Overlay matching is 8-10nm, but DPL re-quires a specification closer to 3nm. As a result, tool and stage dedication may be needed for DPL.

Figure 5 shows predicted 3-sigma overlay at the 32nm node relative to specification. Composite factory data for the current technology node were adjusted using ITRS scaling to make the comparison. Modern scanning exposure tools use two wafer stages: in Figure 5, the orange bars represent stage 1 while green bars represent stage 2. Note that stage 1 is consistently in spec while stage 2 is consistently out of spec.

These disparities are not simple offsets. They arise from the variance of model residuals and may not be easy to correct. In the case of systematic overlay signatures, stage dedication may be a viable solution; however, this strategy comes with a pro-ductivity penalty. At 25 wafers per lot, the correct stage may present itself about 50% of the time, resulting in an additional productivity loss of 2%. This loss will be limited to DPL lay-ers where stage dedication is necessary.

Enabling CD Control for DPL

DPL is much more sensitive to resist profile error when cycle-time is forced down by performing the final etch directly after the second photo step. Part of the pattern is defined by a hard mask and part by resist. Consequently, resist profile control will be critical in order to match the result of the first pattern-ing step. To improve resist profile control, three-dimensional focus-exposure windows can be created using data from 3D scatterometry.2 Initially, we expect to measure bar structures in grating patterns and get width, length, and end-wall angle data that correlate strongly with focus and exposure (Figure 6). Later, as with overlay metrology, such interim methods may be supplanted by true in-die profile and shape metrology.

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Figure 3: Traditional large box-in-box overlay targets suffer from sensitivity to process variation. Grating targets like the one above can reduce error by >2x.

Figure 4: Micro-grating targets enable overlay to be measured in-die and can provide the local accuracy required for DPL (box in lower right is a simulation).

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-11 3 5 7 9 11 13 15 17 19 21 23 25

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Figure 5: Predicted 3-sigma overlay at the 32nm node relative to specification. The figure uses current technology node (65nm) composite factory data adjusted for ITRS scaling. The green bars represent stage 1 (which is consistently in spec) while orange bars represent stage 2 (which is consistently out of spec).

Patterning

Spring 2007 Yield Management Solutions46

of cases, sidewall spacers are formed on each side of a sacrifi -cial structure that is then etched away selectively (Figure 7). The spacers become hard masks for subsequent etching of the underlying substrate (Figure 8). In this way, two structures are formed where one existed before. With respect to overlay, the structures are inherently self-aligned if the CDE of the sacri-fi cial structure is zero. If the CDE is not zero, CD and overlay error are once again confounded. In addition, asymmetry in the spacer deposition or etch process can add incrementally to the overlay error, since

( )210 2

1CDECDECDEOLE −+=

For many designs, CD control may be an easier problem to solve. Although traditional methods for spacer CD measure-ment, such as TEM and SEM, have defi ciencies, scatterometry (SCD) has been shown to be an effective control methodology for spacers on gate structures3. TEM cross-sections contain excellent profi le information, but the measurement is destruc-tive, localized, and subject to human error in locating the material interfaces. SEM images contain very little profi le information, and the measurement is localized with poor defi -nition of the material interfaces and low sensitivity to small changes in spacer width. SCD, on the other hand, has the advantage of being a non-destructive, spatial averaging tech-nique that provides excellent profi le information and sensitivi-ty. Simulations (Figure 9) show more than adequate sensitivity to detect sub-nanometer CD changes, and spacers have been measured down to dimensions of 4nm (Figure 10).

Clearly, much of this work is directly applicable to spacer structures used for double patterning. Extensions of the SCD technology beyond simple oxide-nitride spacers to dual spac-ers4 are promising since these are more complex structures and double patterning may require scatterometry models with a higher number of fl oating parameters.

Spacer Etch Alternatives

Several companies have developed and patented alternative pitch splitting methods based on sidewall spacer formation and etching. Such methods take some of the patterning burden away from lithography, but they also create a need for addi-tional CVD, etch, clean, and inspection steps. In the simplest

Overlap

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Figure 6: Robust process windows can be constructed from 3D scatterometry data, such as end-wall angle, length, and width of bars in a grating target.

Figure 8: After the sacrifi cial structure is removed, the pattern is etched. Although the pattern is self-aligned, overlay error is confounded with CD error of the sacrifi cial structure.

1 20 1 20

Figure 7: Simplifi ed spacer-etch alternative to DPL. A sacrifi cial structure (0) is formed, followed by spacer deposition and etch to create a left (1) and right (2) hardmask.

Patterning

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Recommendations for Success

Practical interim solutions exist to support CD and overlay control in the development of DPL and its alternatives for the 32nm node and beyond.

The following recommendations can increase the probability of success in double patterning:

• Implement grating-based overlay technology to gain accuracy and minimize overlay model residuals, so that 3nm overlay targets are achievable. Embed small grating structures in the device area where feasible.

• Implement grating-based 3D-CD scatterometry to measure shape and profi le parameters that support direct feedback of focus and exposure corrections to the litho cell. About 80% of CD variation is due to changes in effective focus and exposure conditions.

• Implement grating-based 2D-CD scatterometry to provide accurate feed-forward and feedback to the etch module. This method is critical for spacer-etch alternatives to DPL.

The above solutions can be a source of accurate process metrics for enabling conjoint DFM and APC strategies. Moreover, if they can be leveraged for yield improvement and cycle-time reduction, standard factory economic models suggest gross margin benefi ts in the tens of millions of dollars per factory per year.

Acknowledgement

© 2006 IEEE. Kevin M. Monahan, Enabling Double Patterning at the 32nm Node. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2006 Conference.

References1. K. Monahan and U. Whitney, “Enabling DFM and APC strategies with advanced process metrics,” Proceedings of SPIE, vol. 6152, 2006.

2. K. Hung, et al., “Scatterometry measurements of line end shortening struc-tures for focus-exposure monitoring,” Proceedings of SPIE, vol. 6152, 2006.

3. Ryan Chia-Jen Chen, et al., “Application of spectroscopic ellipsometry for ultra thin spacer structure,” Proceedings of SPIE, vol. 5375, pp 1381-1374, 2005.

4. V. Vachellerie, “Gate spacer width monitoring study with scatterometry based on spectroscopic ellipsometry,” in Characterization and Metrology for ULSI Technology 2005, pp. 411-420.

Figure 9: Simulation of spectroscopic ellipsometry data used for CD scatterometry. D is varied in 1nm increments showing high sensitivity for spacer metrology, especially in the UV.

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Y=1.0248x - 2.9979R2=0.9902

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SE S

pac

er W

idth

(Å

)

Figure 10: CD scatterometry results plotted against TEM measurements showing an R-squared value of 0.99 over spacer-widths ranging from 4 to 45nm.

Patterning

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