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Immersion Lithography Process and

Control ChallengesIrfan Malik, Viral Hazari, Kevin Monahan, Matt Hankinson, Mike Adel,

Marcus Liesching, Edward Charrier – KLA-Tencor Corporation

Immersion lithography enables higher resolution, but also introduces new defect

mechanisms. Process development, characterization, and ongoing cell qualification

and monitoring must be adjusted to represent the new interactions and dynamics of

immersion technology. It is critical for fabs to implement new defect management

strategies that can handle immersion-specific defects, immersion-related overlay errors,

and new sources of CD variations.

Hyper-NA immersion 193nm (ArF) lithography provides the technological advances required to obtain production yields in 65nm (half-pitch) patterning and to progress towards 45nm. With added technology, such as double patterning and fluids with indices of refraction greater than that of water, immersion lithography (ilitho) is likely to extend to 32nm and beyond.

Immersion optics enable the printing of smaller design rules by increasing the effective numeri-cal aperture (NA) of the imaging lens.1 In the case of water immersion, NAs up to 1.35 have been achieved.2 While this allows printing of smaller features at higher yields with a better process window than equivalent dry systems,3, 4 immersion imaging is a more complex process that presents numerous challenges. Process integration for ilitho is more challenging as it in-volves a tighter coupling of illumination, mask, imaging optics, optomechanics, wafer, materials, dynamics, and process control.

Immersion lithography also introduces several new problems in the areas of image modeling and creation, defectivity, systematic errors, and materials. While some of these problems are understood and contained, solutions are still needed for others in order to reach competitive manufacturing yields.

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Additionally, we discuss control strategies for process develop-ment, litho cell monitoring and production line monitoring, including the identification of best-known methods (BKMs) for mitigating some ilitho problems and possible tools and approaches for unresolved challenges.

Immersion Lithography’s Impact on CD

The higher NA of immersion scanners allows smaller features to be patterned when compared to an equivalent dry system, since a dry system cannot have a NA greater than 1.0. The depth of focus (DoF) is enhanced by immersion relative to equivalent dry imaging, but the process window is still very small. Other effects are also important, including polarization, polarization homogeneity, optical surface effects, birefringence, absorber characteristics, and mask and wafer topography.7, 8

Resist profile control is becoming a significant portion of final critical dimension (CD) control. The smaller patterns are sensitive to any change in sidewall angle (SWA). The great-est effect on SWA is seen for some resists with post-exposure wetting time, suggesting that the photo-acid generator leaches after exposure.9, 10, 11, 12,13 Leaching and water absorption change the n and k of the resist. Leaching of resist components can also create t-topping or defects such as bridging.14, 15 Topcoats generally reduce leaching effects. Thermal variations also affect CD uniformity, with perturbations seen as a “first wafer” effect, or as variations across the wafer.9 Swelling due to water uptake16 may also have global CD impact or cause localized CD variations.17

Fabs are increasingly using metrology tools to monitor CD and sidewall angle (SWA) on production lots, and this be-comes even more important with immersion creating addi-tional mechanisms which impact SWA within a very tight CD

This paper explores the manufacturing challenges related specifically to the integration of ilitho, including:

New materials (fluid, topcoat, resist) which have new physical and chemical interactions

New thermodynamics due to the thermal mass and evaporative cooling of the immersion fluid

New interactions from the edge of the wafer and scanner stage

New defect mechanism sourcesIncreased optical interactions due to hyper-NA

imaging

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Sub-wavelength Lithography Deep Sub-wavelength Lithography

Immersion lithography

Aggressive OPCat <130nm

OPC at 180nm

365nm

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Process window shrinkingon average >30% per node

WavelengthLinewidth

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Figure 1: New technologies must be introduced to continue to enable design rule reduction well below the exposing wavelength. 5

Incoming Wafer

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hardware and wafer

Figure 2: Contributors to immersion litho defectivity.6

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budget. Fabs also make use of the CD and profile measurement capabilities of spectroscopic ellipsometry-based CD (SCD) metrology systems for immersion studies and in-line measure-ment.

Given the additional complexities of the patterning process with immersion and hyper-NA optics, modeling has become an essential part of quickly designing and optimizing the process. Because of the large illumination and imaging angles, vector models are absolutely required. The model must ac-count for:

Source shape and polarizationMask 3D topography effectsMask material characteristicsOptical proximity correction (OPC) and

phase-shift mask (PSM) strategiesPupil effectsResist characteristics

To obtain the largest possible process window and to avoid zero-yielding collapsed windows, every aspect of the process and its components must be modeled and optimized. Lithogra-phers typically use a simulation tool, such as PROLITHTM, to investigate alternatives. Walking a thin tightrope with the use of OPC, lithographers must also make sure that resist features do not print, causing systematic pattern defects.

Optimizing Overlay for Immersion Lithography

Ongoing reduction of design rules continues to squeeze over-lay requirements, and immersion lithography adds additional hurdles, some of which are not yet completely understood. High overlay error is a yield detractor (Figure 3).

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Several components contribute to overlay error on product wafers, including:

Scanner performanceProcess contributions to scanner and metrology errorThermal effects, both global and localOverlay mark designMeasurement tool errorSampling errorsInappropriate modelsUnexplained errors which cannot be corrected

The major scanner manufacturers are shipping scanners with 7-8nm single machine overlay error, which is higher than dry performance.18 While improvements will be made in each suc-cessive scanner generation, the current performance is weaker than that desired by leading fabs and device designs.

Overlay models are used to understand the contributors to overlay error, and to extract corrections which may be fed back to the exposure tool to compensate for the errors. The better the model represents what is happening during exposure, and the more inputs the scanner can take for correctables, the bet-ter the resulting overlay will be. However, not all identifiable components are correctable. Some may be adjustable during a lot exposure (or between lots), some may require a scanner adjustment or calibration, and some will just be the character-istic fingerprint of the scanner (or individual stage). Whatever cannot be explained by an appropriate model will show up as unexplained errors, often called residuals. With immersion, higher residuals have been seen, and data presented in the lit-erature suggest that there are a few ilitho specific areas which may contribute to overlay degradation.

Temperature of the wafer, stage(s), and fluid impact overlay. These may result in a constant error, or may vary over time as components change and equilibrate. First wafer effects have been seen, where the first wafer(s) in a lot exhibits different overlay behavior from the remainder of the lot.9 If a delay slows the progress of a lot, wafers which follow the delay may also exhibit this effect.9 Additionally, test wafers, which are more like first wafers from a lot, may give misleading results which do not represent manufacturing conditions.

In the past, overlay performance across the lot tended to be uniform, showing low wafer-to-wafer variation. This meant that fabs could effectively sample any wafer from the lot and know with a high degree of confidence what any other wafer in the lot looked like. But with the dynamic thermal effects com-ing from immersion, that may no longer be a valid assump-tion, and test wafers will also be less reliable predictors. Some fabs have taken to measuring a larger number of wafers from a lot to better understand and control wafer-to-wafer variation.

The moving mass of water and the air curtain contribute to overlay error on a more local scale. Rapid motion of the wafer and puddle under the lens may create inhomogeneous thermal conditions, resulting in unmodeled overlay error (shown as higher residuals).19 Grid scaling error has been seen to increase as the trailing edge water contact angle decreases, suggesting cooling from evaporation from more hydrophilic surfaces.10

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New and immersion-enhanced defects include particles, bubbles, watermarks (with pattern effects of bridging, line slimming and broadening, and drying stains) and bridging, as shown in figure 4.15, 16, 17, 21, 22, 23, 24, 25

Higher scan speed generally contributes more defects through multiple mechanisms, and this is compounded with contact angle.21, 26, 27 Lower hydrophobicity (smaller receding contact angle) tends to increase the number of observed defects.

The most obvious new source of defects is the immersion fluid and its transportation of particles. Particles can come from multiple sources, such as the wafer (front surface, bevel, back-side), the scanner stage, lens and shower mechanism, or the water itself. Particles may also come from damage resulting from the motion of the water across the edge.

Filtration should remove particles suspended in the immer-sion fluid in most cases, but failure of the system can happen. Periodically, a contaminating event will drive up the count, saturating the filter or leaving contamination in places where it can be picked up again. On-scanner cleaning systems can suppress particles to counts below 0.04/cm2.

Particles can generate several types of defects:

Particles which are in place during exposure block or scatter light (micromasking), creating extra or distorted pattern. These particles may be in the puddle, or in contact with the wafer surface.1�

Particles remaining on the wafer after exposure can act as a developer block, creating extra pattern. They may even remain after development and rinse.

Particles which have been picked up and not filtered are often seen as deposits parallel to the scan direction,2�

or as semicircles at positions where the scan turns (Figure 5).

Bubbles in the water during exposure, particularly those adher-ing to the wafer surface, act as lens elements. This results in extra, missing, or otherwise distorted patterns.28 Most reports identified bubbles as a large problem during early immersion development, but current showerhead designs seem to have eliminated them, at least away from the wafer edge. It is useful to be aware of bubbles as a potential defect type in case of an

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Within the field, scanning-direction magnification error in-creases with receding edge contact angle.10 Both of these errors are correctable, but they must be characterized and monitored. When droplets of water are left behind, evaporative cooling creates localized error.20 Differential overlap of fluid between fields (the puddle extends beyond the current exposure field into fields which have not yet been exposed) makes the thermal history of each field challenging to decompose and model. Fabs use overlay measurement and analysis to model these effects, as described in the section on control strategies.

The boustrophedonic (zig-zag) motion of the scanner (field and grid) has not contributed to overlay error for several generations. However, with immersion, a hydrodynamic20 or fluid drag9 effect has been suggested to contribute to higher residuals.

Water on the wafer backside has also been seen to degrade overlay accuracy, introducing up to 10nm of additional error.20 While measures are taken in the scanner design to avoid back-side water droplets, a failure can have an impact on overlay residuals. Inspection for evidence of backside water is dis-cussed in the defect section. Since defect data analysis tools can represent backside defect data in frontside coordinates, it may be possible to correlate backside inspection results to some overlay residuals. No manufacturing data have been presented on this, so it is not clear if such problems will systematically appear in consistent locations, or whether the spot placements will be random. It does suggest that backside monitoring should be done periodically to ensure that droplets do not end up on the backside, and that the engineer responsible for over-lay should be aware of backside inspection monitoring.

Topcoats are still being investigated by most fabs; their impact on overlay and other issues is explored below.

Immersion-related Defects

Defects arising from immersion lithography are not dramati-cally different from established litho defects, but they do come from different mechanisms, and arrive in different ratios than in dry lithography. Source determination takes well-established approaches, but requires understanding of new mechanisms.

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Bubbles Microbridging

Droplets / Watermarks Small and large particles

Figure 4: Examples of immersion-specific defects.8

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excursion. Next generation fluids may also see the return of bubbles.

Droplets of water which escape the trailing edge of the puddle or are atomized through splashing may dry and leave residue. The escape of water droplets increases with scan speed and with decreasing contact angle of the trailing edge of the puddle. Numerous researchers have proposed various mechanisms by which these create pattern errors, including:16, 17, 21, 22, 23, 24, 28

Leached substances (typically the photo acid generator (PAG) and quencher) from the films are dissolved in the water droplet. When it dries, they precipitate, and act as a developer stop. These are sometimes called drying stains.

Leached substance depletion changes the solubility of the resist. This can result in line slimming, bridging, or t-topping.

Leached substances are concentrated during drying, and migrate back into the resist, changing the resist solubility. This can result in line slimming, bridging, or t-topping.

A droplet on a yet-to-be exposed area may swell the resist stack or leach chemicals, resulting in CD variation, bridging, or slimming.

Absorbed water creates migration of substances within the resist, changing the solubility in the local vicinity.

In addition, some of the transported particles may be water soluble, or some failure within the system may result in the water supply not being as clean as expected.

Pre- and post-exposure rinses have been shown to reduce the number of water spots and particles for some materials prior to development, although they do increase wafer cycle time.25, 40 Post-exposure rinse is most effective when the droplet is still liquid, as the spot may not be as easily removed if it has had the opportunity to dry.17, 24 This means that the conditions for the portion of the wafer exposed early are different from the portions exposed later. It is good to be aware of the exposure path when diagnosing defect problems in general, and for water spots in particular.

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Resist and Topcoat

Topcoats and low-leaching re-sists are being investigated as a solution to some metrology and defect problems. In general, topcoats allow more flexibility in managing the contact angle, which affects numerous aspects of patterning quality. Topcoats chosen for a higher contact angle reduce the number of defects as compared to no top-coat or a topcoat with a lower contact angle.21, 22, 40 Topcoats add cost and time to the pro-cess, but currently provide the best route to improved results. However, adding another film creates the opportunity for

additional defects (in the film and in coating errors), and can create other process challenges. A topcoat may be developer soluble, or may need a separate solvent. A post-exposure rinse on a soluble topcoat can reduce defects.40

The topcoat can also increase stress on the wafer, adding ad-ditional overlay errors.27 On wafers with underlying topogra-phy, a thin topcoat over steps may create pattern deformation, and a thin topcoat may result in scaling error.20 The error can come from both the exposure tool’s alignment system and from the metrology tool, so it is important to understand the process-induced error, and how to optimize each tool’s setup to minimize it.

At this point, most fabs are choosing to use topcoats, although the development of effective low-leaching resists may reduce the need.

The Wafer’s Edge

To maximize useful real estate on the wafer, fabs have been squeezing the edge exclusion farther out to the edge of the wafer, with 1.5mm targeted for the 65nm node.30 However, device yields near the edge are challenging, and may be 50% of yields on the rest of the wafer.31 During resist coating, surface tension in the liquid resist film can cause a physical buildup (or bead) of resist at the wafer’s edge and on the bevel. Once dry, this buildup can create problems for the exposure tool focus for fields near the wafer edge, or it can flake off and create defects. By cleaning the edge and bevel of the wafer, edge bead removal reduces contamination on wafer handing arms and carriers. Ilitho makes this even more important.

Excess BARC, resist, or topcoat film near the edge, on the bevel, or on the backside can flake or be lifted during immersion exposure. Edge engineering is done to reduce defect sources from the wafer edge.32 With immersion, the fluid puddle can sweep up particles from the edge, and even delaminate the films near the edge.25, 40 The force of the water, either from the onrush of the puddle, or from capillary force from the trailing edge, can lift films at the edge and then re-

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The cumulated data enhance the signature Figure 5: The accumulated particles from the stacked maps enhance the signature from the path of the puddle. 9

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Validating models and collecting data for input into design for manufacturing (DFM) tools;

Identifying systematic overlay components, both adjustable and non-adjustable.

The learning during this phase establishes the baseline for production, and creates libraries of known defects and para-metric behaviors. Initially, this knowledge is used to qualify the scanner, while eventually it aids in production monitoring of process window, overlay error, and defectivity. Furthermore, early detection and ongoing management of killer litho defects and process window excursions result in significant cost sav-ings through yield, rework, and immersion litho cell produc-tivity improvements.33

Process development and early yield characterization can be divided into the following categories: bare wafer characteriza-tion; defect process optimization; CD and overlay optimiza-tion; and, process modeling. Each of these is described in further detail below.

Bare Wafer Characterization

Inspection of bare wafers and blanket films plays an important role in ilitho process characterization. The way that films, the scanner, and water interact on blanket wafers can help identify which defects arise from the interaction with water, leading to a better understanding of the immersion process. When using test wafers for ilitho process development, it is important to simulate the actual process and materials as closely as possible, since contamination and water droplet behavior is strongly affected by scan speed and contact angle.

These cases illustrate how high-sensitivity unpatterned inspec-tion systems can be used for ilitho process development:

Water spot formation can be characterized by running both dry and wet, and comparing the inspection results.

Identification of different defect characteristics of exposed and unexposed regions can be accomplished

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deposit flakes elsewhere on the wafer, or on the stage or lens assembly. Anything which is on the edge of the wafer, even on the backside edge in some cases, can deposit onto the working front side.25 Immersion lithography demands greater consis-tency in edge engineering.

These requirements, along with the drive to maximize the useful area of the wafer, necessitate a better understanding of the full wafer, including its edge.30 Until recently, it has been difficult to obtain adequate quantitative information about the edge of the wafer. New tools have been developed to specifi-cally address this requirement. (Please see the paper “Visualizing the Wafer’s Edge” on page 18 for further details.)

A recently introduced edge inspection tool inspects the bevel, apex, and the front and back of the wafer near the edge using several information channels. It can identify whether defects are bumps or divots, and it clearly images flakes, popped films, and many other defect types (Figure 6). Its output is compat-ible with defect analysis tools, so defects found on the edge can be correlated to events found on the front (and back) of wafers by other inspectors.

Control Strategies

Defect, CD, and overlay control approaches are well estab-lished in the lithography cell. These strategies generally also apply to immersion, although fabs are making some modifica-tions and focusing attention in slightly different ways. This section describes existing BKMs and new applications for ilitho process control.

Process Development and Engineering Analysis

One goal of process development is to identify and minimize critical yield issues. This includes:

Finding all important defect types and identifying their sources;

Optimizing the process window and understanding the parameters which reduce it;

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Bubble

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After ExposureBefore Develop

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Figure 6: Wafer edge defects: a) SEM image of blister undergoing delamination; b) Typical bubble, delamination, and debris; c) Delaminated BARC due to peeling by showerhead.

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by running tests with no exposure and exposure but no develop, and comparing the inspection results.

Rapidly establishing a baseline by defect type using unpatterned inspections can help quickly ramp the ilitho cluster, and is useful for process improvement, ongoing monitoring and future process changes.

The post-exposure rinse and development process can be optimized by running wafers through the process without exposure and monitoring how defect levels vary with changes to the process parameters. It is important to be aware of the scanner path across the wafer to determine if there is a correlation between the time droplets are created, and the ability of the post-exposure rinse to clean them off.

Characterization of defect signatures can be related to the scan path.2�, 34

Using bare wafers as a development tool, IMEC employed a particle per wafer pass (PWP) test methodology to determine whether defects came from the resist stack or from immersion process interactions. By running the test on bare wafers and on the stack, and comparing results from the unpatterned and patterned inspectors, defect sources were more clearly pin-pointed.34 (For more information, see the paper “Unpatterned Wafer Inspection for Immersion Lithography Defectivity” on page 33.)

An important component of bare wafer characterization and overall process yield development is Defect Source Analysis (DSA), a tool used to partition process steps to determine the specific process step where a defect appeared. DSA enables more efficient process optimization by allowing the engineer to focus only on current process level defects. DSA works with defects from many inspectors, including those found using backside inspection. As shown in figure 7, DSA can be used to identify defects specific to the immersion process. DSA of blanket film pre-exposure inspection results and post-exposure broadband brightfield inspection results has greatly assisted

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in the identification of pre-exposure defects related to pattern defects.

Short-loop Process Optimization – Defect

Short-loop experiments utilize patterning on blanket or bare wafers to represent the full process step. The three types of short-loop processes include:

Blanket film – for process window and defect optimization, providing the least pattern noise;

Patterned film – for process window, overlay, and defect optimization, most closely simulating the manufacturing process, but with increased noise;

Bare silicon – for investigating immersion defect interactions.

For defect issues, the Photo Cell Monitor (PCM) is a well- established method for qualifying a litho cell, and for ongo-ing production monitoring. It uses a short-loop process to maximize sensitivity to the defects of interest, while suppress-ing noise from other patterned layers. The basic PCM steps include:33

Determine the films to use.Inspect the incoming wafer prior to patterning.Pattern (coat, expose, develop) using either a

test reticle or a device layer reticle. Inspect on a broadband brightfield inspector.Use DSA to identify added defects.35

Track defects by type using automatic defect classification and binning.

Short-loop experiments, combined with PCM, are used to quickly determine which process conditions produce the fewest defects. Comparisons can be made between different film stacks, dry and immersion exposures, or variations in other parameters such as scan speed or post-exposure rinse times.

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Non-Immersion SpecificImmersion &

Non-Immersion Specific

* DSA (defect source analysis) is the method to superimpose multiple layers of defects and track the defect source back into the prior process steps.

* DSA can filter out non-immersion specific defects.

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(b) BARC (c) Resist CoatingDefect

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Figure 7: KlarityTM Defect Source Analysis separates new defects from previously existing defects.

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ling CD and process window now requires use of line profile, commonly represented as SWA. For both CD and overlay, the primary impact of immersion is on uniformity across the field, the wafer, and the lot.

Wafer-to-wafer variation is affected by the first wafer effect and the delay effect. The stability of the first wafer effect within a given litho cell and among litho cells is yet to be determined. If it varies over time, fabs will need to sample more carefully within the lot. However, if the first-wafer effect is stable, then it may be possible to have compensating scanner recipes for the first wafers. The delay effect is more complicated. More work needs to be done to eliminate the delay and to find ways to compensate for any occurring delay.

Across-wafer variations arise from a combination of thermal effects and wetting times. A large portion of the CD and over-lay related yield loss is seen near the wafer edge, suggesting that more attention to the edge may help to identify sources of variation. While overlay models do not account for the grid nonlinearities seen near the edge, some fabs are exploring whether a segmented model (one for edge fields, another for the rest of the wafer) may provide better adjustments, with appropriate spatial sampling.

Increased sampling does impact throughput. Some SCD tools have a CD and SWA measurement time of only two seconds per site, supporting the larger number of spatial measure-ments needed for adequate CD uniformity characterization and control. Also, the lower total uncertainty of SCD measure-ment improves the ability to detect smaller variations in CD nonuniformity.

Localized CD variations and high overlay residuals are also seen elsewhere on the wafer, including field-to-field differences and across-field variations. The immersion-related sources of these localized variations are not yet well understood. In the case of overlay, fabs can now use grating targets which are small enough to be placed in internal scribes and which act as replacements for dummy-fill in device areas (Figure 8). For dry patterning, significant reductions in residuals have been achieved by enhanced intra-field sampling which enables high order field level modeling.36, 37 Because of thermal across-field effects, this may be an enabling requirement for overlay pro-cess control when immersion lithography reaches production.

Thermal variations have also been identified as a source of focus variation, resulting in CD changes across the wafer and fields. It does not make sense to create focus/dose matrices on production wafers, but SCD can estimate the dose and focus of a single measurement.

Evaporative cooling from backside droplets contributes to localized overlay error. If backside inspection is done after patterning, it should be possible to use the backside maps to correlate water spots to overlay errors. Given that droplets are random, the inspection will need to be done on the same wafer. During development, a suspect wafer can be sent to the inspection system for analysis, but during production, the focus must be more on eliminating any backside water.

Composite wafer maps – made by “stacking” data from multi-ple wafers and/or multiple lots – are used for enhancing defect signatures when there are not many defects on individual wafer maps. Field stack composite maps – where all fields from a wafer or set of wafers are combined – have been useful in iden-tifying immersion-related signatures.

For Process Window Qualification (PWQ), a special case of PCM, the focus and dose are varied to determine the pattern-ing limits of the process window and to evaluate the impact of the process window on pattern defect formation. Defect inspection using PWQ will identify patterns in the mask design which fail within the process window, and are not specifically measured on the CD tool. Known weak points established by this inspection become candidates for CD measurement and profile characterization with SCD, and are fed back into DFM.

Fabs typically perform defect process optimization using high-NA broadband brightfield inspectors.29 DSA, compos-ite maps, and spatial signature analysis (SSA) provide a rich toolset for driving the process to minimum defect levels. Once the process has been developed, baselines for defect types are established, which are then used for ongoing litho cell produc-tion monitoring.

Short-loop Process Optimization – CD and OverlayAs described above, CD unifomity and overlay issues related to immersion may arise from several sources, including ther-mal stabilization, leaching of PAG and quencher, and water absorption into the resist and topcoat. While researchers continue to investigate these effects, suppliers are developing resists and tools which mitigate their impact. As each new process is introduced, fabs will be required to characterize and optimize the process window and process capability index (Cpk) for their product mix.

Characterization approaches for overlay and process window are not significantly different than in prior generations, con-sidering that feature sizes are incrementally smaller. Control-

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Controlling CD and process window now

requires use of line profile, or sidewall angle.

For both CD and overlay, the primary impact of

immersion is on uniformity across the field, the

wafer, and the lot.

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Process ModelingLithographers use modeling to develop new processes. Hyper-NA immersion lithography needs accurate modeling treatment to account for OPC, polarization, and mask topog-raphy effects. Predictive model accuracy should co-optimize the OPC rules and the process (Figure 9).

Litho Cell Monitor

The yield optimization strategies learned during process development result in optimized baselines, often based on simplified (single layer or short-loop) processes.

Fabs typically use the final parameters established during development to implement ongoing monitors. The monitors are run each shift for each resist/cup path/scanner combina- tion. They are also used to qualify a new litho cell, or to requalify one after maintenance. The following summarizes the monitors commonly established by fabs, including the required tools:

Unpatterned wafer PWP – simplified process with similar hydrophobicity:

– Monitor and track by defect type and by total defectivity on frontside and backside; – Unpatterned wafer inspectors and defect analysis tools.

Defect PCM – simplified process optimized for sensitivity to defect types:

– Monitor and track by micro defect type and total micro defectivity; – Printed with test reticle; – Broadband brightfield inspectors and defect analysis tools; – Monitor and track macro defects by type for coat (BARC, resist, topcoat) and develop; – Macro wafer inspectors and defect analysis tools.

CD and SWA – simplified process:– Monitor and track specific CD features; – SCD metrology systems.

Process window – simplified process:– Monitor process window determined by CD and SWA for nominal dose, dose range, nominal focus, focus range; – SCD metrology systems with total process window analysis; – Monitor defect process window; – Printed with test or chosen product reticle; – Broadband brightfield inspectors, PWQ application and defect analysis tools.

Overlay – simplified process:– Monitor components of overlay including sub-field monitor; – Overlay tools with extracted overlay error components.

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AIMTM

Overlay TargetµAIMTM

Overlay Target

Figure 8: Micro-graling overlay targets (µAIM) are small enough to be placed at multiple locations within the scanner exposure field.

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Figure 9: Co-optimization of OPC with advanced polarization requires advanced modeling with PROLITH. This example shows the increase in process window of azimuthal polarization over random polarization.3

Once the process is established, fabs monitor CD, SWA, pro-cess windows, and components of overlay error for each process layer and scanner/resist/cup combination. This identifies any weak points which will need specific monitors during produc-tion. Furthermore, as each of these CD and overlay effects is understood on a systematic basis, it may be possible to build appropriate corrections into scanner and track recipes, and into automatic process control (APC). Where the systematic variation does not fully explain the variation, it will be neces-sary for fabs to add the variant cases to sampling plans and fault detection and response. In each case, characterization will establish baseline specs which will then be used for photocell and product line monitoring.

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The cost of defect excursions will be significant. Based on past experience with dry lithography, a typical excursion impacts about 30 lots of wafers. Assuming a fab uses immer-sion on four critical layers, rigorous sample planning analysis estimates that excursions due to new immersion defects can cost a fab about US $31M per year, nearly the cost of a new litho cell. This is on top of excursion costs for defects not spe-cific to immersion, which have been estimated to be US $13M to US $150M annually for defects preventable by PCM.33

Summary

Immersion lithography brings the advantage of higher resolu-tion, but also brings many new challenges. Researchers are working to fully understand ilitho defect mechanisms, and to reduce their frequency through process, material, and tool innovation. Only gross defectivity has been addressed to date; as volume production ramps up further improvements will be made.

This paper explores some of these mechanisms, and identi-fies defect management strategies appropriate for immersion lithography, with particular emphasis on immersion-specific defects.

Edge-sourced defects are a new and significant cause of defects. New tools, combined with established practices, show promise in controlling defects coming from wafer edges.

Immersion overlay performance is weaker than comparable dry overlay. Overlay models do not yet account for the ob-served immersion effects, most of which appear to be affected by the dynamic thermal environment. Greater CD variations have been seen with immersion than with dry lithography; this larger variation presents a yield challenge. The ability to measure feature profile is a useful tool for CD control and to better determine the process window.

Ilitho process development, characterization, and ongoing cell qualification and monitoring are similar to existing practices, but must be adjusted to represent the new interactions and dynamics of immersion. While many of the problems related to immersion lithography are well on the way to being mini-mized, failures of subsystems do happen in real production. Fabs will avoid significant costs if they can detect and respond to these excursions quickly. The learning here will extend to the next immersion generation, when water is replaced with a higher index fluid.

Production Line Monitoring

Immersion litho defect control is most cost-effectively served by PCM for pattern defects, unpatterned wafer PWP for con-tamination, and product line monitor for macro defects. Each should have a baseline established by defect type, and moni-tored against the established limits.

One risk associated with immersion lithography is the poten-tial for scanner stage contamination and the costly side effects which include yield loss and litho cell downtime. If a single wafer arrives with heavy contamination on the top surface or edge, the puddle can move particles to the scanner stage. From that point on, those particles will become an ongoing source of defects until the problem is recognized, and the stage is cleaned. A long cleaning will reduce the immersion litho cell’s productivity. As a result of this risk, it may be most cost effective to carefully inspect a significant number of all wafers coming into immersion cells, including the wafer edge.

The major difference for immersion is that the new non- linearities which result in global and localized errors must be represented by appropriate sampling.

Because of the sensitivity to focus observed with immersion, it is important to monitor focus on production wafers. However, it is not practical to place a focus/dose matrix on production wafers. SCD, through its calculation model, can provide scanner focus and dose information from the feature profile.38, 39 This helps to monitor and provide focus informa-tion on product wafers.

Economic Considerations

Several fabs have observed that, due to the complexities added by immersion, process development and litho cell qualifica-tion are taking longer than comparable dry systems. This means that ramp time for a new process is greater, putting more pressure on getting a new process to market on time. Implementing the yield management and process development optimization strategies outlined in this article are important components for reducing the time and money required to ramp the immersion litho cell.

Depreciation for an immersion litho cell is on the order of US $1M per month, making any downtime very costly. Pro-duction monitoring solutions must be implemented in order to quickly recognize and correct excursions. Stage contamina-tion is a new and significant issue for immersion, and cannot be resolved quickly without repeated requalification. Further-more, the addition of water to the scanning system suggests that production litho cells may have lower reliability than comparable dry systems.

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One risk associated with immersion lithography is the potential for scanner stage contamination. If a single wafer arrives with heavy

contamination on the top surface or edge, the puddle can move particles to the scanner stage, resulting in reduced litho cell productivity.

1�

Acknowledgements

The authors would like to thank Scott Ashkenaz for his assistance with this paper.

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