Vi INSTITUTE OF TECHNOLOGY

VLSI DESIGN LAB MANUAL

NAME:

SIXTH SEMESTERDEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING2013-2014EC 2357: VLSI DESIGN LAB

ANNA UNIVERSITY SYLLABUS

1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers, address decoders, multiplexers), Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted.

2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators, accumulators). Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted.

3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate count, I/O configuration and pin assignment to be taught in this experiment.

4. Generation of configuration/fuse files for all the blocks/codes developed as part of Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the inputs and outputs for each of the blocks must be demonstrated at least on oscilloscopes (logic analyzer preferred).

5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of gain, bandwidth, output impedance and CMRR.

6. Layout of a simple CMOS inverter, parasitic extraction and simulation.

7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation followed by study of synthesis reports.

8. Automatic layout generation followed by post layout extraction and simulation of the circuit studied in Expt. No.7

Note 1. For Expt. 1 to 4 can be carried out using Altera (Quartus) / Xilinx (Alliance) / ACTEL (Libero) tools.Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to be carried out using atleast 0.5u CMOS technology libraries. The S/W tools needed Cadence / MAGMA / Tanner.

@ViIT

For Expt. 1 to 4

Xilinx 13.1 (Alliance) Tool

For Expt. 5 to 8

Cadence Tool

STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD

EXP NODATEVIVAASSIGNMENTREMARKS

Aim:

To study Verilog HDL, Spartan-3E FPGA board and the related software.

Software used:Xilinx 13.1

Device used:Spartan-3E FPGA 250S

Theory:

Introduction to Verilog HDL:

Verilog HDL is one of the Hardware Description Languages (HDL) used to describe a digital system. VHDL is the other one. Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as an the architectural or behavioral level as a set of modules. Modules can either be specified behaviorally or structurally (for a combination of two). A behavioral specification defines the behavior of a digital system (module) using traditional programming language constructs. E.g. if assignment statements. A structural specification expresses the behavior of a digital system (module) as a hierarchical interconnection of sub modules. At the bottom of the hierarchy the components must be primitives or specified behaviorally. Verilog provides the following gate level primitives:

And/nand-logical AND/NANDor/nor-logical OR/NORxor/xnor-logical XOR/XNORbuf/not-buffer/inverterbufif0/notif0-tristate with low enablebufif1/notif1-tristate with high enable

The structure of a module is the following:

Module ();

End module.

The is an identifier that uniquely names the module. The is a list of input, in-out and output ports which are used to connect to other modules. The section specifies data objects as registers, memories and wires as well as procedural constructs such as functions and tasks. The may be initial constructs, always constructs, continuous assignments or instances of modules.OPERATORS:

Bitwise operators: ~(not), &(and), |(or) and ^(xor)Arithmetic: +, -, *, /Unary reduction: &, &&, |, ~|, ^, ~ ^Logical: !, &&, ||Equality: ==, != (0,1)Identity: ===, !== (0,1,x,z)Relational: ,=Logical shift :Conditional: ?:Concatenate: {}Replicate: {{}}

DESIGN FLOW:

Fig. Flow chart of VLSI design flow

DESIGN ENTRY: The designed circuit is specified either by means of a schematic diagram or by using a hardware description language, such as Verilog or VHDL.

SYNTHESIS: The entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA board.

FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify its functional correctness. This simulation does not take into account any timing issues. A test bench is HDL code that allows you to provide a repeatable set of stimuli with clock and input dat for error checking, file input and output and conditional testing.

FITTING: The CAD filter told determines the placement of LEs defined in the netlist into the LEs in the actual FPGA chip. It also chooses routing wires in the chip to make the required connections between specific LEs.

TIMING ANALYSIS: Propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit.

TIMING SIMULATION: The fitted circuit is tested to verify both its functional correctness and timing.

PROGRAMMING AND CONFIGURATION: The designed circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and established the required wiring connections.

SPARTAN-3E FPGA BOARD:

Fig. Functional block diagram

FPGA device used: XC3S500E

The Features of the XC3S500E FPGA board are the following: No. of Logic Blocks: 1564 No. of Macrocells: 10476 Family Type: Spartan-3E Logic Case Style: QFP No. of Pins: 208 No. of Speed Grades: 4 Total RAM Bits: 368640 No. of I/O's: 158 Clock Management: DLL Core Supply Voltage Min: 1.14V Core Supply Voltage Max: 1.26V Operating Frequency Max: 240MHz MSL: MSL 3 - 168 hours SVHC: No SVHC (19-Dec-2012) Core Supply Voltage Range: 1.14V to 1.26V Frequency: 572MHz I/O Interface Standard: HSTL, LVCMOS, LVTTL, SSTL I/O Output Drive: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V Logic IC Base Number: 3S500 Logic IC Function: FPGA No. of Gates: 500000 Operating Temperature Max: 85C Operating Temperature Min: -40C Operating Temperature Range: -40C to +85C Programmable Logic Type: FPGA Termination Type: SMD

POCEDURE OF XILINX 13.1 SOFTWARE:

1. Start Xilinx ISE 13.1, click on CREATE A NEW PROJECT and then click on Next.2. Select youre working directory, give the name of the project, then click on NEXT.3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade (4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language (Verilog) from the available device list, and then click NEXT and click FINISH.4. Write the HDL code and be careful to give the entity name the same as project name. After writing the code save the file and click on Synthesis XST.5. If the HDL code is error free a green check mark will be shown on the synthesis XST.6. Select simulation then double click on Simulate Behavioral Model (here we can change the level of abstraction. i.e. structural/behavioral/dataflow/switch level)7. If there is zero error a new window will be shown. Apply the desired input as 1s and 0s and check whether the outputs are correct or not in the output waveform.8. Expand the user constraints n the processes for source window and double click Assign package pins (with ISE 13.1 web pack is called I/O floor plan presynthesis). This is where you tell Xilinx which pins on Spartan 3E will be used. 9. In the Design object list I/O pins window type the pin numbers in the following pin assignments under the heading LOC. This action will create a .UCF file for the top_level_struct file and will contain the pin assignments for the Spartan-3E.10. Make sure that the top_level_struct file is selected in the sources window.11. Expand the Synthesis-XST in the Processes window and then double click it. This action will check the syntax of the source code for top_level_struct and convert the source code into a netlist of gates. A synthesis report will also be produced. When the synthesis is finished, green check marks should be displayed indicating that top_level_struct has compiled successfully.12. Expand the Implement design process and double click on it. This is where the netlist is translated, mapped, placed and routed for the logic circuits of the Spartan-3E FPGA. After this process has been run, green check mark should be displayed.13. Expand the Generate Programming file process and double click it. This process createsA bit file that is used to program the Spartan-3E chip. Again, after this process is finished, green check mark should be shown.14. Expand the Implement design and double click on Generate programming file. 15. Right click on the depiction of the Spartan-3E chip and select program. If the download was successful, the message Program succeeded will be displayed.

RESULT:

SIMULATION AND SYTHESIS OF HALF ADDER AND FULL ADDER

EXP. NO.DATEVIVAASSIGNMENTREMARKS

Aim:To simulate and synthesis of half adder and full adder in behavior and structural model of Verilog HDL and to perform timing and power analysis.

Software used:]

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program:

Half adder in Behavioral model:

module ha_behav (a, b, sum, cout);Input a, b;Output sum, cout;Assign sum = a ^ b;Assign cout = a & b;endmodule

Half adder in Structural model:

module ha_struct (x, y, sum, co);Input x, y;Output sum, co;xor (sum, x, y);and (co, x, y)

Full adder in Behavioral model:

module fa_behav (a, b, cin, sum, cout);Input a, b, cin;output sum, cout;Assign sum = a ^ b ^ c;Assign cout = (a & b) | (b & cin) | (a & cin);Endmodule

Full adder in Structural model:

module fa_struct (x, y, ci, sum, co);Input x, y, ci;Output sum, co;Wire im1, im2, im3;xor (sum, x, y, ci);and (im1, x, y);and (im2, y, ci);and (im3, ci, x);or (co, im1,im2,im3);endmodule

Observation:

Half adder:

RTL view:

Flow summary:

Total logic elements -2/33,216 [