Xilinx Training

Xilinx Analog Mixed Signal SolutionHDL Design Flow

Note: Agile Mixed Signal is Now Analog Mixed Signal

Welcome

If you are a FPGA designer, this module introduces the HDL flow for Xilinx Agile Mixed Signal solutions

This module will list some key features of the XADC core that are enabled by Xilinx Agile Mixed Signal solutions

To Learn More About Xilinx Agile Mixed Signal

Related Videos– What is the Xilinx Agile Mixed Signal Solution?

• For beginners and enthusiasts

– Xilinx AMS EDK Design Flow• For embedded designers who want to become familiar with the EDK flow

– Xilinx AMS XADC Evaluation• For designers who want to know how the XADC interface can be evaluated for

their mixed signal application

1. Evaluate 2. Instantiate 3. Simulate

Implementing XADC in your Design

1. Evaluate

• XADC evaluation kit is bundled with all 7 series TDPs

• Choose required XADC settings and evaluate

2. Instantiate

• Set attributes based on evaluation and connect I/O

• Customize analog interface using XADC Wizard

3. Simulate

• Simulate HW (XADC & FPGA logic) using analog stimulus file

• Use HW in the loop with ISim to verify prototype

Edit Settings

Evaluating the XADC

KC705

USB

123.456

Optional External Instrument(e.g. signal generator)

Resources (DACs) for basic testing and connectors for external instruments

#1

Ribbon cable connectionto “analog header” on KC705

National Instruments LabView GUI• XADC settings

• ADC data collection and analysis

1 – Evaluate XADC Settings

XADC Evaluation Card

XADC LogiCORE IP

Typically customizable

Fully tested, documented, and supported by Xilinx

Unlicensed and provided for free with Xilinx software

VHDL and Verilog flow support for several EDA tools

Page 6

XADC LogiCORE IP

XADC block I/O

XADC attributes initialize the XADC registers (settings)

XADC registers / settings can also be accessed at any time via the FPGA fabric

MU

X

7 Series XADC

On-ChipSensors

ADC 1

ADC 2T/H

T/H

1.25V

Re

gis

ters

Instantiating the XADC

Configure the XADC initialize registers by

setting attributes

Connect up the XADC I/O

2 – Instantiate the XADC

XADC instantiation in language templates

XADC and CORE Generator Tool Integration

A GUI allows central access to LogiCORE™ IP products, as well as– Data sheets– Customizable parameters

The CORE Generator tool is available as a standalone application– Launched via Programs > Xilinx ISE Design Suite > ISE Design Tools >

Tools > CORE Generator

Can be launched from the ISE® Project Navigator and PlanAhead™ software tools

Interfaces with design entry tools– Creates instantiation templates for HDL-based designs

Page 9

Running the CORE Generator Tool

From the Project Navigator– Select Project > New Source– Select IP (CORE Generator &

Architecture Wizard), enter a filename, and click Next

– Expand FPGA Features and Design > XADC and select XADC Wizard

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Running the CORE Generator Tool (continued)

From the PlanAhead software – Select Project Manager >

IP Catalog– In the IP Catalog window,

expand FPGA Features and Design > XADC and select XADC Wizard

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XADC Wizard Simplifies HDL Instantiation

Connect XADC I/O andset attributes using GUI

XADC Wizard User GuideClick Generate

to generate core

Adding the XADC Core to the FPGA Design

XCO file associated to project

Customize and regenerate the core

VHO or VEO templates for HDL instantiation

Adding the instantiation templates to HDL

XCO file included in design hierarchy

XADC Implementation

Code autonomous logic to read and write to the XADC via the Dynamic Reconfiguration Port (DRP)

Refer to the 7 Series XADC User Guide (UG480) to determine the different operating modes of XADC and DRP timing information

Xilinx tools provide a graphical view of how XADC is used in FPGA designs

UG480

Simulation and Verification

Text file contains analog information (sensors, external voltages, etc.) thatcan be introduced into the simulation by UNISIM

3 – Simulate XADC (Analog) and Digital

Associating Analog Stimulus to XADC Model

Associating analog stimulus file as attribute in XADC HDL instantiation

Associating analog stimulus file to XADC model in XADC CORE Generator Wizard

Simulation Example

UNISIM

HDLTest-

bench

Stimulus File Example

Analog information readin directly by model not the testbench

Download Example with UG480: ug480_7Series_XADC.zip

Summary

1. Evaluate the XADC for performance and settings– XADC Evaluation Kit is bundled with all 7 series TDPs– Pick required XADC settings (attributes) and evaluate

performance

2. Implement the XADC core in your HDL design flow– CORE generator tool’s XADC Wizard simplifies

configuration• Customizes the core and generates files for instantiation and

simulation• Refer to the XADC Wizard User Guide (UG772) to configure the core.• Generate XCO file that can be instantiated in your HDL

– Write HDL code to perform autonomous operation on XADC for sensing the analog input• Refer to the XADC User Guide (UG480) for more information on XADC operating modes and timing

3. Simulate the XADC in an HDL simulator– UNISIM (Verilog and VHDL) model for XADC– Support for analog test vectors using an analog stimulus file

Where Can I Learn More?

Learn more at www.xilinx.com/AMS– Agile Mixed Signal white paper (WP392)– XADC User Guide (UG480)– Watch more videos of Xilinx AMS

Visit www.xilinx.com/innovation/7-series-fpgas.htm– Application examples – New 7 series documentation

Xilinx training courses– www.xilinx.com/training

• Xilinx tools and FPGA architecture courses• Hardware description language courses• 7 series design courses• Basic FPGA architecture, basic HDL coding techniques, and other free

Videos

Page 19

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