wp3: integration of nanophotonics into c-si thin-film solar cells final review – m36 23 october...
TRANSCRIPT
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WP3: Integration of nanophotonics into c-Si thin-film solar cells Final review – M36
23 October 2015, La Defense, Paris
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Outline
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1. Introduction
2. Materials and layer transfer2.1. Thin c-Si materials & properties 2.2. Transfer processes
3. Solar cells3.1. PolySilicon solar cells3.2. Epi-PECVD3.3. Epifoils3.4. Epifree
4. Summary & outlook
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WP goals
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o Pattern with various techniques o of litho and etcho periodic and non-periodic
o Characterise the patternso Find how to passivate them
WP2
o Model various nanopatterned structures and extract their Jsc
o Give guidelines of optimal structures
o Gather reliable data for modelso Define benchmark structures
WP1
o Fabricate thin c-Si filmso Integrate nanopatterns into solar cells
and reach record Jsc valueso Demonstrate upscalability
WP3o Evaluate industrialiability of
nanopatterningo Evaluate their costs and footprinto Disseminate results and protect IP
WP4
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Reminder WP1 & WP2
But challenging passivation of nanopatterned structures, WP2
Pseudo disorder is good High short circuit current
Good news from WP1
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o Task 3.1 Production of thin c-Si absorber layerso Task 3.2 Fabrication of thin c-Si cells with one-side nanopatternso Task 3.3 Fabrication of record c-Si cells with optimal nanopatternso Task 3.4 Large-area nano-patterned solar cells
WP3
WP tasks and people to achieve them
Imec Ounsi, Christos, Islam, Xingyu, Twan, Kris, Jonathan, Hari, Valérie
INL Loic, Regis, Alain, Christian, Emmanuel, Romain, Mustapha
LPICM Romain, Skander, Wanghua, Gennaro, Ismael, Martin, Pere
Obducat Kidong, Babak
Chalmers Vladimir, Ines, Kristof, Sascha
Total Paul
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WP3 strategy for record cells
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Get a “flavor”
First optimisation
Focus for record
D3.1
D3.2
D3.3
D3.4, D3.5
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Objectives
Cell technology (Si thickness)
Voc(mV)
FF(%)
Jsc(mA/cm2)
Efficiency*(%)
Epifree (1µm) 600 78 30 14.0
PolySi (3µm) 580 77 30 13.4
Epi-PECVD Si films (4-6 µm) 650 78 32 16.2
Epifoils (40µm) 650 78 40 21.3
* Expected efficiencies at the end of the project
Achieved (target) model
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0 0.1 0.2 0.3 0.4 0.5 0.60
5
10
15
20
Voltage (V)
Current den-sity (mA/cm2)
unpatterned
2D PC
The integration challenge:Increasing Jsc without losing Voc and FF
JscmA/cm2
VocmV
FF%
Eff.%
Flat 12.8 548 66 4.6
2D PC 15.4 403 56 3.5
V. Depauw, IEEE J PV 2014
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2. Materials & layer transfer
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Epifree – 1 µm• Some defects: creases (bumps) or some cracks• Possible development: thickening by epi growth
PolySi – 3 µm• Rough (200-500 nm RMS)• No development possible – using current stock
Epifoil – 40 µm• Issues of cracks when dicing into smaller pieces• Solution found: pick and place on glass when possible
Epi – PECVD @ 175 °C • Thicknesses in the range of 2 – 6 µm• Very smooth RMS of 2 – 4 nm
PECVD Epi-Si
C-Si wafer
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Material Process T Pros Cons
Epifree (1µm) 1000 Very interesting optics Too thin ?
PolySi (3µm) 1000No transfer No waferHCL
QualityWet not possible
Epi-PECVD (4-6 µm) 200 Low TH incorporation Current Dep. rate
Epifoils (40µm) 1000 Hig qualityHigh rate
2.1 Thin c-Si Materials & properties
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2.2. Layer-transfer processes
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2.2 Layer-transfer processes= detachment + bonding
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weak layer
Formation of a weak layer
in Si wafer
carrier
Bonding to foreign
substrate
Lift-offThin-film c-Si
or vice-versa
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A bonding “tool box”
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Technique Strength Principle Pros Cons
Anodic Very highReaction
between glass and Si
(high V / T)
Easy post-processing
Strong constraints on materials (e.g.
flatness)
Silicone Low Print glue and cure
Transparent, releases
stress
Interferes with cell
processing
Kapton tape Low Sticky substrate
Quick and easy Weak bond
High-temperature
glueHigh Spin glue and
cureHigh T,
conductiveDefected
bonds
Ormostamp High Spin glue and cure
Transparent, resistant
New developmentPeel off issues
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DetachmentPorous silicon
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1- Etching
1130°C
2- Annealing
High-T epitaxial Si
3- Film growthPSi
EpifreeEpifoil
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New method to produce a fragile interfacehydrogen-rich layer
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Accumulation of H at interface
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No detachment @ 400 ˚C
Detachment @ 300 ˚C
5 nm
substrate
epi
substrate
epi
5 nm
TEM -J.L. Maurice, LPICM
Epi-PECVD with porous interface
Correlation between epi-PECVD/c-Si interface porosity and possibility of lift-off
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epi-PECVD
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1.5 µm epitaxial silicon bonded to Glass
Epi-Si
Glass
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Application of the tool box on films
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Epifree Epifoil PECVD-Si
Anodic Ok, as long as polished, standard method
Ok, as long as polished
Ok, as long as low roughness
SiliconeNot ok, challenging Ok,
standard methodOk for bonding, lift off not successful
Kapton Ok, quality of lifted off layer needs to be kept
Not tested Ok, Transfer needs more development
HT glueNot ok Not tested
Not ok, further development needed
Ormostamp Not tested Not tested Not ok
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New materials: a-SiOx: and µc-SiOx:H combine: thermal stability, AR coating & high conductivity
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Influence of Anodic bonding on passivation quality
Anodic bonding 250 C @1000V
Strong degradation for a-Si:H
Stable for a-SiOx
Ag
SubstrateAl
c-Si / p-type
i/n+ a-Si / ITO
µc-SiOxAl
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3 . So l ar C e l l s
3 .1 p o ly S i l i co n 3 .2 ep i -PEC VD 3 .3 ep i fo i l s3 .4 ep i - f ree
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Limitations from practical issues
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Foil delamination at end of NILStrong adhesion between stamp and resist Some epifree stacks or PECVD-Si delaminate
Difficult optimization of wet-NILNIL resist has lower adhesion to sample surface than
hardmasks Reproducibility is needed for reaching high ff
Challenging process of nanopatterned epifoils IBC-cells require samples larger than NIL or HCL Even more complex detachment and processing
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3.1. Poly-crystalline SiA rough film of 3-5 µm
Ag
Alumina substrate
p++ c-Sic-Si
a-Si/ITOAl
5 cm x 5 cm
alumina
1.1 cm x 1.1 cm cell
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PolySi is the perfect vehicle for HCL
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HCLNIL
~ 75% area nanopatterned 100 % area nanopatterned
270 nm beads
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A good vehicle for HCL but the most limited in effi ciency
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Higher absorption converted into higher Jsc
But Voc and FF are limited by polycrystalline nature
Texture Jsc
[mA/cm2]Voc
[mV]FF[%]
η[%]
Flat 10.1 456 57 2.6NIL 14.2 343 46 2.2HCL 16.3 403 46 3
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3.2 Epi-PECVDA low temperature approach
PECVD Epi-Si
C-Si wafer
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Flow chart for the fabricati on of nanostructured epi-PECVD Si solar cells
Cells on wafer: the easy test bench for material and patterning
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First nanopatterned epi-PECVDEpi-PECVD LPICM NIL OBDUCAT wet etch IMEC Cell process LPICM
VOC [mV] Jsc [mA/cm2] FF [%]
Eff[%]
Ref. Flat 490 15.9 74.9 5.9
NIL pattern& wet etch 450 16 75 5.4
► Improvement paths:■ Optimize etching (dry and wet)■ New materials
Wet etch to be improved
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emitter etching Voc (mV) Jsc(mA cm-2) FF Eff. (%)
n-a-Siflat 492 15.9 74.9 5.9
dry 394 6.95 57.5 1.5
wet 501 19.93 79.2 7.8
Dry etching 140418-1@6
Wet etching 140418-1@4
Ref. without nanopatterns 140415-1@3
c-Si (p++)
n-a-Si
Al
ITOAg
epi 4 μmi-a-Si
Flat vs nanopatterns (NIL+ etching)
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Detachment (450 ˚C; 5 min)
2 µm
Voc (mV)
Jsc
(mA cm-2) FF (%)
Eff.(%)
JV EQE
4 µm epi-Si on glass 342 19,9 18,8 56.2 3.8
(d)
Epi-Si
Al
ITO
Glass
Transferred epi-Si solar cells
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3.3 EpifoilA very-high quality “thick” film
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Ti/Al
0.5 um
37 umSilicone
glass
ITO
c-Si:n (epifoil)
i/p+ aSi
Cu
i/n+ aSiITOCu
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A solar cell processed at module level, bonded with silicone
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HJ-IBC cells are challenging to pattern first go for two-side contact cells
Ti/Al
Siliconeglass
ITO
c-Si:n (epifoil)
i/p+ aSi
Cu
i/n+ aSiITOCu
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Two-side contacted epifoilsEpitaxial foils on parent substrates
Front side processing:1. Texturing2. Passivation/FSF3. ARC4. Metallization
Ti/Pd/Ag
c-Si:n (epifoil)
c-Si (Parent substrate)
porous Si layer
Antireflective coating(nano-)textured surface
Front Surface Field
Bonding and detachmentwith silicone glue
Back side processing:1. Emitter2. Dielectric metal stack
Dicing
Silicone
Ti/Pd/Agglass
c-Si:n (epifoil)
glass
i/p+ aSi ITO
i/p+ aSi
Ti/Pd/Ag
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Nanopatterned Epifoil cells
224 nm 420 nm
544 nm
Sample Jsc*
[mA/cm2]Voc
[mV]FF
[%]Eta[%]
Deep Dry NIL 22.6 (30) 618 61 8.6
Medium Dry NIL 25.2 (30.8) 635 73 11.8
Shallow Dry NIL 24.7 (30.9) 670 76 12.5
Wet NIL 25.2 (32.6) 634 72 11.5
Random Pyramids 26.1 (32.6) 675 75 13.2
580 nm
3 um
Decrease in Voc, ff and efficiency
Dec
reas
e in
Voc
,ff a
nd e
ffici
ency
*Current in the parenthesis calculated by integrating the measured EQE
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300 400 500 600 700 800 900 1000 1100 12000
102030405060708090
100
Random Pyramids Dry NILWet-NIL r2d03c03R02D05C04_3 R2D10c09
Wavelength (nm)
EQE,
A (%
)Nanopatterned Epifoil cells:Improved light trapping1) Better UV response for RP 2) Better performance for Wet NIL because of a
better optical vs electrical trade off3) Better light trapping for nanopatterning
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2
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Epifoils into IBC solar cells?Too challenging in this time frame
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Unsuccessful BSF passivation due to
silicone-resist interaction
Shorter term:
Two-side contacted w-NIL: 11.5%
IBC Dec 2014 w-NIL 6.8%
IBC April 2015 w-NIL 5.6%
Free-standing two-side contacted
Longer term: IBC!
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3.4 EpifreeThe thinnest crystalline-silicon cell
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5 cm x 5 cm glass substrate
1 cm x 1 cm cell
Al
Ag a-Si/ITO
c-Si
Substrate
1 µm
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First integration in epifreeLIL and dry-etching
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Higher absorptance and better trapping
Damage of electrical properties by
dry-etching
Strong losses in non-active layers
Ag
SubstrateAl
Alc-Si / p-type
i/n+ a-Si / ITO
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Integrati on of µc-SiOx:H as rear buff erOpti mised NIL with µc-SiOx:H reaches 6.5%
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6.55%
3.98 %
NIL
µc-SiOx:H
Ag
SubstrateAl
c-Si / p-type
i/n+ a-Si / ITO
µc-SiOxAl
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µc-SiOx:H improved rear-side and new NIL stamp improved absorptance
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µc-SiOx:H
Optimised NIL
Flat reference ucSiOx 800nm NIL
ucSiOx flat
ucSiOx 680nm NILoptimised
WP1
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Last epifree batchHCL or NIL and optimised emitter
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Ag
SubstrateAl
c-Si / p-type
i/n+ a-Si / ITO
µc-SiOxAl
Improved emitter2 different thicknesses
HCL vs. NIL+ try wet-NIL
Rear passivation
Dry-NIL Dry-HCL Wet-NIL (failed)
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J-V performancesGood reproducibility and the record cell
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Jsc to be certified
µc-SiOx:H
Wet-NIL
dry-NIL
dry-HCL 9.58 %
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Impact of thinner emitter is clear at spectral response
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300 400 500 600 700 800 900 1000 1100 12000
10
20
30
40
50
60
70
80
90
100
Wavelength (nm)
EQE,
1--R
(%)
.... but EQE is higher at front
Similar reflectance...
Dry-HCL thin emitterDry-HCL thick emitter
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0 0.1 0.2 0.3 0.4 0.5 0.60
5
10
15
20
25
Voltage (V)
Current density (mA/cm2)
Successful integration into 1.1 µm c-Siepifreeback side passivati on patt erning emitt er and passivati on
~ modeled max
Softer slopes + µc-SiOx:H rear buffer
Disorder + thinner front a-Si:H
9.6%
3.5%
2D PC
Unpatterned
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Summary on solar cells and effi ciencies
Cell technology (Si thickness)
Voc(mV)
FF(%)
Jsc(mA/cm2)
Efficiency*(%)
Epifree (1µm) 600 78 21 (30) 23 9.6 (14)
PolySi (3µm) 580 77 16.3 (30) 13.4
Epi-PECVD Si films (4-6 µm) 650 78 20* (32) 30 16.2
Epifoils (40µm) 650 78 29 (40) 37-39 21.3
* Expected efficiencies achievable at the end of the project
Achieved (target) model
* Non patterned
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46
Summary on Materials and cell effi ciencies
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Effici
ency
(%)
Epifr
ee
Epi-P
ECVD
Epifoil
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Higlight (1)
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Developped strong know how on epi-PECVD interface
Correlation between epi-PECVD/c-Si interface porosity and lift-off
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Highlight (2)
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a-SiOx:H and µc-SiOx:H layers combine:- good passivation, high thermal stability,- tunable refractive index- high conductivity
Passivation preserved after anodic bonding
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49
Highlight (3)
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Dry NIL 29.2 mA/cm2
Random pyramids 24.1 mA/cm2
Epifoil: successful integration !
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Highlight (4)
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Record efficiency for ultrathin nanopatterned epifree solar cell
0 0.1 0.2 0.3 0.4 0.5 0.60
5
10
15
20
25
Voltage (V)
9.6%
Cu
rre
nt d
en
sity
(m
A/c
m2 )
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51
Outlook
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Integration of a-SiOx:H and µc-SiOx:H materials in current c-Si solar cells
Further work on epi-PECVD, in particular aiming at higher deposition rates
Continue the development of IBC epifoil solar cells
Epi-PECVD transfer know how for PV and micro-electronics
… and much more to come
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nanophotonics for ultra-thin crystalline silicon photovoltaics
This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement No 309127
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First round of patterned cells: Current status
Cell technology (Si thickness)
Voc(mV)
FF(%)
Jsc(mA/cm2)
Efficiency*(%)
Epifree (1µm) 600 78 16 (30, 25) 24 14.0
PolySi (3µm) 580 77 16.3 (30, 30) 13.4
Epi-PECVD Si films (4-6 µm) 650 78 20 (32, 31) 35 16.2
Epifoils (40µm) 650 78 29 (40, 39) 39 21.3
* Expected efficiencies achievable at the end of the project
Achieved (target, go/no-go) model
MS6 (Month 21). Decision on patterning techniques for each cell techno
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54© IMEC 2012
Surface passivation is critical
V. DEPAUW - SPIE PHOTONICS BRUSSELS 2012
c-Si - τ bulk W
S (Surf. Recom. Velocity)
1/τeff = 1/τbulk + 2S/W
S= 50 cm/s
10 cm/s
5 cm/s
1 µm
10 µ
mW
=10
0 µm
Thin mono c-Si dominated by surface
Nano and micro c-Si
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