wistron la14 rsb schematics

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

LA14 SBBLOCK DIAGRAM

A3

1 52Thursday, May 07, 2009

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A3


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A3


Mobile CPU

CantigaHOST BUS 667/800/[email protected]

DDR2 DIMM1667/800 MHz

667/800MHz

667/800MHz

ICH9M

X4 DMI400MHz C-Link0

ODD SATA

SATAHDD SATA

SATA

Camera(USB)

USB4 Port

USB

KBCKBC773L

INT.KB

TouchPad

WinbondW25X1616M Bits

BIOS

DEBUGCONN.

LPC

LPC BUS

a/b/g/nMini CardPCIex1Kedron

AR8132

LANAtheros TXFM RJ45

MS/MS Pro/xD/MMC/SD5 in 1

CRT

LCD

CLK GEN.ICS 9LPRS365BKLFT (71.09365.A03) THERMAL EMC2102

CodecCX20561

MIC In

G1454OP AMP

AZALIA

INT.SPKR

Line Out(NO SPDIF)

AGTL+ CPU I/FDDR Memory I/F

INTEGRATED GRAHPICSLVDS, CRT I/F

6 PCIe portsPCI/PCI BRIDGE

ACPI 2.04 SATA

12 USB 2.0/1.1 ports

667/800 MHz

CardReaderRealtekRTS5159

USB

ETHERNET (10/100/1000MbE)High Definition Audio

LPC I/FSerial Peripheral I/F

Matrix Storage Technology(DO)Active Managemnet Technology(DO)

Penryn 4793

4, 5

6,7,8,9,10,11

16

1718

19

12,13,14,15

32

21

20

2330

24 25 25

30

31

26

27

28

28

28

33

35 33

34 34

PCIex1

Project code: 91.4BW01.001PCB P/N : 48.4BW01.01MREVISION : SA

TOP

VCC

S

S

GND

BOTTOM

PCB STACKUP

DCBATOUT

SYSTEM DC/DC

1D8V_S3

INPUTS

SYSTEM DC/DCTPS51125

5V_S5

42

OUTPUTS

RT9026DDR_VREF_S0

43

3D3V_S5

1D8V_S3

44

DCBATOUT1D05V_S0

INPUTS OUTPUTS

TPS51124

DDR_VREF_S3

RT9018A

1D8V_S3 1D5V_S0

43

46

41

VCC_CORE_S00.35~1.5V

OUTPUTS

CPU DC/DC

INPUTS

DCBATOUT

CHARGER

OUTPUTSINPUTS

BT+

DCBATOUTDCBATOUT

BQ24745

ISL6266A

DDR2 DIMM2

18

Power Board

36

SILEGO SLG8SP513VTR(71.08513.003)

AR8114

LA14 Block Diagram ?

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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LA14 SBReference

A3


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LA14 SBReference

A3


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LA14 SBReference

A3


1 = TLS cipher suite with confidentiality (default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

Cantiga chipset and ICH9M I/O controllerHub strapping configuration

page 218

Intel Management engine Crypto strap

CFG6

Reserved This signal should not be pulled high.

GPIO49

SPI_MOSI

GPIO33/HDA_DOCK_EN#

SATALED#

SPKR

TP3

CFG9

00 = Reserve

(Default)CFG16

0 = LFP Disabled (Default)Local Flat Panel(LFP) Present

CFG19

CFG20

SDVO_CTRLDATA

11 = Disabled (default)

1 = Dynamic ODT Enabled0 = Dynamic ODT Disabled

1= LFP Card Present; PCIE disabledL_DDC_DATA

FSB Dynamic ODT

DMI Lane Reversal

NOTE:

PCIE config2 bit2,Rising Edge of PWROK.

GNT2#/GPIO53

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

Top-Block Swap Override.Rising Edge of PWROK.

GNT0#:SPI_CS1#/GPIO58

0 = Reverse Lanes,15->0,14->1 ect..

Boot BIOS Destination Selection 0:1.Rising Edge of PWROK.

ESI compatible mode is for server platforms only.This signal should not be pulled low for desttopand mobile.

HDA_SDOUT

HDA_SYNC

GNT3#/GPIO55

Signal

Sampled low:Top-Block Swap mode(inverts A16 forall cycles targeting FWH BIOS space).Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

This signal has a weak internal pull-up.

XOR Chain Entrance/PCIE Port Config1 bit1,Rising Edge of PWROK

1= Normal operation(Default):Lane Numbered in order

Allows entrance to XOR Chain testing when TP3pulled low.When TP3 not pulled low at rising edgeof PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h). This signal has weak internal pull-down

PCIE config1 bit0,Rising Edge of PWROK.

GPIO20

Usage/When Sampled

ESI Strap (Server Only)Rising Edge of PWROK

Comment

CFG[13:12]

0 = Only Digital Display Port or PCIE is operational (Default)1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)1 = SDVO Card Present

DMI Termination Voltage,Rising Edge of PWROK.

The signal is required to be low for desktopapplications and required to be high formobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)

CFG[2:0]

CFG[4:3]CFG8CFG[15:14]CFG[18:17]

CFG5

Pin Name

011 = FSB667FSB Frequency Select

0 = DMI x2

others = Reserved

Reserved

(Default)1 = DMI x4

Strap Description

DMI x2 Select

iTPM Host Interface

Configuration

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)

This signal has a weak internal pull-down.

GNT1#/GPIO51

Integrated TPM Enable,Rising Edge of CLPWROK

Sample low: the Integrated TPM will be disabled.Sample high: the MCH TPM enable strap is sampledlow and the TPM Disable bit is clear, theIntegrated TPM will be enable.

Flash Descriptor Security Override StrapRising Edge of PWROK

PCI Express Lane Reversal. Rising Edgeof PWROK.No Reboot.Rising Edge of PWROK.

XOR Chain Entrance.Rising Edge of PWROK.

This signal should not be pull low unless using XOR Chain testing.

If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timersystem reboot feature). The status is readable via the NO REBOOT bit.

ICH9M Functional Strap Definitions

Controllable via Boot BIOS Destination bit(Config Registers:Offset 3410h:bit 11:10).GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

page 92

Sampled low:the Flash Descriptor Security will beoverridden. If high,the security measures will be in effect.This should only be enabled in manufacturingenvironments using an external pull-up resister.

SDVO Present

Montevina Platform Design guide 22339 0.5

LAN Atheros AR8114A

USB Table

LANE2

LANE1

MiniCard WLAN

PCIE Routing

010 = FSB800

000 = FSB1067

LANE3

ICH9 EDS 642879 Rev.1.5

ICH9M

BATTERY

KBC

ThermalEMC2102

BAT_SCL

SMBC_ICH 9LPRS365BKLFT

DDR

CFG7

SMBus

ICH9 EDS 642879 Rev.1.5

ICH9M Integrated Pull-upand Pull-down Resistors

SIGNAL Resistor Type/Value

HDA_BIT_CLK

HDA_RST#HDA_SDIN[3:0]HDA_SDOUT

HDA_SYNC

GNT[3:0]#/GPIO[55,53,51]

GPIO[20]

LDA[3:0]#/FHW[3:0]#

LDRQ[0]

PME#PWRBTN#SATALED#

LAN_RXD[2:0]

LDRQ[1]/GPIO23

TP[3]

SPKR

GLAN_DOCK#

SPI_CS1#/GPIO58/CLGPIO6

USB[11:0][P,N]

CL_RST0#

SPI_MOSI

SPI_MISO

TACH_[3:0]

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 15K

The pull-up or pull-down active when configured for nativeGLAN_DOCK# functionality and determined by LAN controller

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20KPULL-UP 15K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20KPULL-UP 20K

PULL-DOWN 20KPULL-DOWN 20KPULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

GPIO[49]

HDA_DOCK_EN#/GPIO33

CL_DATA[1:0]CL_CLK[1:0]

DPRSLPVR/GPIO16ENERGY_DETECT

PULL-DOWN 20KPULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20K

0= The iTPM Host Interface is enabled(Note2)1=The iTPM Host Interface is disalbed(default)

PCIE Graphics Lane

CFG10 PCIE Loopback enable0 = Enable (Note 3)1= Disabled (default)

XOR/ALL

1 = Reverse LanesDMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Normal operation(Default): Lane Numbered in Order

Digital Display Port(SDVO/DP/iHDMI)Concurrent with PCIe

1. All strap signals are sampled with respect to the leading edge ofthe (G)MCH Power OK (PWROK) signal.2. iTPM can be disabled by a 'Soft-Strap' option in theFlash-decriptor section of the Firmware. This 'Soft-Strap' isactivated only after enabling iTPM via CFG6.Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

10 = XOR mode Enabled01 = ALLZ mode Enabled (Note 3)

LANE4

LANE5

LANE6 NC

NC

NC

NC

USB2(High speed)1011

NC

NC

MINIC1

NC

CardReader

NC

USB1

WEBCAM

Pair

4

Bluetooth

USB

5

0

2

3

1

Device

67

89

NC

NC

?

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

3D3V_CLKGEN_S03D3V_48MPWR_S03D3V_CLKPLL_S0

PCLKCLK5

PCLKCLK2

PCLKCLK4

CPU_SEL2_R

PCLKCLK1

PCLKCLK5PCLKCLK4

GEN_XTAL_OUT_RCLK48

PCLKCLK0

GEN_XTAL_OUT

3D3V_48MPWR_S0

PCLKCLK2

GEN_XTAL_IN

3D3V_CLKGEN_S0

3D3V_CLKPLL_S0

CLK48_ICHPCLK_ICHPCLK_KBCCLK_ICH14

CPU_SEL2_R

PCLK_FWH

PCLKCLK3CPU_SEL2_R

CLK48_5159

PCLKCLK3

PCIE_REQ_MINI#_R

PCIE_REQ_LAN#_R

PCLKCLK0

PCLKCLK1PCIE_REQ_MINI#_R

PCIE_REQ_LAN#_R

3D3V_S03D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

1D05V_S0

3D3V_S0

CPU_SEL14,7

PM_STPCPU#13

CLK48_ICH13

CLK_CPU_BCLK 4CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6CLK_MCH_BCLK# 6

CLK_PCIE_SATA 12CLK_PCIE_SATA# 12

CLK_PCIE_ICH 13CLK_PCIE_ICH# 13

PM_STPPCI#13

CLK_PWRGD13

PCLK_ICH13

CPU_SEL04,7

PCLK_KBC33

CLK_PCIE_LAN# 24CLK_PCIE_LAN 24

DREFCLK 7DREFCLK# 7

DREFSSCLK# 7DREFSSCLK 7

SMBD_ICH15,16,17SMBC_ICH15,16,17

CLK48_515930

CPU_SEL24,7

CLK_ICH1413

PCLK_FWH34

CLK_MCH_3GPLL 7CLK_MCH_3GPLL# 7

CLK_PCIE_MINI1 31CLK_PCIE_MINI1# 31

PCIE_REQ_MINI#31

PCIE_REQ_LAN#24

CLK_MCH_OE#7

SATACLKREQ#13

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Clock Generator

3 52Thursday, May 07, 2009LA14 SB

Title


Date: Sheet of


Clock Generator


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Date: Sheet of


Clock Generator


CL=20pF0.2pF

PIN NAME DESCRIPTIONByte 5, bit 10 = SRC3 enabled (default)1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pairByte 5, bit 00 = CR#_D controls SRC1 pair (default)1= CR#_D controls SRC4 pair

SRCC3/CR#_D

SRCC11/CR#_G

SRCT11/CR#_H

Byte 6, bit 70 = SRC7# enabled (default)1= CR#_F controls SRC6

Byte 6, bit 60 = SRC7 enabled (default)1= CR#_F controls SRC8

Byte 6, bit 40 = SRC11 enabled (default)1= CR#_H controls SRC10

Byte 6, bit 50 = SRC11# enabled (default)1= CR#_G controls SRC9

SRCC7/CR#_E

SRCT7/CR#_F

SEL1FSB

SEL0FSA

133M100M

166M800M

0 101 X

667M200M

0 1

CPUSEL2FSC

FSB

0 10

101

1066M266M0 0 0

533M

PIN NAME DESCRIPTIONByte 5, bit 70 = PCI0 enabled (default)1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pairByte 5, bit 60 = CR#_A controls SRC0 pair (default),1= CR#_A controls SRC2 pair

Byte 5, bit 50 = PCI1 enabled (default)1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pairByte 5, bit 40 = CR#_B controls SRC1 pair (default)1= CR#_B controls SRC4 pair

PCI1/CR#_B

0 = Overclocking of CPU and SRC Allowed1 = Overclocking of CPU and SRC NOT allowedPCI2/TME

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#PCI4/27M_SEL

ICS9LPRS365BKLFT setting table

0 =SRC8/SRC8#1 = ITP/ITP#PCI_F5/ITP_EN

PCI3

PCI0/CR#_A

Byte 5, bit 30 = SRC3 enabled (default)1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pairByte 5, bit 20 = CR#_C controls SRC0 pair (default),1= CR#_C controls SRC2 pair

SRCT3/CR#_C

CPU

NB

LAN

SB DMI

MINI1

NB CLK

SB SATA

NB CLKNB CLK

3.3V PCI clock output

(96 MHz)

0915 add EC34 for EMI demand

1014 add ER5 for EMI deamnd

1015 modify component size of R801015 modify component size of R871015 modify component size of R95

1120 swap thesenets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#,CLK_PCIE_MINI1,CLK_PCIE_MINI1#)

SB

SB 1120 add RN61 and RN621120 modify RN61 and RN62

1120 move these nets(CLK_PCIE_MINI1,CLK_PCIE_MINI1#)

SB

SB

SB1124 add R302

1126 add the net(PCIE_REQ_LAN#)SB

1126 add the net(PCIE_REQ_MINI#)SB

1126 modify RN61 and RN62SB

1127 swap the nets of RN61 and RN62SB

1231modify R801

1222 modify R871

11224 modify R91

12

C173SCD

1U16V2ZY-2G

P

DYC173SC

D1U

16V2ZY-2GP

DY12345 6 7 8

RN61SRN10KJ-6-GP

RN61SRN10KJ-6-GP

12

C179

SCD

1U16V2ZY-2G

P

C179

SCD

1U16V2ZY-2G

P

12

C204

SC4D

7U10V5ZY-3G

P

DY

C204

SC4D

7U10V5ZY-3G

P

DY

1 2R800R2J-2-GP

DYR80

0R2J-2-GP

DY

12R88 2K2R2J-2-GPR88 2K2R2J-2-GP

12

C156SCD

1U16V2ZY-2G

P

C156SCD

1U16V2ZY-2G

P

12

EC25

SC22P50V2JN

-4GP

DY

EC25

SC22P50V2JN

-4GP

DY

12

C176SCD

1U16V2ZY-2G

P

C176SCD

1U16V2ZY-2G

P

1 2

C230SC33P50V2JN-3GP

C230SC33P50V2JN-3GP

1 2R870R0402-PAD

R870R0402-PAD

1 2R302

0R2J-2-GP

R302

0R2J-2-GP

1234 5

678

RN62

SRN470J-3-GP

RN62

SRN470J-3-GP

12

C155

SCD

1U16V2ZY-2G

P

C155

SCD

1U16V2ZY-2G

P

12

X4X-14D31818M-35GP

82.30005.891

X4X-14D31818M-35GP

82.30005.891

12

EC66

SC5P50V2C

N-2G

P

DY

EC66

SC5P50V2C

N-2G

P

DY

12

C226

SCD

1U16V2ZY-2G

P

C226

SCD

1U16V2ZY-2G

P

GND

REF

1

X22X13

VDD

REF

4

REF0/FSLC/TEST_SEL5

SDATA6SCLK7

PCI0/CR#_A8

VDD

PCI

9

PCI1/CR#_B10PCI2/TME11PCI312PCI4/27_SELECT13PCI_F5/ITP_EN14

GND

PCI

15VD

D48

16

USB_48MHZ/FSLA17

GND

4818

VDD

96_I

O19

SRCT0/DOTT_96 20SRCC0/DOTC_96 21

GND

22VD

DPL

L323

27MHZ_NONSS/SRCT1/SE1 2427MHZ_SS/SRCC1/SE2 25

GND

26VD

DPL

L3_I

O27

SRCT2/SATAT 28SRCC2/SATAC 29

GND

SRC

30

SRCT3/CR#_C 31SRCC3/CR#_D 32

VDD

SRC_

IO33

SRCT4 34SRCC4 35

GND

SRC

36

SRCT9 37SRCC9 38

SRCC11/CR#_G 39SRCT11/CR#_H 40

SRCT10 41SRCC10 42

VDD

SRC_

IO43

CPU_STOP#44PCI_STOP#45

VDD

SRC

46

SRCC6 47SRCT6 48

GND

SRC

49

SRCC7/CR#_E 50SRCT7/CR#_F 51

VDD

SRC_

IO52

CPUC2_ITP/SRCC8 53CPUT2_ITP/SRCT8 54

NC#5555

VDD

CPU_

IO56

CPUC1_F 57CPUT1_F 58

GND

CPU

59

CPUC0 60CPUT0 61VD

DCP

U62

CK_PWRGD/PD#63

FSLB/TEST_MODE64

GND

65

U14

ICS9LPRS365BKLFT-GP-U71.09365.A03

2nd = 71.08513.003

U14

ICS9LPRS365BKLFT-GP-U71.09365.A03

2nd = 71.08513.003

12 3

4RN20

SRN22-3-GP

RN20

SRN22-3-GP

12

EC62

SC5P50V2C

N-2G

P

DY

EC62

SC5P50V2C

N-2G

P

DY

12R89 10KR2J-3-GP

DYR89 10KR2J-3-GP

DY

12ER5 33R2J-2-GP

DY

ER5 33R2J-2-GP

DY

12

C196SCD

1U16V2ZY-2G

P

DYC196SC

D1U

16V2ZY-2GP

DY

12

EC31

SC5P50V2C

N-2G

P

DY

EC31

SC5P50V2C

N-2G

P

DY

1 2 3 45678

RN28SRN10KJ-6-GPRN28SRN10KJ-6-GP

12

EC33SC

5P50V2CN

-2GP

DY

EC33SC

5P50V2CN

-2GP

DY

12

C149SC4D

7U10V5ZY-3G

P

C149SC4D

7U10V5ZY-3G

P

12

EC34

SC5P50V2C

N-2G

P

DY

EC34

SC5P50V2C

N-2G

P

DY

12

C152SCD

1U16V2ZY-2G

P

DYC152SC

D1U

16V2ZY-2GP

DY

12

C227SC1U

16V3ZY-GP

C227SC1U

16V3ZY-GP

1 2

C229SC33P50V2JN-3GP

C229SC33P50V2JN-3GP

1 2R95

0R2J-2-GP

R95

0R2J-2-GP

1234 5

678

RN23

SRN33J-7-GP

RN23

SRN33J-7-GP

12

C221

SC4D

7U6D3V3KX-GP

DYC221

SC4D

7U6D3V3KX-GP

DY

12

C224

SCD

1U16V2ZY-2G

P

C224

SCD

1U16V2ZY-2G

P

12

C205

SCD

1U16V2ZY-2G

P

DYC205

SCD

1U16V2ZY-2G

P

DY12

C165SCD

1U16V2ZY-2G

P

DY

C165SCD

1U16V2ZY-2G

P

DY

1 2R910R0402-PAD

R910R0402-PAD

?

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

H_A#18

H_A#20H_A#21H_A#22

H_A#17

H_A#19

H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28H_A#29H_A#30H_A#31

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16

H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4

H_A#[35..3]

H_RS#1H_RS#0

H_RS#2

H_IERR#

XDP_TCKXDP_TDI

XDP_TMSXDP_TRST#

XDP_TDO

XDP_DBRESET#

XDP_BPM#5

H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39

H_D#41H_D#40

H_D#42H_D#43

H_D#[63..0]

H_D#44H_D#45H_D#46H_D#47

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9

H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15

H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31

H_D#48H_D#49

H_D#51H_D#50

H_D#52H_D#53H_D#54H_D#55

H_D#57H_D#56

H_D#58H_D#59H_D#60H_D#61

H_D#63H_D#62

COMP0COMP1COMP2COMP3

TEST1

TEST2

H_DSTBN#[3..0]H_DSTBP#[3..0]

H_DINV#[3..0]

RSVD_CPU_12

RSVD_CPU_13RSVD_CPU_14RSVD_CPU_11

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_DBRESET#

XDP_TCK

H_THERMDC

H_THERMDA

CPU_GTLREF0

CPU_PROCHOT#

TEST4

TEST1TEST2

TEST4

H_A#32H_A#33H_A#34H_A#35

XDP_BPM#5

H_CPURST#

XDP_TDO

1D05V_S0

1D05V_S0

1D05V_S0

1D05V_S0

3D3V_S0

1D05V_S0

H_ADS# 6H_BNR# 6

H_DRDY# 6H_DBSY# 6

H_BREQ#0 6

H_HIT# 6H_HITM# 6

H_LOCK# 6

H_DSTBN#2 6H_DSTBP#2 6H_DINV#2 6

H_D#[63..0] 6

H_DSTBN#3 6H_DSTBP#3 6H_DINV#3 6

H_ADSTB#16

H_A#[35..3]6

H_ADSTB#06H_REQ#[4..0]6

H_DSTBN#06H_DSTBP#06H_DINV#06

H_DSTBN#16H_DSTBP#16H_DINV#16

H_BPRI# 6

H_DEFER# 6

H_INIT# 12

H_CPURST# 6,48H_RS#[2..0] 6

H_TRDY# 6

H_THERMDA 32

CLK_CPU_BCLK 3CLK_CPU_BCLK# 3

H_DPRSTP# 7,12,41H_DPSLP# 12H_DPWR# 6H_PWRGD 12,39,48H_CPUSLP# 6

H_FERR#12

H_THERMDC 32

PM_THRMTRIP-A# 7,12,39

H_INTR12H_NMI12H_SMI#12

H_IGNNE#12

H_A20M#12

H_DINV#[3..0] 6H_DSTBN#[3..0] 6H_DSTBP#[3..0] 6

CPU_SEL23,7

CPU_SEL03,7CPU_SEL13,7

H_STPCLK#12

PSI# 41

CPU_PROCHOT#_R 41

Title


Date: Sheet of


CPU (1 of 2)4 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

H_IERR# with a GND0.1" away

Place testpoint on

Layout Note:Comp0, 2 connect with Zo=27.4 ohm, make

Comp1, 3 connect with Zo=55 ohm, maketrace length shorter than 0.5" .

trace length shorter than 0.5" .

Layout Note:"CPU_GTLREF0"0.5" max length.

( No stub)

should connect toPM_THRMTRIP#

without T-ingICH9 and MCH

All place within 2" to CPU

Net "TEST4" as short as possible,make sure "TEST4" routing isreference to GND and away othernoisy signals

Side BandNon GTL

Follow Demo Circuit

1TP44TPAD14-GP TP44TPAD14-GP 1TP60TPAD14-GP TP60TPAD14-GP

12

C352SC1KP50V2KX-1GP

DYC352SC1KP50V2KX-1GP

DY

D16#N22D17#K25D18#P26D19#R23D20#L23D21#M24D22#L22D23#M23D24#P25D25#P23D26#P22D27#T24D28#R24D29#L25D30#T25D31#N25

DINV0#H25

DINV1#N24

DSTBN0#J26

DSTBN1#L26

DSTBP0#H26

DSTBP1#M26

D0#E22D1#F24D2#E26D3#G22D4#F23D5#G25D6#E25D7#E23D8#K24D9#G24D10#J24D11#J23D12#H22D13#F26D14#K22D15#H23

D53# AC26

D60# AC22

D63# AC23

GTLREFAD26

TEST2D25

BSEL0B22BSEL1B23BSEL2C21

DINV2# U22

D32# Y22D33# AB24D34# V24D35# V26D36# V23

D38# U25D39# U23D40# Y25D41# W22D42# Y23D43# W24D44# W25D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20D55# AE22D56# AF23D57# AC25D58# AE21D59# AD21

D61# AD23

DINV3# AC20DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5DPSLP# B5DPWR# D24

PWRGOOD D6SLP# D7PSI# AE6

TEST1C23

TEST6A26

TEST3C24

TEST5AF1TEST4AF26

D37# T22

DSTBP3# AF24

COMP2 AA1COMP3 Y1

2 OF 4

DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

U33B

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

2 OF 4

DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

U33B

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

1 2R42 54D9R2F-L1-GPR42 54D9R2F-L1-GP

1 2R60 1KR2J-1-GPDYR60 1KR2J-1-GPDY

1 2R213 51R2F-2-GPDYR213 51R2F-2-GPDY

12

R1791KR2F-3-GP

R1791KR2F-3-GP

1TP11 TPAD14-GPTP11 TPAD14-GP

1 2R48 54D9R2F-L1-GPR48 54D9R2F-L1-GP

1 2R53 27D4R2F-L1-GPR53 27D4R2F-L1-GP1 2R51 54D9R2F-L1-GPR51 54D9R2F-L1-GP

A3#J4A4#L5A5#L4A6#K5A7#M3A8#N2A9#J1A10#N3A11#P5A12#P2A13#L2A14#P4A15#P1A16#R1

A20M#A6

ADS# H1

ADSTB0#M1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L1

A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5

A30#U2

A24#R4A25#T5A26#T3

A32#W3

A28#W5A29#Y4A27#W2

A31#V4

A33#AA4A34#AB2A35#AA3

FERR#A5IGNNE#C4

RSVD#M4M4RSVD#N5N5RSVD#T2T2RSVD#V3V3RSVD#B2B2RSVD#C3C3

BNR# E2BPRI# G5

DEFER# H5

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2

HIT# G6HITM# E4

BPM0# AD4BPM1# AD3BPM2# AD1BPM3# AC4PRDY# AC2PREQ# AC1

TCK AC5TDI AA6

TDO AB3TMS AB5

TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2D2

RSVD#F6F6RSVD#D3D3RSVD#D22D22

STPCLK#D5LINT0C6LINT1B4SMI#A3

A23#U1

ADSTB1#V1

RESET# C1

KEY_NCB1

THRMDC B25

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

U33A

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

U33A

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

12C343 SCD1U10V2KX-4GP

DYC343 SCD1U10V2KX-4GP

DY

1TP20TPAD14-GP TP20TPAD14-GP

12

R6368R2-GPR6368R2-GP

1 2R62

0R2J-2-GP

DYR62

0R2J-2-GP

DY


12

C438SC2200P50V2KX-2GPDY C438SC2200P50V2KX-2GPDY

1 2R41 54D9R2F-L1-GPR41 54D9R2F-L1-GP

1 2R45 27D4R2F-L1-GPR45 27D4R2F-L1-GP

1 2R43 54D9R2F-L1-GPR43 54D9R2F-L1-GP

1 2R44 54D9R2F-L1-GPR44 54D9R2F-L1-GP

12

R6456R2J-4-GPR6456R2J-4-GP

12

R1812KR2F-3-GP

R1812KR2F-3-GP



1 2R50 54D9R2F-L1-GPR50 54D9R2F-L1-GP

1 2R47 54D9R2F-L1-GPDYR47 54D9R2F-L1-GPDY

?

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

H_VID0H_VID1H_VID2H_VID3H_VID4H_VID5H_VID6

1D5V_S01D5V_VCCA_S0

1D05V_S0

VCC_CORE

VCC_CORE

VCC_CORE

VCC_CORE

1D05V_S0

VCC_CORE

VCC_CORE

VCC_CORE

VCC_SENSE 41

VSS_SENSE 41

H_VID[6..0] 41

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

Layout Note:

should be of equal length.VCCSENSE and VSSSENSE lines

Layout Note:Provide a test point (withno stub) to connect a differential probe between VCCSENSE andVSSSENSE at the locationwhere the two 54.9ohmresistors terminate the55 ohm transmission line.

layout note: "1D5V_VCCA_S0"as short as possible

One phase-->ADD TC6 are77.E9071.011

12

C65SC

D1U

10V2KX-4GP

C65SC

D1U

10V2KX-4GP

1 TP45TPAD14-GP TP45TPAD14-GP

12

C96

SCD

1U10V2KX-4G

P

DY

C96

SCD

1U10V2KX-4G

P

DY

12

C69

SCD

1U10V2KX-4G

P

C69

SCD

1U10V2KX-4G

P

VCCA7VCCA9

VCCAC10

VCCA10VCCA12VCCA13VCCA15VCCA17VCCA18VCCA20VCCB7VCCB9VCCB10VCCB12VCCB14VCCB15VCCB17VCCB18VCCB20VCCC9VCCC10VCCC12VCCC13VCCC15VCCC17VCCC18VCCD9VCCD10VCCD12VCCD14VCCD15VCCD17VCCD18VCCE7VCCE9VCCE10VCCE12VCCE13VCCE15

VCCAA7VCCAA9VCCAA10VCCAA12VCCAA13VCCAA15VCCAA17VCCAA18VCCAA20VCCAB9

VCCAB12VCCAB14VCCAB15VCCAB17VCCAB18

VCCE17VCCE18VCCE20VCCF7VCCF9VCCF10VCCF12VCCF14VCCF15VCCF17VCCF18VCCF20

VCC AB20VCC AB7VCC AC7VCC AC9VCC AC12VCC AC13VCC AC15VCC AC17VCC AC18VCC AD7VCC AD9VCC AD10VCC AD12VCC AD14VCC AD15VCC AD17VCC AD18VCC AE9VCC AE10VCC AE12VCC AE13VCC AE15VCC AE17VCC AE18VCC AE20VCC AF9VCC AF10VCC AF12VCC AF14VCC AF15VCC AF17VCC AF18VCC AF20

VCCP G21

VCCP J6

VCCP J21VCCP K6

VCCP K21VCCP M6

VCCP M21

VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6VCCP T21

VCCP V6

VCCP V21VCCP W21

VCCA B26VCCA C26

VID0 AD6

VID6 AE2VID4 AE3VID2 AE5

VID5 AF3VID3 AF4VID1 AF5

VSSSENSE AE7

VCCSENSE AF7VCCAB10

3 OF 4U33C

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

3 OF 4U33C

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

12

C384

SC10U6D3V5M

X-3GP

DY

C384

SC10U6D3V5M

X-3GP

DY

12

C97SCD

1U10V2KX-4G

P

DY

C97SCD

1U10V2KX-4G

P

DY

12

C52

SCD

1U10V2KX-4G

P

DY

C52

SCD

1U10V2KX-4G

P

DY

12

R38100R2F-L1-GP-UR38100R2F-L1-GP-U


12

C92

SC10U6D3V5M

X-3GP

CAP

C92

SC10U6D3V5M

X-3GP

CAP

12

C66

SC4D

7U6D3V3KX-GP

C66

SC4D

7U6D3V3KX-GP

12

C84SCD

1U10V2KX-4G

P

C84SCD

1U10V2KX-4G

P



12

C80

SC10U6D3V5M

X-3GP

DY

C80

SC10U6D3V5M

X-3GP

DY

12

R39100R2F-L1-GP-UR39100R2F-L1-GP-U

12

C93

SCD

1U10V2KX-4G

P

DY

C93

SCD

1U10V2KX-4G

P

DY

12

C68SCD

1U10V2KX-4G

P

DY

C68SCD

1U10V2KX-4G

P

DY

12

C420SCD01U

16V2KX-3GP

DY

C420SCD01U

16V2KX-3GP

DY

12

C49

SC10U6D3V5M

X-3GP

DY

C49

SC10U6D3V5M

X-3GP

DY

VSSAF2

VSSA4VSSA8VSSA11VSSA14VSSA16VSSA19VSSA23

VSSB6VSSB8VSSB11VSSB13VSSB16VSSB19VSSB21VSSB24VSSC5VSSC8VSSC11VSSC14VSSC16VSSC19VSSC2VSSC22VSSC25VSSD1VSSD4VSSD8VSSD11VSSD13VSSD16VSSD19VSSD23VSSD26VSSE3VSSE6VSSE8VSSE11VSSE14VSSE16VSSE19VSSE21VSSE24VSSF5VSSF8VSSF11VSSF13VSSF16VSSF19VSSF2VSSF22VSSF25VSSG4VSSG1VSSG23VSSG26VSSH3VSSH6VSSH21VSSH24VSSJ2VSSJ5VSSJ22VSSJ25VSSK1VSSK4VSSK23VSSK26VSSL3VSSL6VSSL21VSSL24VSSM2VSSM5VSSM22VSSM25VSSN1VSSN4VSSN23VSSN26VSSP3

VSS P6VSS P21VSS P24VSS R2VSS R5VSS R22VSS R25VSS T1VSS T4VSS T23VSS T26VSS U3VSS U6VSS U21VSS U24VSS V2VSS V5VSS V22VSS V25VSS W1VSS W4VSS W23VSS W26VSS Y3VSS Y6VSS Y21VSS Y24VSS AA2VSS AA5VSS AA8VSS AA11VSS AA14VSS AA16VSS AA19VSS AA22VSS AA25VSS AB1VSS AB4VSS AB8VSS AB11VSS AB13VSS AB16VSS AB19VSS AB23VSS AB26VSS AC3VSS AC6VSS AC8VSS AC11VSS AC14VSS AC16VSS AC19VSS AC21VSS AC24VSS AD2VSS AD5VSS AD8VSS AD11VSS AD13VSS AD16VSS AD19VSS AD22VSS AD25VSS AE1VSS AE4VSS AE8VSS AE11VSS AE14VSS AE16VSS AE19VSS AE23VSS AE26VSS A2VSS AF6VSS AF8VSS AF11VSS AF13VSS AF16VSS AF19VSS AF21VSS A25VSS AF25

4 OF 4U33D

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

4 OF 4U33D

BGA479-SKT6-GPU762.10079.001

2nd = 62.10053.401

12

C54SCD

1U10V2KX-4G

P

DY

C54SCD

1U10V2KX-4G

P

DY

12

C82

SCD

1U10V2KX-4G

P

C82

SCD

1U10V2KX-4G

P

12

C71

SC10U6D3V5M

X-3GP

DY

C71

SC10U6D3V5M

X-3GP

DY

12

C70

SC10U6D3V5M

X-3GP

CAP

C70

SC10U6D3V5M

X-3GP

CAP

12

C383

SC10U6D3V5M

X-3GP

CAP

C383

SC10U6D3V5M

X-3GP

CAP

12

C446

SC4D

7U6D3V3KX-GP

DY

C446

SC4D

7U6D3V3KX-GP

DY

12

C48

SC10U6D3V5M

X-3GP

DY

C48

SC10U6D3V5M

X-3GP

DY

12

C91SCD

1U10V2KX-4G

P

DY

C91SCD

1U10V2KX-4G

P

DY

12

C429SC10U6D3V5M

X-3GP

C429SC10U6D3V5M

X-3GP

12

C81

SCD

1U10V2KX-4G

P

C81

SCD

1U10V2KX-4G

P

12

C90

SC10U6D3V5M

X-3GP

CAP

C90

SC10U6D3V5M

X-3GP

CAP

12

C62

SC10U6D3V5M

X-3GP

DY

C62

SC10U6D3V5M

X-3GP

DY

12

C382

SC10U6D3V5M

X-3GP

CAP

C382

SC10U6D3V5M

X-3GP

CAP

12

C63

SCD

1U10V2KX-4G

PDY

C63

SCD

1U10V2KX-4G

PDY

12

C381

SC10U6D3V5M

X-3GP

DY

C381

SC10U6D3V5M

X-3GP

DY


12

C83

SCD

1U10V2KX-4G

P

C83

SCD

1U10V2KX-4G

P

12

C78

SCD

1U10V2KX-4G

P

C78

SCD

1U10V2KX-4G

P

12

C79

SC10U6D3V5M

X-3GP

DY

C79

SC10U6D3V5M

X-3GP

DY

12

C53SCD

1U10V2KX-4G

P

DY

C53SCD

1U10V2KX-4G

P

DY

1 TP61TPAD14-GP TP61TPAD14-GP1

2 34

TC6

ST900U2D5VM-1-GPDYTC6

ST900U2D5VM-1-GPDY

12

C59

SCD

1U10V2KX-4G

P

DY

C59

SCD

1U10V2KX-4G

P

DY

12

C61

SC10U6D3V5M

X-3GP

CAP

C61

SC10U6D3V5M

X-3GP

CAP

1 2

L10

PBY160808T-121Y-GP68.00206.021

2nd = 68.00230.041

L10

PBY160808T-121Y-GP68.00206.021

2nd = 68.00230.041

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_D#[63..0]H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63

H_A#35

H_A#29H_A#30H_A#31

H_A#26H_A#27H_A#28

H_A#23H_A#24H_A#25

H_A#20H_A#21H_A#22

H_A#17H_A#18H_A#19

H_A#14H_A#15H_A#16

H_A#11H_A#12H_A#13

H_A#8H_A#9H_A#10

H_A#5H_A#6H_A#7

H_A#3H_A#4

H_A#[35..3]

H_A#33H_A#34

H_A#32

H_RS#1H_RS#2

H_RS#0

H_REQ#1

H_REQ#3H_REQ#2

H_REQ#0

H_REQ#4

H_REQ#[4..0]

H_DSTBN#[3..0]

H_DSTBN#3H_DSTBN#2H_DSTBN#1H_DSTBN#0

H_DSTBP#[3..0]

H_DSTBP#2

H_DSTBP#0

H_DSTBP#3

H_DSTBP#1

H_DINV#0H_DINV#1H_DINV#2H_DINV#3

H_DINV#[3..0]H_RCOMP

H_SWING

H_RS#[2..0]

H_AVREF

H_SWINGH_RCOMP

1D05V_S0

1D05V_S0

H_D#[63..0]4

H_CPURST#4,48H_CPUSLP#4

H_A#[35..3] 4

H_BNR# 4

H_BREQ#0 4

H_ADS# 4H_ADSTB#0 4H_ADSTB#1 4

H_DBSY# 4

H_DRDY# 4H_HIT# 4H_HITM# 4

CLK_MCH_BCLK 3CLK_MCH_BCLK# 3

H_LOCK# 4

H_BPRI# 4

H_DEFER# 4

H_DPWR# 4

H_TRDY# 4

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

Title


Date: Sheet of


Cantiga (1 of 6)_HOST6 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

Place them near to the chip ( < 0.5")

H_RCOMP routing Trace width andSpacing use 10 / 20 mil

H_SWING routing Trace width andSpacing use 10 / 20 mil

H_SWING Resistors andCapacitors close MCH500 mil ( MAX )

1 2R226 24D9R2F-L-GPR226 24D9R2F-L-GP

12

C478SCD1U10V2KX-4GP

C478SCD1U10V2KX-4GP

12

R239221R2F-2-GPR239221R2F-2-GP

12

R238100R2F-L1-GP-UR238100R2F-L1-GP-U

H_A#_10 P16H_A#_11 R16H_A#_12 N17H_A#_13 M13H_A#_14 E17H_A#_15 P17H_A#_16 F17H_A#_17 G20H_A#_18 B19H_A#_19 J16H_A#_20 E20H_A#_21 H16H_A#_22 J20H_A#_23 L17H_A#_24 A17H_A#_25 B17H_A#_26 L16H_A#_27 C21H_A#_28 J17H_A#_29 H20

H_A#_3 A14

H_A#_30 B18H_A#_31 K17

H_A#_4 C15H_A#_5 F16H_A#_6 H13H_A#_7 C18H_A#_8 M16H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16H_ADSTB#_1 G17

H_BNR# A9H_BPRI# F11

H_BREQ# G12

HPLL_CLK# AH6

H_CPURST#C12

HPLL_CLK AH7

H_D#_0F2

H_REQ#_2 F13H_REQ#_3 B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4H_D#_9H3

H_DBSY# B10

H_D#_11M11H_D#_12J1H_D#_13J2H_D#_14N12H_D#_15J6H_D#_16P2H_D#_17L2H_D#_18R2H_D#_19N9

H_D#_2F8

H_D#_21M5H_D#_22J3H_D#_23N2H_D#_24R1H_D#_25N5H_D#_26N6H_D#_27P13H_D#_28N8H_D#_29L7

H_D#_3E6

H_D#_31M3H_D#_32Y3H_D#_33AD14H_D#_34Y6H_D#_35Y10H_D#_36Y12H_D#_37Y14H_D#_38Y7H_D#_39W2

H_D#_4G2

H_D#_41Y9H_D#_42AA13H_D#_43AA9H_D#_44AA11H_D#_45AD11H_D#_46AD10H_D#_47AD13H_D#_48AE12H_D#_49AE9

H_D#_5H6

H_D#_51AD8H_D#_52AA3H_D#_53AD3H_D#_54AD7H_D#_55AE14H_D#_56AF3H_D#_57AC1H_D#_58AE3H_D#_59AC3

H_D#_6H2

H_D#_61AE8H_D#_62AG2H_D#_63AD6

H_D#_7F6

H_DEFER# E9

H_DINV#_0 J8H_DINV#_1 L3H_DINV#_2 Y13H_DINV#_3 Y1

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10H_DSTBN#_1 M7H_DSTBN#_2 AA5H_DSTBN#_3 AE6

H_DSTBP#_0 L9H_DSTBP#_1 M8H_DSTBP#_2 AA6H_DSTBP#_3 AE5

H_AVREFA11H_DVREFB11

H_TRDY# C9

H_HIT# H9H_HITM# E12H_LOCK# H11

H_REQ#_0 B15H_REQ#_1 K13

H_REQ#_4 B14

H_A#_32 B20H_A#_33 F21H_A#_34 K21H_A#_35 L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0 B6H_RS#_1 F12H_RS#_2 C8

HOST

1 OF 10U35A

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

HOST

1 OF 10U35A

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

12

R2402KR2F-3-GPR2402KR2F-3-GP

12


12

C479SCD1U16V2ZY-2GPC479SCD1U16V2ZY-2GP

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PM_EXTTS#1PM_EXTTS#0

PM_SYNC#

PWROK_GDRSTIN#

PM_DPRSLPVRPM_THRMTRIP-A#

H_DPRSTP#

M_RCOMPPM_RCOMPN

SM_RCOMP_VOHSM_RCOMP_VOL

DREFSSCLK#

DREFCLK#DREFSSCLK

DREFCLK

DMI_TXP3

DMI_RXN3

DMI_TXN2DMI_TXN1DMI_TXN0

DMI_TXN3

DMI_RXP3DMI_RXP2DMI_RXP1DMI_RXP0

DMI_TXP2DMI_TXP1DMI_TXP0

DMI_RXN2DMI_RXN1DMI_RXN0

CLPWROK_MCH

MCH_CLVREF

M_RCOMPP

M_RCOMPN

CFG20

CLK_MCH_OE#

GMCH_LCDVDD_ON

CLK_DDC_EDIDLCTLB_DATA

LCTLA_CLK

DAT_DDC_EDID

GMCH_BL_ONL_BKLTCTL

L_LVBGLIBG

GMCH_DDCDATAGMCH_DDCCLK

GMCH_HS

GMCH_VS

CRT_IREF

GMCH_BLUE

GMCH_GREEN

GMCH_RED

PEG_CMP

SM_RCOMP_VOH

SM_RCOMP_VOL

PM_EXTTS#0PM_EXTTS#1

LIBG

SM_REXTTP_SM_DRAMRST#

MCH_TSATN#

TVA_DAC

TVC_DACTVB_DAC

TVC_DACTVB_DACTVA_DAC

LCTLB_DATALCTLA_CLK

GMCH_BL_ONGMCH_LCDVDD_ON

GMCH_REDGMCH_GREEN

GMCH_BLUE

CFG16

1D05V_S0

3D3V_S0

1D05V_S0

1D8V_S3

3D3V_S0

1D8V_S3

DDR_VREF_S3

1D05V_S0

3D3V_S0

CPU_SEL13,4CPU_SEL23,4

CPU_SEL03,4

H_DPRSTP#4,12,41PM_SYNC#13

PLT_RST1#13,24,30,31,33,34

PM_THRMTRIP-A#4,12,39

M_CLK_DDR#2 16M_CLK_DDR#3 16

M_CLK_DDR0 17M_CLK_DDR1 17

M_CKE0 17M_CKE1 17M_CKE2 16M_CKE3 16

M_CLK_DDR2 16M_CLK_DDR3 16

M_CS1# 17M_CS2# 16M_CS3# 16

M_CS0# 17

M_CLK_DDR#0 17M_CLK_DDR#1 17

M_ODT0 17M_ODT1 17M_ODT2 16M_ODT3 16

CLK_MCH_3GPLL 3CLK_MCH_3GPLL# 3

DREFCLK# 3DREFCLK 3

DREFSSCLK# 3DREFSSCLK 3

DMI_RXN0 13

DMI_TXN0 13DMI_TXN1 13

DMI_TXP1 13

DMI_TXN2 13DMI_TXN3 13

DMI_TXP0 13

DMI_TXP2 13DMI_TXP3 13

DMI_RXN1 13DMI_RXN2 13DMI_RXN3 13

DMI_RXP0 13

DMI_RXP2 13DMI_RXP3 13

DMI_RXP1 13

CL_RST#0 13

CL_CLK0 13CL_DATA0 13

PWROK 13,39

MCH_ICH_SYNC# 13

L_BKLTCTL18

GMCH_LCDVDD_ON18

CLK_DDC_EDID18DAT_DDC_EDID18

GMCH_BL_ON33

GMCH_TXAOUT0+18GMCH_TXAOUT1+18GMCH_TXAOUT2+18

GMCH_TXAOUT0-18GMCH_TXAOUT1-18GMCH_TXAOUT2-18

GMCH_TXACLK-18GMCH_TXACLK+18

GMCH_DDCCLK19GMCH_DDCDATA19

GMCH_GREEN19

GMCH_BLUE19

GMCH_RED19

CLK_MCH_OE# 3

PM_DPRSLPVR13,41

PWROK13,39

GMCH_HSYNC19GMCH_VSYNC19

Title


Date: Sheet of


Cantiga (2 of 6)_DMI/PM/CFG7 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

CRT_IREF routing Tracewidth use 20 mil

FOR Cantiga:500 ohm Teenah: 392 ohm

Close to GMCH as 500 mils.

layout take note

Pin Name Strap Description Configuration

CFG20 Digital DisplayPort(SDVO/DP/HDMI)Concurrent withPCIE

Low = Only digital DisplayPort(SDVO/DP/HDMI) or PCIE is operational (default)

High = Digital DisplayPort(SDVO/DP/HDMI) and PCIE are operating simultaneously via the PEG port

0912 delete GMCH_TXB*

0912 add these parts for EMI demand

1014 swap these nets

1017 delete these parts(EC208~EC210)

11224 add R306

12R110 0R0402-PADR110 0R0402-PAD

12

R92511R2F-2-GPR92511R2F-2-GP

1 2R211 100R2J-2-GPR211 100R2J-2-GP

12


12

C487SCD01U16V2KX-3GPC487SCD01U16V2KX-3GP

12


TP36TPAD30TP36TPAD30

1234 5

678

RN22

SRN100KJ-8-GP-U

RN22

SRN100KJ-8-GP-U

1 2R98 4K02R2F-GPDYR98 4K02R2F-GPDY

12

R242

56R2J-4-GP

R242

56R2J-4-GP

PEG_COMPI T37PEG_COMPO T36

PEG_RX#_0 H44PEG_RX#_1 J46PEG_RX#_2 L44PEG_RX#_3 L40PEG_RX#_4 N41PEG_RX#_5 P48PEG_RX#_6 N44PEG_RX#_7 T43PEG_RX#_8 U43PEG_RX#_9 Y43

PEG_RX#_10 Y48PEG_RX#_11 Y36PEG_RX#_12 AA43PEG_RX#_13 AD37PEG_RX#_14 AC47PEG_RX#_15 AD39

PEG_RX_0 H43PEG_RX_1 J44PEG_RX_2 L43PEG_RX_3 L41PEG_RX_4 N40PEG_RX_5 P47PEG_RX_6 N43PEG_RX_7 T42PEG_RX_8 U42PEG_RX_9 Y42

PEG_RX_10 W47PEG_RX_11 Y37PEG_RX_12 AA42PEG_RX_13 AD36PEG_RX_14 AC48PEG_RX_15 AD40

PEG_TX#_0 J41

PEG_TX#_10 Y40

PEG_TX#_3 M40PEG_TX#_4 M42PEG_TX#_5 R48PEG_TX#_6 N38PEG_TX#_7 T40PEG_TX#_8 U37PEG_TX#_9 U40

PEG_TX#_1 M46

PEG_TX#_11 AA46PEG_TX#_12 AA37PEG_TX#_13 AA40PEG_TX#_14 AD43PEG_TX#_15 AC46

PEG_TX#_2 M47

PEG_TX_0 J42PEG_TX_1 L46PEG_TX_2 M48PEG_TX_3 M39PEG_TX_4 M43PEG_TX_5 R47PEG_TX_6 N37PEG_TX_7 T39PEG_TX_8 U36PEG_TX_9 U39

PEG_TX_10 Y39PEG_TX_11 Y46PEG_TX_12 AA36PEG_TX_13 AA39PEG_TX_14 AD42PEG_TX_15 AD46

L_CTRL_CLKM32

L_CTRL_DATAM33L_DDC_CLKK33L_DDC_DATAJ33

L_VDD_ENM29LVDS_IBGC44LVDS_VBGB43LVDS_VREFHE37LVDS_VREFLE38LVDSA_CLK#C41LVDSA_CLKC40

LVDSA_DATA#_0H47LVDSA_DATA#_1E46LVDSA_DATA#_2G40

LVDSA_DATA_1D45LVDSA_DATA_2F40

LVDSB_CLK#B37LVDSB_CLKA37

LVDSB_DATA#_0A41LVDSB_DATA#_1H38LVDSB_DATA#_2G37

LVDSB_DATA_1G38LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25TVB_DACH25TVC_DACK25

TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29CRT_TVO_IREFE29

CRT_REDJ28

CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

3 OF 10U35C

CANTIGA-GM-GP-U-NF71.CNTIG.00U

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

3 OF 10U35C


12 3

4

RN21SRN33J-5-GP-U

RN21SRN33J-5-GP-U

12

C147SC100P50V2JN-3GP DY

C147SC100P50V2JN-3GP DY

12


12

C489

SC2D2U6D3V3MX-1-GP

C489

SC2D2U6D3V3MX-1-GP

1234 5

678

RN15

SRN75J-1-GP

RN15

SRN75J-1-GP

1 2R306 4K02R2F-GPDYR306 4K02R2F-GPDY

12


12345

678

RN32

SRN10KJ-6-GP

RN32

SRN10KJ-6-GP

12

R24680D6R2F-L-GPR24680D6R2F-L-GP

12

R2503K01R2F-3-GPR2503K01R2F-3-GP

SA_CK_0 AP24SA_CK_1 AT21SB_CK_0 AV24

SA_CK#_0 AR24SA_CK#_1 AR21SB_CK#_0 AU24

SA_CKE_0 BC28SA_CKE_1 AY28SB_CKE_0 AY36SB_CKE_1 BB36

SA_CS#_0 BA17SA_CS#_1 AY16SB_CS#_0 AV16SB_CS#_1 AR13

SM_DRAMRST# BC36

SA_ODT_0 BD17SA_ODT_1 AY17SB_ODT_0 BF15SB_ODT_1 AY13

SM_RCOMP BG22SM_RCOMP# BH21

CFG_18P29CFG_19R28

CFG_2P25CFG_0T25CFG_1R25

CFG_20T28

CFG_3P20CFG_4P24CFG_5C25CFG_6N24CFG_7M24CFG_8E21CFG_9C23CFG_10C24CFG_11N21CFG_12P21CFG_13T21CFG_14R20CFG_15M20CFG_16L21CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33PM_EXT_TS#_1P32PWROKAT40RSTIN#AT11

DPLL_REF_CLK B38DPLL_REF_CLK# A38

DPLL_REF_SSCLK E41DPLL_REF_SSCLK# F41

DMI_RXN_0 AE41DMI_RXN_1 AE37DMI_RXN_2 AE47DMI_RXN_3 AH39

DMI_RXP_0 AE40DMI_RXP_1 AE38DMI_RXP_2 AE48DMI_RXP_3 AH40

DMI_TXN_0 AE35DMI_TXN_1 AE43DMI_TXN_2 AE46DMI_TXN_3 AH42

DMI_TXP_0 AD35DMI_TXP_1 AE44DMI_TXP_2 AF46DMI_TXP_3 AH43

RESERVED#AL34AL34

RESERVED#AN35AN35RESERVED#AK34AK34

RESERVED#AM35AM35

RESERVED#BG23BG23RESERVED#BF23BF23RESERVED#BH18BH18RESERVED#BF18BF18

PM_DPRSTP#B7

SB_CK_1 AU20

SB_CK#_1 AV20

RESERVED#AY21AY21

RESERVED#AH9AH9RESERVED#AH10AH10RESERVED#AH12AH12RESERVED#AH13AH13

RESERVED#M36M36RESERVED#N36N36RESERVED#R33R33RESERVED#T33T33

GFX_VID_0 B33GFX_VID_1 B32GFX_VID_2 G33GFX_VID_3 F33

GFX_VR_EN C34

SM_RCOMP_VOH BF28SM_RCOMP_VOL BH28

THERMTRIP#T20DPRSLPVRR32

RESERVED#K12K12

CL_CLK AH37CL_DATA AH36

CL_PWROK AN36CL_RST# AJ35CL_VREF AH34

NC#A47A47

NC#BG48BG48NC#BF48BF48NC#BD48BD48NC#BC48BC48NC#BH47BH47NC#BG47BG47NC#BE47BE47NC#BH46BH46NC#BF46BF46NC#BG45BG45NC#BH44BH44NC#BH43BH43NC#BH6BH6NC#BH5BH5NC#BG4BG4

SDVO_CTRLCLK G36SDVO_CTRLDATA E36

CLKREQ# K36

RESERVED#T24T24

ICH_SYNC# H36

TSATN# B12

PEG_CLK# E43PEG_CLK F43

NC#BH3BH3

GFX_VID_4 E33

RESERVED#B31B31

DDPC_CTRLCLK N28

NC#BF3BF3NC#BH2BH2NC#BG2BG2NC#BE2BE2NC#BG1BG1NC#BF1BF1NC#BD1BD1NC#BC1BC1NC#F1F1

SM_VREF AV42SM_PWROK AR36

SM_REXT BF17

RESERVED#M1M1

HDA_BCLK B28HDA_RST# B30

HDA_SDI B29HDA_SDO C29

HDA_SYNC A28

DDPC_CTRLDATA M28

RESERVED#B2B2

PM

MISC

NC

DDR CLK/

CONT

ROL/

COMP

ENSA

TION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

2 OF 10U35B

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

PM

MISC

NC

DDR CLK/

CONT

ROL/

COMP

ENSA

TION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

2 OF 10U35B

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

123

4RN29

SRN10KJ-5-GP

RN29

SRN10KJ-5-GP

12

C483

SC2D2U6D3V3MX-1-GP

C483

SC2D2U6D3V3MX-1-GP

12

R24780D6R2F-L-GPR24780D6R2F-L-GP

12R99

49D9R2F-GP

R99

49D9R2F-GP


1 2R253 1K02R2F-1-GPR253 1K02R2F-1-GP


1 2R243499R2F-2-GP

R243499R2F-2-GP

12

C231SCD

1U10V2KX-4G

P

C231SCD

1U10V2KX-4G

P

1234 5

678

RN14

SRN150F-1-GP

RN14

SRN150F-1-GP

12 R1110R0402-PADR1110R0402-PAD

12

C250SCD

1U10V2KX-4G

P

C250SCD

1U10V2KX-4G

P

1 2R103

2K37R2F-GP

R103

2K37R2F-GP

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63..0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_A_DQS#3

M_A_DQS#0

M_A_DQS#6

M_A_DQS#4

M_A_DQS#1M_A_DQS#2

M_A_DQS#5

M_A_DQS#7

M_A_A0

M_A_A6

M_A_A3

M_A_A5

M_A_A7

M_A_A1M_A_A2

M_A_A4

M_A_A10

M_A_A8

M_A_A13

M_A_A11

M_A_A9

M_A_A12

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_DM[7..0]M_A_DM0M_A_DM1M_A_DM2M_A_DM3M_A_DM4M_A_DM5M_A_DM6M_A_DM7

M_A_DQS[7..0]

M_A_DQS5

M_A_DQS7

M_A_DQS2M_A_DQS3M_A_DQS4

M_A_DQS0M_A_DQS1

M_A_DQS6

M_A_A14

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63..0]

M_B_DQS#[7..0]M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7

M_B_DQS[7..0]M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_A12

M_B_A9

M_B_A11

M_B_A13

M_B_A8

M_B_A10

M_B_A[14..0]M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7

M_B_DM[7..0]M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7

M_B_A14

M_A_DQ[63..0]17M_A_BS#0 17M_A_BS#1 17M_A_BS#2 17

M_A_CAS# 17

M_A_DQS#[7..0] 17

M_A_DQS[7..0] 17

M_A_A[14..0] 17

M_A_DM[7..0] 17

M_A_RAS# 17

M_A_WE# 17

M_B_DQ[63..0]16M_B_BS#0 16M_B_BS#1 16M_B_BS#2 16

M_B_CAS# 16M_B_RAS# 16

M_B_WE# 16

M_B_DQS#[7..0] 16

M_B_DQS[7..0] 16

M_B_A[14..0] 16

M_B_DM[7..0] 16

Title


Date: Sheet of


Cantiga (3 of 6)_DDR8 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

SB_DQ_0AK47SB_DQ_1AH46

SB_DQ_10BA48SB_DQ_11AY48SB_DQ_12AT47SB_DQ_13AR47SB_DQ_14BA47SB_DQ_15BC47SB_DQ_16BC46SB_DQ_17BC44SB_DQ_18BG43SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45SB_DQ_21BC41SB_DQ_22BF40SB_DQ_23BF41SB_DQ_24BG38SB_DQ_25BF38SB_DQ_26BH35SB_DQ_27BG35SB_DQ_28BH40SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34SB_DQ_31BH34SB_DQ_32BH14SB_DQ_33BG12SB_DQ_34BH11SB_DQ_35BG8SB_DQ_36BH12SB_DQ_37BF11SB_DQ_38BF8SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5SB_DQ_41BC6SB_DQ_42AY3SB_DQ_43AY1SB_DQ_44BF6SB_DQ_45BF5SB_DQ_46BA1SB_DQ_47BD3SB_DQ_48AV2SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3SB_DQ_51AN2SB_DQ_52AY2SB_DQ_53AV1SB_DQ_54AP3SB_DQ_55AR1SB_DQ_56AL1SB_DQ_57AL2SB_DQ_58AJ1SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2SB_DQ_61AM3SB_DQ_62AH3SB_DQ_63AJ3

SB_DQ_7AP48SB_DQ_8AU47SB_DQ_9AU46

SB_BS_0 BC16SB_BS_1 BB17SB_BS_2 BB33

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47SB_DM_2 BD40SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3SB_DM_6 AP1SB_DM_7 AK2

SB_DQS_0 AL47SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1SB_DQS_7 AN6

SB_DQS#_0 AL46SB_DQS#_1 AV47SB_DQS#_2 BH41SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2SB_DQS#_6 AT2SB_DQS#_7 AN5

SB_MA_0 AV17SB_MA_1 BA25

SB_MA_10 BB16SB_MA_11 AW33SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28SB_MA_7 AW28SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33

SB_RAS# AU17

SB_WE# BF14

DDR SY

STEM

ME

MORY

B

5 OF 10U35E

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

DDR SY

STEM

ME

MORY

B

5 OF 10U35E

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

SA_DQ_0AJ38SA_DQ_1AJ41

SA_DQ_10AU40SA_DQ_11AT38SA_DQ_12AN41SA_DQ_13AN39SA_DQ_14AU44SA_DQ_15AU42SA_DQ_16AV39SA_DQ_17AY44SA_DQ_18BA40SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41SA_DQ_21AY43SA_DQ_22BB41SA_DQ_23BC40SA_DQ_24AY37SA_DQ_25BD38SA_DQ_26AV37SA_DQ_27AT36SA_DQ_28AY38SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36SA_DQ_31AW36SA_DQ_32BD13SA_DQ_33AU11SA_DQ_34BC11SA_DQ_35BA12SA_DQ_36AU13SA_DQ_37AV13SA_DQ_38BD12SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9SA_DQ_41BA9SA_DQ_42AU10SA_DQ_43AV9SA_DQ_44BA11SA_DQ_45BD9SA_DQ_46AY8SA_DQ_47BA6SA_DQ_48AV5SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9SA_DQ_51AN8SA_DQ_52AU5SA_DQ_53AU6SA_DQ_54AT5SA_DQ_55AN10SA_DQ_56AM11SA_DQ_57AM5SA_DQ_58AJ9SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12SA_DQ_61AM13SA_DQ_62AJ11SA_DQ_63AJ12

SA_DQ_7AM42SA_DQ_8AN43SA_DQ_9AN44

SA_BS_0 BD21SA_BS_1 BG18SA_BS_2 AT25

SA_CAS# BD20

SA_DM_0 AM37SA_DM_1 AT41SA_DM_2 AY41SA_DM_3 AU39SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44SA_DQS_1 AT44SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7

SA_DM_7 AJ5

SA_DQS#_0 AJ43SA_DQS#_1 AT43SA_DQS#_2 BA44SA_DQS#_3 BD37SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9SA_DQS#_7 AM8

SA_MA_0 BA21SA_MA_1 BC24

SA_MA_10 BC21SA_MA_11 BG26SA_MA_12 BH26SA_MA_13 BH17

SA_MA_2 BG24SA_MA_3 BH24SA_MA_4 BG25SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27SA_MA_8 BF25SA_MA_9 AW24

SA_RAS# BB20

SA_WE# AY20

SA_MA_14 AY25DDR SY

STEM

ME

MORY

A

4 OF 10U35D

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

DDR SY

STEM

ME

MORY

A

4 OF 10U35D

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SM_LF6_GMCHSM_LF7_GMCH

SM_LF1_GMCHSM_LF2_GMCHSM_LF3_GMCHSM_LF4_GMCHSM_LF5_GMCH

VCC_GMCH_35

1D8V_S3

1D05V_S0

1D05V_S0

1D8V_S3

1D05V_S0

1D05V_S0

1D05V_S0

Title


Date: Sheet of


Cantiga (4 of 6)_POWER9 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

FOR VCC SM

Place on the Edge

Place CAP whereLVDS and DDR2 taps

Coupling CAP 370 mils from the Edge

Coupling CAP

Place on the Edge Coupling CAP

place near Cantiga

667MTS 2400mA800MTS 3000mA

1118 delete TC27SB

12

TC21ST220U2VBM-3GP

DYTC21

ST220U2VBM-3GP

DY

12

C246 SCD

47U16V3ZY-3G

P

C246 SCD

47U16V3ZY-3G

P

12

C136

SCD

22U1

0V2K

X-1G

P

C136

SCD

22U1

0V2K

X-1G

P

12

C112SC10U

6D3V5M

X-3GP

DY

C112SC10U

6D3V5M

X-3GP

DY

12

C175SC1U

10V3ZY-6GP

C175SC1U

10V3ZY-6GP

1 2G9

GAP-CLOSE-PWR

G9

GAP-CLOSE-PWR

12

C111SC10U

6D3V5M

X-3GP

DY

C111SC10U

6D3V5M

X-3GP

DY

12

C208SC10U

6D3V5M

X-3GP

C208SC10U

6D3V5M

X-3GP


12

C164SC10U

6D3V5M

X-3GP

DY

C164SC10U

6D3V5M

X-3GP

DY

12

C456SC10U

6D3V5M

X-3GP

DY

C456SC10U

6D3V5M

X-3GP

DY

12

C235 SC1U

10V3KX-3GP

C235 SC1U

10V3KX-3GP

12

C455SC10U

6D3V5M

X-3GP

DY

C455SC10U

6D3V5M

X-3GP

DY

12

C194SCD

1U10V2KX-4G

P

C194SCD

1U10V2KX-4G

P 12

C450SCD

1U10V2KX-4G

P

DY

C450SCD

1U10V2KX-4G

P

DY

VCC_NCTF AM32

VCC_NCTF AC30

VCC_NCTF AJ29

VCC_NCTF AK25

VCC_NCTF AA32VCC_NCTF Y32VCC_NCTF W32VCC_NCTF U32VCC_NCTF AM30VCC_NCTF AL30VCC_NCTF AK30

VCC_NCTF AG30VCC_NCTF AF30VCC_NCTF AE30

VCC_NCTF AL32

VCC_NCTF W30VCC_NCTF V30

VCC_NCTF AK32

VCC_NCTF AH29VCC_NCTF AG29VCC_NCTF AE29

VCC_NCTF AL28VCC_NCTF AK28VCC_NCTF AL26VCC_NCTF AK26

VCC_NCTF AJ32

VCC_NCTF AK24

VCC_NCTF AH32VCC_NCTF AG32VCC_NCTF AE32VCC_NCTF AC32

VCC_NCTF AC29VCC_NCTF AA29VCC_NCTF Y29VCC_NCTF W29VCC_NCTF V29

VCC_NCTF U30VCC_NCTF AL29VCC_NCTF AK29

VCC_NCTF AH30

VCC_NCTF AB30VCC_NCTF AA30VCC_NCTF Y30

VCCAG34VCCAC34VCCAB34VCCAA34VCCY34VCCV34VCCU34VCCAM33VCCAK33VCCAJ33VCCAG33VCCAF33

VCCAE33VCCAC33VCCAA33VCCY33VCCW33VCCV33VCCU33VCCAH28VCCAF28VCCAC28VCCAA28VCCAJ26VCCAG26VCCAE26VCCAC26VCCAH25VCCAG25VCCAF25VCCAG24VCCAJ23VCCAH23VCCAF23

VCCT32

VCC_NCTF AK23

POW

ERVCC NCTF

VCC CORE

6 OF 10U35F

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

POW

ERVCC NCTF

VCC CORE

6 OF 10U35F

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

12

C253 SC1U

10V3KX-3GP

C253 SC1U

10V3KX-3GP

12

C210SC10U

6D3V5M

X-3GP

DY

C210SC10U

6D3V5M

X-3GP

DY

12

C140 SCD

1U10V2KX-4G

P

C140 SCD

1U10V2KX-4G

P

12

C193SCD

1U10V2KX-4G

P

C193SCD

1U10V2KX-4G

P1

TP32 TPAD14-GPTP32 TPAD14-GP

12

C153 SCD

1U10V2KX-4G

P

C153 SCD

1U10V2KX-4G

P

12

C207SC10U

6D3V5M

X-3GP

DY

C207SC10U

6D3V5M

X-3GP

DY

12

C202SCD

1U10V2KX-4G

P

DYC202SC

D1U

10V2KX-4GP

DY

12

C177SCD

1U10V2KX-4G

P

C177SCD

1U10V2KX-4G

P

12

C145SCD

1U10V2KX-4G

P

C145SCD

1U10V2KX-4G

P

VCC_SMAY32

VCC_SMBF31

VCC_SMAW29

VCC_SMBD32VCC_SMBC32VCC_SMBB32VCC_SMBA32

VCC_SMAW32VCC_SMAV32VCC_SMAU32VCC_SMAT32VCC_SMAR32VCC_SMAP32VCC_SMAN32VCC_SMBH31VCC_SMBG31

VCC_SMAN33

VCC_SMBG30VCC_SMBH29VCC_SMBG29VCC_SMBF29VCC_SMBD29VCC_SMBC29VCC_SMBB29VCC_SMBA29VCC_SMAY29

VCC_SMBH32

VCC_SMAV29VCC_SMAU29VCC_SMAT29VCC_SMAR29

VCC_AXG_NCTF V23VCC_AXG_NCTF AM21VCC_AXG_NCTF AL21VCC_AXG_NCTF AK21VCC_AXG_NCTF W21VCC_AXG_NCTF V21VCC_AXG_NCTF U21VCC_AXG_NCTF AM20VCC_AXG_NCTF AK20VCC_AXG_NCTF W20

VCC_AXG_NCTF V28

VCC_AXG_NCTF U20VCC_AXG_NCTF AM19VCC_AXG_NCTF AL19VCC_AXG_NCTF AK19VCC_AXG_NCTF AJ19VCC_AXG_NCTF AH19VCC_AXG_NCTF AG19VCC_AXG_NCTF AF19VCC_AXG_NCTF AE19VCC_AXG_NCTF AB19

VCC_AXG_NCTF W26

VCC_AXG_NCTF AA19VCC_AXG_NCTF Y19VCC_AXG_NCTF W19VCC_AXG_NCTF V19VCC_AXG_NCTF U19VCC_AXG_NCTF AM17VCC_AXG_NCTF AK17VCC_AXG_NCTF AH17VCC_AXG_NCTF AG17VCC_AXG_NCTF AF17

VCC_AXG_NCTF V26

VCC_AXG_NCTF AE17VCC_AXG_NCTF AC17VCC_AXG_NCTF AB17VCC_AXG_NCTF Y17VCC_AXG_NCTF W17VCC_AXG_NCTF V17VCC_AXG_NCTF AM16VCC_AXG_NCTF AL16VCC_AXG_NCTF AK16VCC_AXG_NCTF AJ16

VCC_AXG_NCTF W25

VCC_AXG_NCTF AH16VCC_AXG_NCTF AG16VCC_AXG_NCTF AF16VCC_AXG_NCTF AE16VCC_AXG_NCTF AC16VCC_AXG_NCTF AB16VCC_AXG_NCTF AA16

VCC_AXG_NCTF V25VCC_AXG_NCTF W24VCC_AXG_NCTF V24VCC_AXG_NCTF W23

VCC_SMAP29

VCC_SMBG32VCC_SMBF32

VCC_AXG_NCTF W28VCC_SMAP33

VCC_AXGY26VCC_AXGAE25VCC_AXGAB25VCC_AXGAA25VCC_AXGAE24VCC_AXGAC24VCC_AXGAA24VCC_AXGY24VCC_AXGAE23VCC_AXGAC23VCC_AXGAB23VCC_AXGAA23VCC_AXGAJ21VCC_AXGAG21VCC_AXGAE21VCC_AXGAC21VCC_AXGAA21VCC_AXGY21VCC_AXGAH20VCC_AXGAF20VCC_AXGAE20VCC_AXGAC20VCC_AXGAB20VCC_AXGAA20VCC_AXGT17

VCC_AXGAM15VCC_AXGAL15

VCC_AXGAJ15VCC_AXGAH15

VCC_AXGAF15VCC_AXGAB15

VCC_SM_LF AV44VCC_SM_LF BA37VCC_SM_LF AM40VCC_SM_LF AV21VCC_SM_LF AY5VCC_SM_LF AM10VCC_SM_LF BB13

VCC_AXGT16

VCC_AXGAG15

VCC_AXGAA15VCC_AXGY15VCC_AXGV15VCC_AXGU15VCC_AXGAN14VCC_AXGAM14VCC_AXGU14VCC_AXGT14

VCC_AXG_SENSEAJ14VSS_AXG_SENSEAH14

VCC_AXG_NCTF Y16VCC_AXG_NCTF W16VCC_AXG_NCTF V16VCC_AXG_NCTF U16

VCC_SM/NCBA36VCC_SM/NCBB24VCC_SM/NCBD16VCC_SM/NCBB21VCC_SM/NCAW16VCC_SM/NCAW13VCC_SM/NCAT13

VCC_AXGAE15

POW

ERVCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

7 OF 10U35G


POW

ERVCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

7 OF 10U35G


12

C172 SCD

22U10V2KX-1G

P

C172 SCD

22U10V2KX-1G

P

12

C211SC10U

6D3V5M

X-3GP

C211SC10U

6D3V5M

X-3GP

12

C144SCD

1U10V2KX-4G

P

DY

C144SCD

1U10V2KX-4G

P

DY

12

C225SCD

1U10V2KX-4G

P

C225SCD

1U10V2KX-4G

P

12

C162

SC10U

6D3V5M

X-3GP

C162

SC10U

6D3V5M

X-3GP

12

C183

SC10U

6D3V5M

X-3GP

C183

SC10U

6D3V5M

X-3GP

12

C163

SC10U

6D3V5M

X-3GP

DY

C163

SC10U

6D3V5M

X-3GP

DY

12

C203SCD

1U10V2KX-4G

P

C203SCD

1U10V2KX-4G

P

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_VCCA_HPLL

M_VCCA_MPLL

M_VCCA_DPLLA

M_VCCA_DPLLB

1D8V_TXLVDS_S3

1D05V_RUN_PEGPLL

1D5VRUN_QDAC

VTTLF1VTTLF2VTTLF3

1D05V_HV_S0

M_VCCA_DAC_BG

M_VCCA_DPLLB

M_VCCA_DPLLA

M_VCCA_MPLL

M_VCCA_HPLL

1D05V_RUN_PEGPLL

3D3V_CRTDAC_S0

1D8V_SUS_SM_CK_RC

1D5VRUN_QDAC

1D05V_RUN_PEGPLL

1D8V_TXLVDS_S3

1D8V_S3

1D05V_S0

1D05V_S0

1D8V_TXLVDS_S3

3D3V_HV_S0

1D8V_S3

1D8V_S31D8V_SUS_SM_CK

1D05V_S0

1D05V_S0

3D3V_S0 3D3V_HV_S0

3D3V_S0_DAC

3D3V_S0_DAC

1D5V_S0

1D5V_S0

1D05V_S0

1D05V_S0

1D05V_S0

1D05V_S0

1D05V_S0

3D3V_S0_DAC

5V_S0 3D3V_S0_DAC

1D05V_S0

1D05V_S0

1D5V_S0

Title


Date: Sheet of


Cantiga (5 of 6)_POWER


Title


Date: Sheet of




Title


Date: Sheet of




1782mA

456mA

106mA

119mA

124mA

322mA

852mA73mA

5mA

120ohm 100MHz

120ohm 100MHz

220ohm 100MHz

180ohm 100MHz

65mA

65mA

24mA

139.2mA

13.2mA

720mA

26mA

35mA

50mA

157.2mA

50mA

60.3mA

Imax = 300 mA

79mA

1015 modify component size of R252

SB 1113 modify 2nd of U44

1120 modify EC78SB

1222 modify R2521

1229 modify U441

12

C214SC4D

7U6D3V3KX-GP

C214SC4D

7U6D3V3KX-GP

1 2R81

0R0603-PAD

R81

0R0603-PAD

1 2L5

SBK160808T-221Y-N-GP

2nd = 68.00217.52168.00119.111

L5


2nd = 68.00217.52168.00119.111

12

C485SC22U16V0KX-1GPC485SC22U16V0KX-1GP

12

C220SC4D

7U6D3V3KX-GP

C220SC4D

7U6D3V3KX-GP

12R254

0R0402-PAD

R254

0R0402-PAD

12

C169 SC10U6D3V5M

X-3GP

C169 SC10U6D3V5M

X-3GP

12

C254SC1U10V3KX-3GPC254SC1U10V3KX-3GP

12


12


12

C469SCD1U10V2KX-4GPDY


12

C222 SC22U6D3V5M

X-2GP

C222 SC22U6D3V5M

X-2GP

12 C166SCD1U10V2KX-4GP

C166SCD1U10V2KX-4GP

12

C239SCD1U10V2KX-4GP

C239SCD1U10V2KX-4GP

12

C482SCD01U16V2KX-3GPC482SCD01U16V2KX-3GP 1

2C262SC1KP50V2KX-1GPC262

SC1KP50V2KX-1GP

2

1C139

SCD

47U6D3V2KX-GP

2

1C139

SCD

47U6D3V2KX-GP

12



1 2R249

HFB1608VF-102-GP

2nd = 68.00084.A0168.00331.011

R249

HFB1608VF-102-GP

2nd = 68.00084.A0168.00331.011

2

1 C135SCD

47U6D3V2KX-GP

DY2

1 C135SCD

47U6D3V2KX-GP

DY

12

C457 SC22U6D3V5M

X-2GP

DY

C457 SC22U6D3V5M

X-2GP

DY

12

C497SCD

1U10V2KX-4G

P

C497SCD

1U10V2KX-4G

P

12

C178 SC10U6D3V5M

X-3GP

DY

C178 SC10U6D3V5M

X-3GP

DY

12

C209SC4D

7U6D3V3KX-GP

C209SC4D

7U6D3V3KX-GP

12

C263SC10U6D3V5M

X-3GP

C263SC10U6D3V5M

X-3GP

12

C261SCD1U10V2KX-4GP

C261SCD1U10V2KX-4GP

12

C213SC2D

2U6D3V3MX-1-G

P

C213SC2D

2U6D3V3MX-1-G

P

12

C160 SC1U

10V3KX-3GP

C160 SC1U

10V3KX-3GP

12

C267SC10U6D3V5M

X-3GP

C267SC10U6D3V5M

X-3GP

1 2

L4

PBY160808T-181Y-GP68.00206.041

2nd = 68.00214.051

L4

PBY160808T-181Y-GP68.00206.041

2nd = 68.00214.051 21

C133

SCD

47U6D3V2KX-GP

2

1C133

SCD

47U6D3V2KX-GP

12

EC77SC1U

16V3ZY-GP

DY

EC77SC1U

16V3ZY-GP

DY

12

C492SCD01U

16V2KX-3GP

C492SCD01U

16V2KX-3GP

12

C466 SC4D

7U6D3V3KX-GP

DY

C466 SC4D

7U6D3V3KX-GP

DY

12



12

C134SCD

1U10V2KX-4G

P

C134SCD

1U10V2KX-4G

P

12

C157 SC1U

10V3KX-3GP

C157 SC1U

10V3KX-3GP

12

C181

SCD1U10V2KX-4GP

C181

SCD1U10V2KX-4GP

1 2R82

1R2F-GP

R82

1R2F-GP

12


12

C244SC10U6D3V5MX-3GPC244SC10U6D3V5MX-3GP

12C463

SC10U6D3V5M

X-3GP

DYC463 SC10U6D3V5MX-3G

P

DY

1

2

3

D18

BAT54-5-GP83.BAT54.D81

2nd = 83.BAT54.X813rd = 83.00054.Z81

D18

BAT54-5-GP83.BAT54.D81

2nd = 83.BAT54.X813rd = 83.00054.Z81

2

1C467

SCD47U6D3V2KX-GP 2

1C467

SCD47U6D3V2KX-GP

12


1 2R116

0R0603-PAD

R116

0R0603-PAD

12 EC78

SC4D7U10V3KX-GP

EC78

SC4D7U10V3KX-GP

12

C480SC10U6D3V5MX-3GPDY

C480SC10U6D3V5MX-3GPDY1

2

C161 SC4D

7U6D3V3KX-GP

DYC161 SC

4D7U6D3V3KX-G

P

DY

12

C198SC10U6D3V5M

X-3GP

C198SC10U6D3V5M

X-3GP

12


VTT V3VTT U3VTT V2VTT U2

VCCA_PEG_BGAD48

VCCA_PEG_PLLAA48

VCCA_CRT_DACB27VCCA_CRT_DACA26

VCCA_DPLLAF47

VCCA_DPLLBL48

VCCA_HPLLAD1

VCCA_LVDSJ48

VCCA_MPLLAE1

VCCA_TV_DACB24VCCA_TV_DACA24

VCCD_PEG_PLLAA47

VTT U6VTT T6VTT U5VTT T5

VTT T8VTT U7VTT T7

VCCD_HPLLAF1

VTT U13VTT T13

VTT T12VTT U11VTT T11VTT U10VTT T10VTT U9VTT T9VTT U8

VTT U12

VCCA_SM_CKAP28VCCA_SM_CKAN28

VCCA_DAC_BGA25

VCCD_TVDACM25

VTTLF A8VTTLF L1VTTLF AB2

VCC_DMI AH48VCC_DMI AF48

VCC_SM_CK BF21VCC_SM_CK BH20VCC_SM_CK BG20VCC_SM_CK BF20

VCCD_LVDSM38

VCCD_QDACL28

VCC_AXF B22VCC_AXF B21VCC_AXF A21

VCCA_SMAR20VCCA_SMAP20VCCA_SMAN20VCCA_SMAR17VCCA_SMAP17

VCCA_SMAT16VCCA_SMAR16VCCA_SMAP16

VCC_TX_LVDS K47

VSSA_LVDSJ47

VCC_HV C35VCC_HV B35

VCC_PEG V48

VCCD_LVDSL37

VCC_PEG U48VCC_PEG V47VCC_PEG U47VCC_PEG U46

VCCA_SMAN17

VCCA_SM_CKAP25VCCA_SM_CKAN25VCCA_SM_CKAN24VCCA_SM_CK_NCTFAM28VCCA_SM_CK_NCTFAM26VCCA_SM_CK_NCTFAM25VCCA_SM_CK_NCTFAL25VCCA_SM_CK_NCTFAM24VCCA_SM_CK_NCTFAL24VCCA_SM_CK_NCTFAM23

VTT T2VTT V1VTT U1

VCC_HV A35

VCC_DMI AH47VCC_DMI AG47

VSSA_DAC_BGB25

VCCA_SM_CK_NCTFAL23

VCC_HDAA32

POWER

CRT

PLL

A PEG

A SM

TV

D TV/C

RT

LVDS

VTTLF

PEG

SM CK

AXF

VTT

DMI

HV

A CK

A LVDS

HDA

8 OF 10U35H


POWER

CRT

PLL

A PEG

A SM

TV

D TV/C

RT

LVDS

VTTLF

PEG

SM CK

AXF

VTT

DMI

HV

A CK

A LVDS

HDA

8 OF 10U35H


12

C481SC1U

10V3KX-3GP

C481SC1U

10V3KX-3GP

12

C464

SC4D

7U6D3V3KX-GP

C464

SC4D

7U6D3V3KX-GP

1 2

R25510R2F-L-GPR25510R2F-L-GP

12


1 2


12 C468SCD1U10V2KX-4GP

C468SCD1U10V2KX-4GP

VIN1GND2EN3 NC#4 4

VOUT 5

U44

RT9198-33GBR-GP74.09198.Q7F

2nd = 74.09091.J3F

U44

RT9198-33GBR-GP74.09198.Q7F

2nd = 74.09091.J3F

12

C184 SC2D

2U6D3V3MX-1-G

P

DY

C184 SC2D

2U6D3V3MX-1-G

P

DY

12

C218SCD

1U10V2KX-4G

P

DYC218SC

D1U

10V2KX-4GP

DY

1 2R108

0R0603-PAD

R108

0R0603-PAD

12



1 2L13


2nd = 68.00217.16168.00119.101

L13


2nd = 68.00217.16168.00119.101

1 2R2520R0402-PAD

R2520R0402-PAD

1 2L12


2nd = 68.00217.16168.00119.101

L12


2nd = 68.00217.16168.00119.101

12



1 2R104

0R0603-PAD

R104

0R0603-PAD

12

C180SCD

1U10V2KX-4G

P

C180SCD

1U10V2KX-4G

P

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Cantiga (6 of 6)11 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

1 TP66TPAD14-GP TP66TPAD14-GP1 TP65TPAD14-GP TP65TPAD14-GP1 TP74TPAD14-GP TP74TPAD14-GP1 TP67TPAD14-GP TP67TPAD14-GP1 TP71TPAD14-GP TP71TPAD14-GP

VSSBG21

VSSAW21VSSAU21VSSAP21VSSAN21VSSAH21VSSAF21VSSAB21VSSR21VSSM21VSSJ21VSSG21VSSBC20VSSBA20VSSAW20VSSAT20VSSAJ20VSSAG20VSSY20VSSN20VSSK20VSSF20VSSC20VSSA20VSSBG19VSSA18VSSBG17VSSBC17VSSAW17VSSAT17VSSR17VSSM17VSSH17VSSC17

VSSBA16

VSSAU16VSSAN16VSSN16VSSK16VSSG16VSSE16VSSBG15

VSSW15VSSA15VSSBG14VSSAA14VSSC14VSSBG13VSSBC13VSSBA13

VSSAN13VSSAJ13VSSAE13VSSN13VSSL13VSSG13VSSE13VSSBF12VSSAV12VSSAT12VSSAM12VSSAA12VSSJ12VSSA12VSSBD11VSSBB11VSSAY11VSSAN11VSSAH11

VSSY11VSSN11VSSG11VSSC11VSSBG10VSSAV10VSSAT10VSSAJ10VSSAE10VSSAA10

VSSBH8VSSB9VSSG9VSSAD9VSSAM9VSSAN9VSSBC9VSSM10VSSBF9

VSS AH8VSS Y8VSS L8VSS E8VSS B8VSS AY7VSS AU7VSS AN7VSS AJ7VSS AE7VSS AA7VSS N7VSS J7VSS BG6VSS BD6VSS AV6VSS AT6

VSSAC15

VSS AM6VSS M6VSS C6VSS BA5VSS AH5VSS AD5VSS Y5VSS L5VSS J5VSS H5VSS F5VSS BE4

VSS BC3VSS AV3VSS AL3

VSS_NCTF AF32VSS_NCTF AB32VSS_NCTF V32VSS_NCTF AJ30VSS_NCTF AM29VSS_NCTF AF29VSS_NCTF AB29VSS_NCTF U26VSS_NCTF U23VSS_NCTF AL20VSS_NCTF V20VSS_NCTF AC19VSS_NCTF AL17VSS_NCTF AJ17VSS_NCTF AA17VSS_NCTF U17

NCTF_VSS_SCB#BH48 BH48NCTF_VSS_SCB#BH1 BH1NCTF_VSS_SCB#A48 A48NCTF_VSS_SCB#C1 C1NCTF_VSS_SCB#A3 A3

NC#E1 E1NC#D2 D2NC#C3 C3NC#B4 B4NC#A5 A5NC#A6 A6

NC#A43 A43NC#A44 A44NC#B45 B45NC#C46 C46NC#D47 D47NC#B47 B47NC#A46 A46NC#F48 F48NC#E48 E48NC#C48 C48NC#B48 B48

VSS R3VSS P3

VSS BA2

VSS AR2VSS AU2

VSS AP2

VSS F3

VSS AW2

VSS AE2VSS AF2VSS AH2VSS AJ2

VSS AD2VSS AC2VSS Y2VSS M2VSS K2VSS AM1VSS AA1VSS P1VSS H1

VSSBB8VSSAV8VSSAT8

VSS U24VSS U28VSS U25VSS U29

VSSL12

VSS

VSS NCTF

VSS SCB

NC

10 OF 10

NCTF

TES

T PI

N:A3

,C1,

A48,

BH1,

BH48

U35J


VSS

VSS NCTF

VSS SCB

NC

10 OF 10

NCTF

TES

T PI

N:A3

,C1,

A48,

BH1,

BH48

U35J


VSSAU48

VSS A23

VSSAR48VSSAL48VSSBB47VSSAW47VSSAN47VSSAJ47VSSAF47VSSAD47VSSAB47VSSY47VSST47VSSN47VSSL47VSSG47VSSBD46VSSBA46

VSSAV46VSSAR46VSSAM46VSSV46VSSR46VSSP46VSSH46VSSF46VSSBF44VSSAH44VSSAD44VSSAA44VSSY44VSSU44VSST44VSSM44VSSF44VSSBC43VSSAV43VSSAU43VSSAM43VSSJ43VSSC43VSSBG42VSSAY42VSSAT42VSSAN42VSSAJ42VSSAE42VSSN42VSSL42VSSBD41VSSAU41VSSAM41VSSAH41VSSAD41VSSAA41VSSY41VSSU41VSST41VSSM41VSSG41VSSB41VSSBG40VSSBB40VSSAV40VSSAN40VSSH40VSSE40VSSAT39VSSAM39VSSAJ39VSSAE39VSSN39VSSL39VSSB39VSSBH38VSSBC38VSSBA38VSSAU38VSSAH38VSSAD38VSSAA38VSSY38VSSU38VSST38VSSJ38VSSF38VSSC38

VSSBD36

VSS AM36VSS AE36VSS P36VSS L36VSS J36VSS F36VSS B36VSS AH35VSS AA35VSS Y35VSS U35VSS T35VSS BF34VSS AM34VSS AJ34VSS AF34VSS AE34VSS W34VSS B34VSS A34VSS BG33VSS BC33VSS BA33VSS AV33VSS AR33VSS AL33VSS AH33VSS AB33VSS P33VSS L33VSS H33VSS N32VSS K32VSS F32VSS C32VSS A31VSS AN29VSS T29VSS N29VSS K29VSS H29VSS F29VSS A29VSS BG28VSS BD28VSS BA28VSS AV28VSS AT28VSS AR28VSS AJ28VSS AG28VSS AE28VSS AB28VSS Y28VSS P28VSS K28VSS H28VSS F28VSS C28VSS BF26VSS AH26VSS AF26VSS AB26VSS AA26VSS C26VSS B26VSS BH25VSS BD25VSS BB25VSS AV25VSS AR25VSS AJ25VSS AC25VSS Y25VSS N25VSS L25VSS J25VSS G25VSS E25VSS BF24

VSSBF37VSSBB37VSSAW37VSSAT37VSSAN37VSSAJ37VSSH37VSSC37VSSBG36

VSSAU36

VSS AT24

VSS AH24

VSS AB24

VSS L24

VSSAY46

VSS G24

VSS E24

VSS AG23

VSS B23

VSS AY24

VSS AJ24

VSS AF24

VSS R24

VSS K24VSS J24

VSS F24

VSS BH23

VSS Y23VSSAK15

VSS AD12

VSS AJ6

VSS

9 OF 10U35I


VSS

9 OF 10U35I


?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

INTRUDER#

H_THERMTRIP_R

LAN_RSTYNC

RTC

_BAT

_R

LAN100_SLP

RTC_RST#

INTVRMEN

RTC_BAT

ACZ_RST#_R

ACZ_SDATAOUT_R

H_FERR#_R

H_INIT#_G

PM_THRMTRIP-A#

RTC_X1

RTC_X2

H_FERR#_R

INTVRMEN LAN100_SLP

FWH_INIT#H_INIT#

LPC_LAD[0..3]

SATARBIAS

SRTC_RST#

LDRQ0#

H_DPSLP#

3D3V_LDRQ1_S0

LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3

ICH_TP8

H_DPRSTP#

H_PWRGD

ACZ_BIT_CLK_R

ACZ_RST#_R

ACZ_SDATAOUT_R

SATA_RXN0_CSATA_RXP0_CSATA_TXN0_CSATA_TXP0_C

SATA_RXN1_CSATA_RXP1_CSATA_TXN1_CSATA_TXP1_C

HDA_DOCK_RST#

GLAN_COMP

HDA_DOCK_EN#

ACZ_BIT_CLK_RACZ_SYNC_R

GLAN_DOCK#

ACZ_SYNC_R

H_THERMTRIP_R

1D05V_S0

1D05V_S0 3D3V_S0

RTC_AUX_S5

3D3V_AUX_S5

1D5V_S0

3D3V_S0

RTC_AUX_S5 RTC_AUX_S5

1D05V_S0

1D05V_S0

GLAN_DOCK#13

H_FERR#4

CLK_PCIE_SATA# 3CLK_PCIE_SATA 3

SATA_TXN121SATA_TXP121

SATA_RXN121SATA_RXP121

ACZ_SDATAIN026

HDD_LED#33,38

SATA_TXN020SATA_TXP020

SATA_RXN020SATA_RXP020

LPC_LAD[0..3] 33,34

KBRCIN# 33

LPC_LFRAME# 33,34

H_IGNNE# 4

H_INIT# 4H_INTR 4

H_STPCLK# 4

H_NMI 4H_SMI# 4

KA20GATE 33H_A20M# 4

H_DPRSTP# 4,7,41H_DPSLP# 4

H_PWRGD 4,39,48

PM_THRMTRIP-A# 4,7,39

ACZ_BITCLK_AUDIO26

ACZ_SDATAOUT_AUDIO26ACZ_SYNC_AUDIO26

ACZ_RST#_AUDIO26

Title


Date: Sheet of


ICH9-M (1 of 4)_SATA/HDA/RTC12 52Thursday, May 07, 2009

LA14 SB

Title


Date: Sheet of



LA14 SB

Title


Date: Sheet of



LA14 SB

0915 add EC73 for EMI demand

1119 add G84 and C540

1117 delete MDC function(R231,R237,R232,R234)

1016 modify X2

1124 delete C540near DIMM door

integrated VccSus1_05,VccSus1_5,VccCL1_5

integrated VccLan1_05VccCL1_05

INTVRMEN

LAN100_SLP

High=Enable Low=Disable

High=Enable Low=Disable

1229 modify C76,C77 from 12pF to 15pF 1

Layout note: R373 needs to placedwithin 2" of ICH9, R379 must beplaced within 2" of R373 w/o stub

1224 modify RN541

HDD

ODD

1126 delete R230,R233,R235,R236 and RN63

SB

GLAN_COMP place within 500 mil of ICH9M

Place within 500 mils ofICH9 ball

SB

1 2C56 SCD01U50V2KX-1GPC56 SCD01U50V2KX-1GP

12

R1970R2J-2-GPDY R1970R2J-2-GPDY


TP50TPAD30

TP50TPAD30

12

C281SCD1U16V2ZY-2GP

DY C281SCD1U16V2ZY-2GP

DY

12 3

4

RN51SRN20KJ-GP-URN51SRN20KJ-GP-U

2

1

3

D16

CH715FPT-GP83.R0304.B81

2nd = 83.R2004.C81

D16

CH715FPT-GP83.R0304.B81

2nd = 83.R2004.C81


12

R200330KR2F-L-GPR200330KR2F-L-GP

1 2

R222200R2F-L-GP

DY

R222200R2F-L-GP

DY

12

EC65SC10P50V2JN-4GPDY


123 4X2

X-32D768KHZ-46GP82.30001.861

X2X-32D768KHZ-46GP

82.30001.861

12



12

R22356R2J-4-GPDYR22356R2J-4-GPDY

1 2

R22954D9R2F-L1-GP

DY R22954D9R2F-L1-GP

DY

123 4

RN55SRN10KJ-5-GP

DYRN55

SRN10KJ-5-GP

DY12

R199330KR2F-L-GPR199330KR2F-L-GP


1 TP25 TPAD14-GPTP25 TPAD14-GP

1 2R193 1MR2J-1-GPR193 1MR2J-1-GP


C

B

EQ24

MMBT3904-3-GP

DYQ24

MMBT3904-3-GP

DY

1234 5

678

RN54

SRN56J-5-GP

RN54

SRN56J-5-GP

12

R1980R2J-2-GPDY R1980R2J-2-GPDY

1 TP70 TPAD14-GPTP70 TPAD14-GP

1 2

C77

SC15P50V2JN-2-GP

C77

SC15P50V2JN-2-GP

12345

678

RN63

SRN47J-4-GP

RN63

SRN47J-4-GP

1 2R121

1KR2J-1-GP

R121

1KR2J-1-GP




1 2R20724D9R2F-L-GP

R20724D9R2F-L-GP

12R227

24D9R2F-L-GPR227

24D9R2F-L-GP

PWR 1GND 2NP1 NP1NP2 NP2

RTC1

BAT-CON2-1-GP-U62.70001.011

RTC1

BAT-CON2-1-GP-U62.70001.011

RTCX1C23RTCX2C24

INTVRMENB22INTRUDER#C22

GLAN_CLKE25

LAN_RSTSYNCC13

LAN_RXD0F14LAN_RXD1G13LAN_RXD2D14

LAN_TXD0D13LAN_TXD1D12LAN_TXD2E13

HDA_BIT_CLKAF6HDA_SYNCAH4

HDA_RST#AE7

HDA_SDIN0AF4HDA_SDIN1AG4HDA_SDIN2AH3

HDA_SDOUTAG5

SATALED#AG8

SATA0RXNAJ16SATA0RXPAH16SATA0TXNAF17SATA0TXPAG17

SATA1RXNAH13SATA1RXPAJ13SATA1TXNAG14SATA1TXPAF14

SATA_CLKN AH18SATA_CLKP AJ18

SATARBIAS# AJ7SATARBIAS AH7

FWH0/LAD0 K5FWH1/LAD1 K4FWH2/LAD2 L6FWH3/LAD3 K2

LDRQ0# J3LDRQ1#/GPIO23 J1

FWH4/LFRAME# K3

A20GATE N7A20M# AJ27

DPRSTP# AJ25DPSLP# AE23

FERR# AJ26

CPUPWRGD AD22

IGNNE# AF25

INIT# AE22INTR AG25

RCIN# L3

SMI# AF24NMI AF23

STPCLK# AH27

THRMTRIP# AG26

RTCRST#A25

GLAN_DOCK#/GPIO56B10

GLAN_COMPOB27GLAN_COMPIB28

HDA_SDIN3AE5

SATA4TXN AG12SATA4RXN AH11

SATA4TXP AF12SATA4RXP AJ11

PECI AG27

HDA_DOCK_EN#/GPIO33AG7HDA_DOCK_RST#/GPIO34AE8

LAN100_SLPA22

SATA5RXN AH9SATA5RXP AJ9SATA5TXN AE10SATA5TXP AF10

SRTCRST#F20

RTC

LAN /

GLAN

IHDA

SATA

LPC

CPU

1 OF 6U16A

ICH9M-GP-NF71.ICH9M.00U

RTC

LAN /

GLAN

IHDA

SATA

LPC

CPU

1 OF 6U16A

ICH9M-GP-NF71.ICH9M.00U

12

C396SC1U16V3ZY-GP

C396SC1U16V3ZY-GP

12

C392SC1U16V3ZY-GPC392SC1U16V3ZY-GP


12

R5710MR2J-L-GPR5710MR2J-L-GP


1 2

C76

SC15P50V2JN-2-GP

C76

SC15P50V2JN-2-GP

12

C391SC1U16V3ZY-GPC391SC1U16V3ZY-GP


21

G84

GAP-OPEN

G84

GAP-OPEN

1 2R228 8K2R2J-3-GP

DYR228 8K2R2J-3-GP

DY

?

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_REQ#1

INT_PIRQA#PCI_LOCK#

PCI_FRAME#

INT_SERIRQ

PM_CLKRUN#

INT_PIRQD#

PCI_STOP#

INT_PIRQE#PCI_IRDY#

INT_PIRQF#PCI_PERR#

PCI_DEVSEL#

PCI_REQ#3

PCI_SERR#

INT_PIRQH#

INT_PIRQB# ECSCI#_1

PCI_REQ#2

INT_PIRQC#PCI_REQ#0

PCI_TRDY#INT_PIRQG#

ICH_TP3

SDATAOUT1

ICH_TP7

SMLINK1SMLINK0SMB_LINK_ALERT#

SMB_ALERT#

PM_RI#

DBRESET#PM_SUS_STAT#

GPIO12

PSW_CLR#

GPIO20

RSMRST#_SB

PM_DPRSLPVR

PM_BATLOW#_R

SATA0GPSATA1GPGPIO36

S4_STATE#

GPIO37

SLPS5#

PM_SLP_M#

CL_VREF1_ICHCL_VREF0_ICH

TXP2TXN2

TXP1TXN1

USB_OC#7

USB_OC#9USB_OC#8

USB_OC#1USB_OC#2USB_OC#3

USB_OC#5USB_OC#6

USB_RBIAS_PN

DMI_IRCOMP_R

ECSWI#

DBRESET#

USB_OC#2

USB_OC#0 GPIO10

USB_OC#3PCIE_WAKE#

PM_BATLOW#_RSMB_LINK_ALERT#

PM_RI#USB_OC#4

SMB_ALERT#

USB_OC#7

USB_OC#6

USB_OC#5USB_OC#1

RSMRST#_SB

GPIO10GPIO24

USB_OC#10USB_OC#11

GPIO57

SB_GPIO13

INT_PIRQB#INT_PIRQC#INT_PIRQD#

INT_PIRQA#

PCI_LOCK#PCI_SERR#PCI_STOP#PCI_TRDY#PCI_FRAME#

PCI_PERR#

ICH_PME#

INT_PIRQE#INT_PIRQF#INT_PIRQG#INT_PIRQH#

PLT_RST#_R

PCI_IRDY#PCI_PAR

PCI_DEVSEL#

PCI_REQ#0

PCI_REQ#2

PCI_REQ#1

PCI_REQ#3

GPIO49

USB_OC#0

USB_OC#4

GPIO14

GPIO18

PCI_GNT#0

SPI_CS#1

PCI_GNT#3

PCI_GNT#0

SPI_CS#1

PCI_GNT#3

SB_GPIO1

GPIO9

SMLINK1SMLINK0

RSMRST#_SB

USB_OC#11USB_OC#10

USB_OC#8USB_OC#9

GPIO14SB_GPIO13

SDATAOUT1

PWROK

GPIO57

SATA0GPSATA1GPGPIO36GPIO37

GPIO22

PWRBTN#_ICH

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S0

1D5V_S0

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_S5

ACZ_SPKR26MCH_ICH_SYNC#7

PCIE_RXN231PCIE_RXP231PCIE_TXN231PCIE_TXP231

PCIE_RXN124PCIE_RXP124PCIE_TXN124PCIE_TXP124

RSMRST#_KBC33

CL_DATA0 7

CL_CLK0 7

CL_RST#0 7

PWROK 7,39

CLK_PWRGD 3

PM_SUS_CLK 32

PM_PWRBTN# 33

PM_DPRSLPVR 7,41

PM_SLP_S4# 33,43,44

CLK_ICH14 3CLK48_ICH 3

PM_SLP_S3# 33,39,43,44

PWROK 7,39PM_STPPCI

wistron la14 rsb schematics

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