wireless sdr solutions: the challenge and promise of next...

Wireless SDR Solutions: The Challenge and Promise of Next

Generation Handsets

1 North Lexington Ave, 10th FloorWhite Plains, New York 10601

914-287-8500

John Glossner, Ph.D., Founder, CTO & EVP

Erdem Hokenek, Ph.D., Founder, Chief H/W Architect

Mayan Moudgill, Ph.D., Founder, Chief S/W [email protected]

mailto:[email protected]

http://www.SandbridgeTech.com

Agenda

Motivation for SDR

Market

Technology Requirements

Sandbridge Technologies’ Solution


The Challenges of an Industry

Cost3G is >10x more complex than 2G

but cost should be same, or even lessConvergence phone 2x complexity

WLAN, 2G, and 2.5G integration Traditionally implemented in HW

Moore’s law reduces cost 50% every 18 months6 years until the wireless multimedia is a real consumer market

Time-to-marketGPRS terminals were late

OEMs had to wait until bug free SoCs were available3G terminals will be late

OEMs have to wait until bug free SoCs with ‘reasonable’ power consumption are available


Multifunction Devices

TD-SCDMA

802.11b

802.11a

GSM

Bluetooth

GPRS

GPS

CDMA-2k

IS-95Java

WCDMA

IS-54

802.11g

Sandbridge’s reconfigurable baseband technology

minimizes silicon requirements and optimizes

flexibility

MP3

AAC

EDGE

PDC

Software Defined, SandblasterTM Mastered


Agenda

Motivation for SDR

Market




Programmable DSP Market

$0

$2

$4

$6

$8

$10

$12

2001 2002 2003 2004 2005 2006

Programmable DSP Market

Source: Forward Concepts 2002

CAGR: 21.8%

Billions


Agenda

Motivation for SDR

Market




Datarate Evolution

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

1.E+13

1980 1985 1990 1995 2000 2005

Voice Modems Data Modems Wireless Ethernet Fiber - TDM Fiber - WDM

G.lite

2.5G

3G

4G

V.90

ISDN

GSM

G.dmt

VDSL

8x2.5G

32x10G

160x10G80x10G

1G eth

1Gbps

1Mbps

1Tbps

1kbps


DSP Power/PerformanceDSP Performance vs. Power

(Log Log scale)

C55x

C203

C549

C5421

C5441

2181

2164

2173

21065L

16210

16291628 16091620

56652 5660256307

5600256812

SC140

SC140 FR500

FR300

1M/mW

1M/mW

5M/mW10M/mW

10M/mW

50M/mW

50M/mW

10

100

1000

10000

100000

10 100 1000

mWatts

MM

AC

/s

3G (10 GMAC/s)


Competitive PowerDSP Performance vs. Power

(Log Log scale)

C55x

C203

C549

C5421

C5441

SB9600

2181

2164

2173

21065L

16210

16291628 16091620

56652 5660256307

5600256812

SC140

SC140 FR500

FR300

1M/mW

1M/mW

5M/mW

5M/mW

10M/mW

10M/mW

50M/mW

50M/mW

10

100

1000

10000

100000

10 100 1000

mWatts

MM

AC

/s

100 GMAC/sec


Agenda

Motivation for SDR

Market




Sandbridge ApproachAvailable now Q3-03 Q1-04

High productivity C compiler70% time-to-market reductionUser-friendly Environment

SandBlasterTM DSP

ProgrammableUltra-low powerHigh-performanceMultithreaded

SandBlasterTM Tools

SB9600 Baseband

Scalable & Programmable

Integrated Sandblaster cores

Up to 2Mbit/sec data rate

40,000 RISC MIPS

10,000 MMACs

Low Cost 0.13um CMOS

Integrated protocol stack

Low Cost

Power Efficient

Ultra-high performance

Fully tested / validated

Dedicated Customer Support

Flexible and upgradeable

Multi-function System Solution


SandblasterTM Architecture Performs

CompilableDSP

Java ProcessorControl

Processor

SystemProductivityAdvantage

9-12+ months

C programmedLatency hiding architecture

3G Applications Standard 3G, xDSL, 802.11Control Stacks


Multithreaded DSP

High ParallelismVector / SIMD data parallelismMultiple instruction issueThread-level parallelism

Inter-Chip Connection Exte

rnal

Mem

ory


rnal

Mem

ory


rnal

Mem

ory

Thre

ad C

ache

Instruction Decode

Branch PC

MMU

CR

LR

CTR

Integer IQ

RegisterFileOffset

External MemoryExternal MemoryExternal MemoryData Memory

Data Buffer

MPY

VRABC

Vector File

MPY

VRABC

VectorFile

PABC

MPY

VectorFile

MPY

VectorFile

Vector IQ

Offset

SAT

VRABC VRABC

PABCPABCPABC

ACC ACC ACC ACC

RA RB

ADDADD ADD ADD ADD

ADD


Compiler Productivity

NEW

Compile

10x every 10 years

Signal Processing Applications Complexity

1E+3

10E+3

100E+3

1985 1995 2005

Line

s of

C C

ode

DesignAlgorithms

SandblasterTM Provides Dramatic Improvement

6-9 Months!

Map toFixed Point C

Write DSPSpecific C

Write DSPAssembly

Hand ScheduleOperations on DSP

Final Product Final Product

6-9 Months!


Compiler Optimizations

Loop Optimizations

Loop Invariant Code MotionStrength Reduction

Induction Variable EliminationLoop Splitting

Software Pipelining

Loop Optimizations

Loop Invariant Code MotionStrength Reduction

Induction Variable EliminationLoop Splitting

Software Pipelining

DSP Optimizations

Saturation ArithmeticFixed Point Semantic AnalysisBit-exact ETSI compliance

DSP Optimizations

Saturation ArithmeticFixed Point Semantic AnalysisBit-exact ETSI compliance

Vector Optimizations

Vector LoadsVector Stores

Vector ArithmeticVector Reduction

Saturating Vector Operations

Vector Optimizations

Vector LoadsVector Stores

Vector ArithmeticVector Reduction

Saturating Vector Operations

Scalar Optimizations

Range/type PropagationCommon Subexpression Elim.

Constant FoldingDead Code Elimination

Register Coloring

Scalar Optimizations

Range/type PropagationCommon Subexpression Elim.

Constant FoldingDead Code Elimination

Register Coloring

Interprocedural Opts.

Constant PropagationMemory Disambiguation

Function InliningAlias Analysis

Interprocedural Opts.

Constant PropagationMemory Disambiguation

Function InliningAlias Analysis


AMR Out of Box Results

AMR Encoder

0

100

200

300

400

500

600

700

SB TI C64x TI C62x SC140 ADI BlackFin

DSP's

Mhz

10 MHz


Simulation Technology

Compiled Simulator 100 MHz on high end x86JIT “Flash” compilationMulti-threaded supportedFunction level profiler

Non-intrusive

Up to 4 orders of magnitude fasterDramatic development time reductionSignificant productivity improvement

Cycle Accurate SimulatorUsed for Verification against VHDL modelProvides detailed statistics


Functional Simulator Speeds

Simulation Speed(log scale)

0.114 0.106

0.002

0.013

24.639

0.001

0.010

0.100

1.000

10.000

100.000

Mill

ions

of I

nstru

ctio

ns P

er S

econ

d

SB 24.639

TI C64x (Code Composer) 0.114

TI C62x(Code Composer) 0.106

SC140(Metrow erks) 0.002

ADI Blackfin (Visual DSP) 0.013

Results on 1Ghz laptop


Integration

IF

RF

MMI

APPLICATIONTASKS

PROTOCOLSTACK

DATA I/OLCD, KPD …

L1 CONTROL

L1 BASEBAND SW


Development Process

MATLAB physical layerEnd-to-end UTRAN + UEChannel modelsConfigurable via test-scriptsBER/FER measurement

Simulation level CFixed pointUE onlyFixed configurationPerformance measurement

Product level CPartitioned for real-timeUsing actual peripheralsIntegrate with L1 control + L2/L3


Real-time WCDMA Performance

FILTER

RAKE Searcher

PN BT#1 PN BT#2 PN BT#3

De-Scrambler

Path Table Building

Timing Management

De-SpreadDe-SpreadDe-SpreadChannelEst/Derot

Path 2Path 3Path 4

Path 1DSCH

Path 1S-CCPCH

De-ScrambleDe-ScrambleDe-Scramble

DPCH

De-SpreadDe-SpreadDe-SpreadDe-Spread

Path 2Path 3Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io

Multi Channel Code De-Mux2nd Deinterleaver

1nd Deinterleaver Channel DecodingFurther Processing

FILTER

RAKE Searcher


De-Scrambler

Path Table Building

Timing Management


Path 2Path 3Path 4


Path 2Path 3Path 4

Path 1DSCH

Path 1S-CCPCH


DPCHS-CCPCH


DPCH


Path 2Path 3Path 4


Path 2Path 3Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io



Physical channel Segmentation

Radio frame segmentation

2nd interleaving

Physical channel mapping

Channel coding

Rate matching

TrBk concatenation /Code block segmentation

CRC attachment

Radio frameequalization

1 st interleaving

TrCHMultiplexing

Spreading/Scrambling

Filter

Rate matching

Physical channel Segmentation

Radio frame segmentation

2nd interleaving

Physical channel mapping

Channel coding

Rate matching

TrBk concatenation /Code block segmentation

CRC attachment

Radio frameequalization

1 st interleaving

TrCHMultiplexing

Spreading/Scrambling

Filter

Rate matching

Real-time chip, bit, and symbol rate processing1 SB9600 chip for 2Mbps Rx concurrently with 768kbps Tx<75% utilization for 384kbps Rx / 384kbps Tx

Includes functions traditionally implemented in H/WTurbo DecoderRake ReceiverTx/Rx Filters


SB9600 Features

PulseShaping

RAKE Searcher


De-Scrambler

Path Table Building

Timing Management


Path 2Path 3Path 4

Path 1DSCH

Path 1S-CCPCH


DPCH


Path 2Path 3Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io



PulseShaping

RAKE Searcher


De-Scrambler

Path Table Building

Timing Management


Path 2Path 3Path 4


Path 2Path 3Path 4

Path 1DSCH

Path 1S-CCPCH


DPCHS-CCPCH


DPCH


Path 2Path 3Path 4


Path 2Path 3Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io



ImageVoiceDataControl

SandblasterTM

DSP

R a t e m a tc h in g

P h y s ic a l c h a n n e ls e g m e n ta ti o n

R a d io f ra m e s e g m e n ta t io n

2 n d in te r le a v in g

P h y s ic a l c h a n n e l m a p p in g

C h a n n e l c o d in g


T rB k c o n c a te n a t io n /C o d e b lo c k s e g m e n t a t io n

C R C a t ta c h m e n t

R a d io f r a m ee q u a l i z a tio n

1 s t in te r le a v in g

T r C H M u l t ip le x in g

S p re a d i n g /S c r a m b l in g

F il te r


P h y s ic a l c h a n n e ls e g m e n ta ti o n

R a d io f ra m e s e g m e n ta t io n

2 n d in te r le a v in g

P h y s ic a l c h a n n e l m a p p in g

C h a n n e l c o d in g


T rB k c o n c a te n a t io n /C o d e b lo c k s e g m e n t a t io n

C R C a t ta c h m e n t

R a d io f r a m ee q u a l i z a tio n

1 s t in te r le a v in g

T r C H M u l t ip le x in g

S p re a d i n g /S c r a m b l in g

F il te r

Communications ProtocolsGSM / GPRS / WCDMA multimodeBluetooth / GPS / 802.11b

Audio/Video/TelephonyMP-3 / AAC / MIDI / WMA / RealMPEG-4 (QCIF, 15fps)VoIP (H.263, G.723.1)Still & Video Camera

MiscMMS / SMS / iMode / WAPSIM / USIMSMIL / SyncMLJava

Reconfigurable on the Fly


SB9600 2003 Handset Chip

EXT INT

AHB INT ARM(922T)

RCVR

SPI &Stat Cntl

I2C &Stat Cntl

TDMInfc (2)

XMTR

TDMInfc (2)

AHB-I/O

Internal AHB

TDMInfc (2)

TDMInfc (2)

External AHB

RF DeviceControl

RF DeviceControl

TDM

TDM

TDM

TDM

RX Data

TX Data

JTAG

DSP

Ins & Data Mem(64KB / 64KB)

L2 Mem

(256KB

)

EXT INT

DSP


L2 Mem

(256KB

)

EXT INT

DSP


L2 M

em(2

56K

B)

EXT

INT

DSP


L2 M

em(2

56K

B)

EXT

INT

DMACntlr

BlueToothI/O

802.11

GPS

XMRI/O

Bridge

SPI

I2C

GPIO

USB UART

SIM/USIM

Keypad

LCD Int.

…

APB

SystemClk/Cntl

Ext.Interrupts

0.13um CMOS, customReplicated SandblasterTM core

Low Power design


Summary

Multithreaded baseband processormulti-threadedhigh-performance and low-power

Sophisticated compiler technologyautomatically generates DSP operationsnear-assembly language performance

Reconfigurable Communications ProtocolsWCDMAGSM, GPRS802.11BluetoothGPS

Expanding the Dimensions of Wireless Multimedia Technology

wireless sdr solutions: the challenge and promise of next...

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