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Verilog Coding for Logic Synthesis

Verilog Coding for Logic SynthesisWENG FOOK LEE

A JOHN WILEY & SONS, INC., PUBLICATION

Copyright 2003 by John Wiley & Sons, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400, fax 978-750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, e-mail: permreq@wiley.com. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specically disclaim any implied warranties of merchantability or tness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of prot or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services please contact our Customer Care Department within the U.S. at 877-762-2974, outside the U.S. at 317-572-3993 or fax 317-572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print, however, may not be available in electronic format. Library of Congress Cataloging-in-Publication Data:

Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1

Dedicated to my mother for all her sacrices.

ContentsTable of Figures Table of Examples List of Tables Preface Acknowledgments Trademarks 1 Introduction 2 Asic Design Flow 2.1 2.2 Specication RTL Coding 2.2.1 Types of Verilog Code: RTL, Behavioral, and Structural Test Bench and Simulation Synthesis Prelayout Timing Analysis APR Back Annotation Post layout Timing Analysis Logic Verication xi xvii xxi xxiii xxv xxvi 1 3 3 5 6 6 9 10 11 12 13 14 16 16 16vii

2.3 2.4 2.5 2.6 2.7 2.8 2.9

3 Verilog Coding 3.1 Introduction to Basic Verilog Concepts 3.1.1 Verilog Syntax

viii

CONTENTS

3.2 3.3

3.4

3.1.2 Comments 3.1.3 Numbers 3.1.4 Verilog Data Type 3.1.5 Signal Strength Verilog Gate-Level Primitives User-Dened Primitives 3.3.1 Combinational UDP 3.3.2 Sequential UDP Concurrent and Sequential Statements

17 17 19 25 27 34 35 37 40 41 41 43 44 46 47 51 51 52 53 54 66 68 68 69 71 78 85 92 100 105 112 115 117 121 127 132 133 151 151 153

4 Coding Style: Best-Known Method for Synthesis 4.1 4.2 4.3 Naming Convention Design Partitioning Clock 4.3.1 Internally Generated Clock 4.3.2 Gated Clock 4.4 Reset 4.4.1 Asynchronous Reset 4.4.2 Synchronous Reset 4.5 Timing Loop 4.6 Blocking and Nonblocking Statement 4.7 Sensitivity List 4.8 Verilog Operators 4.8.1 Conditional Operators 4.8.2 Bus Concatenation Operator 4.8.3 Shift Operator 4.8.4 Arithmetic Operator 4.8.5 Division Operator 4.8.6 Modulus Operator 4.8.7 Logical Operator 4.8.8 Bitwise Operator 4.8.9 Equality Operator 4.8.10 Reduction Operator 4.8.11 Relational Operator 4.9 Latch Inference 4.10 Memory Array 4.11 State Machine Design 4.11.1 Intelligent Trafc Control System 5 Design Example of Programmable Timer 5.1 5.2 Programmable Timer Design Specication Microarchitecture Denition for Programmable Timer

CONTENTS

ix

5.3 5.4 5.5

Flow Diagram Denition for Programmable Timer Verilog Code for Programmable Timer Synthesizable Verilog Code for Programmable Timer

155 161 175

6 Design Example of Programmable Logic Block for Peripheral Interface 6.1 6.2 Programmable Logic Block for Peripheral Interface Design Specication Mode of Operation for Programmable Logic Block for Peripheral Interface 6.2.1 Mode 0 Operation 6.2.2 Mode 1 Operation 6.2.3 Mode 2 Operation Microarchitecture Denition for Programmable Peripheral Interface Flow Diagram Denition for Programmable Peripheral Interface Synthesizable Verilog Code for Programmable Peripheral Interface Simulation for Programmable Peripheral Interface Design 6.6.1 6.6.2 Simulation for Mode 0 Operation with PortA, PortB, and PortC as input and Output Simulation for Mode 0 Operation with PortA, PortB, and PortC Lower as Input and PortC Upper as Output Simulation for Mode 0 Operation with PortA, PortB, and PortC Upper as Input and PortC Lower as Output Simulation for Writing and Reading Data from STATUS and CWR Register Simulation for Mode 1 Operation with PortA and PortB as Strobed Input Simulation for Mode 1 Operation with PortA as Strobed Input and PortB as Strobed Output Simulation for Mode 1 Operation with PortA as Strobed Output and PortB as Strobed Input Simulation for Mode 1 Operation with PortA and PortB as Strobed Output Simulation for Mode 2 Operation with PortA as Strobed I/O and PortB as Input Simulation for Mode 2 Operation with PortA as Strobed I/O and PortB as Output Simulation for Mode 1 Operation with PortA and PortB as Strobed Input and STATUS Register Disabled

181 182 185 185 187 188 189 191 213 234 235

6.3 6.4 6.5 6.6

240 245 249 253 257 262 267 272 277

6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 6.6.10 6.6.11

282

x

CONTENTS

6.6.12 Simulation for Mode 2 Operation with PortA as Strobed I/O and PortB as Output and STATUS Register Disabled

287

Appendix Appendix A.1. two-bit by two-bit adder Appendix A.2. two-bit by two-bit subtractor Appendix A.3. four-bit by four-bit multiplier Glossary Bibliography Index

293 293 295 297 305 307 308

Table of Figures

Figure 2.1 Figure 2.2

Diagram Showing an ASIC Design Flow Diagram Indicating Step 1 of an ASIC Design Flow: Specication Figure 2.3 Diagram Showing the Denition of Architecture and Micro Architecture Figure 2.4 Diagram Indicating Step 2 of an ASIC Design Flow: RTL Coding Figure 2.5 Diagram Indicating Step 3 of an ASIC Design Flow: Testbench and Simulation Figure 2.6 Diagram Indicating Step 4 of an ASIC Design Flow: Synthesis Figure 2.7 Diagram Indicating Step 5 of an ASIC Design Flow: Pre Layout Timing Analysis Figure 2.8 Diagram Indicating Step 6 of an ASIC Design Flow: Auto Place & Route (APR) Figure 2.9 Diagram Indicating Step 7 of an ASIC Design Flow: Back Annotation Figure 2.10 Diagram Indicating Step 8 of an ASIC Design Flow: Post Layout Timing Analysis Figure 2.11 Diagram Indicating Step 9 of an ASIC Design Flow: Logic Verication Figure 4.1 Diagram Showing Two Sub-modules Connected on a Fullchip Level Figure 4.2 Diagram Showing a Fullchip Level of Global Clock Interconnect Figure 4.3 Diagram Showing Ideal Connectivity of Clock Signal in a Design Figure 4.4 Diagram Showing an Output Flip-op Driving Another Flip-op

4 4 5 6 8 9 11 12 13 14 15 42 44 45 46xi

xii

TABLE OF FIGURES

Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 4.17 Figure 4.18 Figure 4.19 Figure 4.20 Figure 4.21 Figure 4.22 Figure 4.23 Figure 4.24 Figure 4.25 Figure 4.26 Figure 4.27

Diagram Showing a Gated Clock Driving a Flip-op Diagram Showing Signal Gated Driving Clock of 32 Flip-ops Diagram Showing Multiple Gated Signal to Drive 32 Flip-ops Diagram Showing a Design with an Asynchronous Reset Flip-op Diagram Showing a Design with a Synchronous Reset Flip-op Diagram Showing a Design with Timing Loop Diagram Showing Simulation Results of Verilog Code in Example 4.8 Diagram Showing Simulation Results of Verilog Code in Example 4.9 Diagram Showing Simulation Results of Verilog Code in Example 4.10 Diagram Showing Simulation Results of Verilog Code in Example 4.12 Diagram Showing Simulation Results of Verilog Code in Example 4.13 Diagram Showing Simulation Results of Verilog Code in Example 4.14 Diagram Showing Synthesized Logic for Module conditional Diagram Showing Synthesized Logic for Module shift_left Diagram Showing Synthesized Logic for Module shift_right Diagram Showing Synthesized Logic for Module addition Diagram Showing Synthesized Logic for Module subtraction Diagram Showing Synthesized Logic for Module multiplication Diagram Showing Synthesized Logic for Design Module division Diagram Showing Synthesized Logic for Design Module modulus Diagram Showing Synthesized Logic for Verilog Code Module logical Diagram Showing Synthesized Logic for Verilog Code Module bitwise Diagram Showing Synthesized Logic for Verilog Code Module logicequal

47 49 49 52 53 54 58 58 59 59 63 64 70 72 75 79 81 83 86 94 100 107 113

TABLE OF FIGURES

xiii

Figure 4.28 Diagram Showing Synthesized Logic for Verilog Code Module reduction Figure 4.29 Diagram Showing Simulation Results of Verilog Testbench Module relational_tb Figure 4.30 Diagram Showing Synthesized Logic for Module latch_infer Figure 4.31 Diagram Showing Synthesized Logic of Module latch_noninfer Figure 4.32 Diagram Showing Synthesized Logic for Module case_infer Figure 4.33 Diagram Showing Synthesized Logic for Module case_uninfer_diff Figure 4.34 Diagram Showing Synthesis Represent