SAT Control System

Weekly Meeting February 28th, 2012

2SAT Control System - Weekly Meeting

Meeting Agenda

Status ReportCoil Driver (all)LVDT (all)AOB

28/02/2012

Channels

Accel

LVDT

CD

LVDT

Analog Domain Digital Domain

2 OUT + 1 IN(1 channel)

2 OUT + 2 IN(2 channels)

1 OUT(1 channel)

2 DA+ 2 ADchannels

2 DA+ 2 ADchannels

2 DA+ 2 ADchannels

Data Conversion Block

DAC

FPGA Ch1

ADC

Ch2

ADC

LVDT Block Diagram

Bal OUT

Diff IN

LVDT

P

S

LVDT

P

S

OLDSSM2017

G = 100:1000HiZ

R 11k

R 310k

R 210k

0

U 1

SSM -2017 /AD

O U T11

+5

-4

R E F10

V +13

V -7

R G 12

R G 215

IN +

IN -

R 4100k

C 1

10n

0

+12

-12

20nV/sqrt(Hz) Fully DiffG=1:10

Vp –Vn > 10V

Balanced Driver with Diff Input

G=2Vp –Vn > 14V

AD8397(Dual High Current)

OPA1612(Dual Low Distortion)

DSPBlock PCIe

SR

IO

Communications

DSP

FPGA

TOLM

PC

IeLin

k

PCI

Locking / Align

DAQ

SRIO DSP

FPGA

PC

Ie

Analog IO SA

USB USB

Eth

HyperLink

Eth