vlsi for electricals - veena

7/29/2019 VLSI for Electricals - Veena

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VLSI For Electrical Engineering

Dr. Veena S [email protected]

ProfessorDepartment of Electronics & Communication

EngineeringBNMIT
mailto:[email protected]:[email protected]


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Agenda

Introduction- History, Revolution, growth

Understand the core device - MOS

Shrinking MOS / Scaling

Design Methodology

SOC

Product development flow

Getting ready for semiconductor Industry

Summary


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Guess and Identify..

ok closely n' guess what they cud be...


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So it is


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Smart home control application


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History

6

Silicon Revolution in 40 years !!

Intel PentiumII, 1997

Clock: 233MHz

Number of transistors: 7.5 M

Gate Length: 0.35

First integrated circuit (germanium), 1958Jack S. Kilby , Texas Instruments

Contained five components, three types:transistors resistors and capacitors

1958

19581997

1997


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Gorden Moore

7


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Moores Law Feature Size

8


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Growth

9

1 cm 1 mm 0.1 mm 10m 1 m 0.1 m 10 nm 1 nm 1

Chip size(1 cm)

Diameter ofHuman Hair

(70 m)

1996 devices(0.35 m)

2007 devices(0.1 m)

Siliconatomradius

(1.17 )Deep UV

Wavelength(0.248 m)

X-rayWavelength

(0.6 nm)

1997 devices(0.25 m)

1 Micron, 1 m = 1000 nM

1 nM = 10 A0 (Angstrom)


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Moores Law Some analogies

10


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Transistor- structure

11


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Transistor- Function

12


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Transistor- Characteristics

13


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Transistor- Connections

14


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Transistor- application

15

n+ n+

p-

S

G

D

S D

G

- Substrate , Diffusion , Gate-Oxide(SiO2) & PolySi gate

- Source , Drain , Gate & Substrate

N-Transistor

p+ p+

n-

D

G

S

SD

G

P-Transistor

Vgs >= Vth ON

Vgs < Vth OFF

Vgs Vth OFF

Vss Vdd

Vss Vdd

- MOS Transistor is Bi-Directional Device

Substrate

Substrate


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Transistor- application

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a b

S = 0

S = 1

a b

Vss

Vdd

Vss

Vdd

Vgs S

DG

S

DG

Vgs

a b

S = 1

S = 0

a b

s

-s

a b

N-Switch

P-Switch

Complimentary Switch(Transmission Gate)

a b

Transistor Schematic

Logic Symbol

s

-s

S=1 : Output b is Good 0 / Good 1

Depending on input a.

S=0 : Switch is OFF

No path from a to b.


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CMOS logic

17

Vdd

Vss

a x

a x

0

1

1

0

Circuit Symbol

Vdd

Vss

a

b

xa b

0

0

1

1

0

1

0

1

a b x1

1

1

0

a xab x

Circuit Symbol

Vdd

Vss

a

b

a b

x

0

0

1

1

0

1

0

1

a b x1

0

0

0

ab

x

Circuit Symbol

INVERTER NAND2 NOR2


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Inverter Mask Set

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Transistors and wires are defined by masks

Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor


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Inverter Layout

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Scaling

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Scaling- FET

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Short Channel Effect

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2 D Field effects

Drain Induced Barrier Lowering DIBL

Mobility reduction

Threshold reduction

High Electrical field in the channel Carrier velocity saturation

Impact Ionization Hot Electron effect

Gate oxide charging

Parasitic Bipolar effect

Decrease of Source Drain distance

Punch through

Channel length modulation


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Wire Scaling

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0

5

10

15

20

25

30

35

40

45

0.65um 0.5um 0.35um 0.25um 0.18um 0.13um 0.1um

Delay(p

Gate

Cu Interconnect

Al Interconnect

Cu + Gate

Al + Gate

Mark Bohr, Intel, IEDM95

Wire

43um long

0.8um high

Scaled width


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VLSI Design

24


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25


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Design Description Domains

Structural DomainBehavioral Domain

Physical Domain

Transistor

Cells

Modules

Chips , Boards & Boxes

Transistor

Gates. Adders, Registers

RISC Processor

Chip / System

Instruction

Subroutines

OS

Application

Architectural Abstraction Layer

RTL, Logic Abstraction Layer

Circuit Abstraction Layer


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IN [ 1 : N ] OUT [ 1 : M ]

CS [1 : K] NS [ 1 : K]

CombinationalLogic ( C / L )

D

Reg

Clock

OUT = F1 (IN , CS);NS = F2 (IN , CS)

Generalized Mealy Model for Synchronous Sequential Machines

DReg

DReg

DReg

DRegC / L

1

C / L

2

C / L

3SYS_CLK

Iterative Model for Synchronous Sequential Machines

t1 t2 t3 t4

Clk (1) Clk (2) Clk (3) Clk (4)

Stage 1 Stage 2 Stage 3 Stage 4

q

TT >= tclk-q+ tC/Lmax + t setup

( )

SYS_CLK

Timing Constraint

q q qD D D D

RTL Model Sequential Machine & Finite State Machine (FSM)


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- Performance Speed , Power , Function & flexibility.-Size of Die ( hence cost of Die).-Time to Design ( hence cost of Engineering & Schedule ).- Ease of Test Generation ( hence cost of Engineering & Schedule ).

Implementation Options :

Performance

Die Size

Design Effort

Test Generation Effort

Low Medium High

Large Small Smallest

Low Medium Very High

Low Medium High

Gate Array Cell Based Full Custom

NOTE : Test Generation has two aspects. 1. Design or Function Test . & 2. Manufacturing Test.

System Design Parameters to Consider


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Structured Design Strategies

Hierarchy :Successive refinement of design abstraction to Manage complexity.Structural hierarchy within one Abstraction Level.

Regularity:Reuse blocks designed once , many times to improve design productivity.

Modularity :

Module -> Sub-Module - > .-> Leaf Cell.Well defined functionality & Interface.

Locality :Well characterized module interface to hide internal design details.

- These have a strong Parallel to Object oriented Software design Methodology.

-Hierarchy : Successive refinement of SW Design into lower & lower functions/objects.- Regularity : Repetitive use of Objects. Object Reuse ( Object Factory.).-Modularity : Well defined object functionality & interface to enable reuse of the Objects- Locality : Local variables & Methods hidden from outside world.


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Structured Software & VLSI Hardware Design

Software Hardware

Hierarchy

Regularity

Modularity

Locality

Subroutines , Libraries Modules

Iteration,Code-sharing,OO-Procedures

Data pathModule Reuse,Regular arrays,

Well defined SubroutineInterface

Well DefinedModule Interface,

Timing & Loading Data.

Local Scoping,No Global Variables.

Local ConnectionThro Floor-planning.Registered I/O.


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SOC

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What is SoC?

System-on-ChipAn IC that integrates the major functional elements of acomplete end-product into a single chip.


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SOC (Contd.)

An SOC contains

Reusable IP

Embedded processor/Memory

Real world interface

Mixed signal blocks

Programmable hardware

Has more than 500K gates

Use 0.25um technology or below

Not an ASIC


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SOC design methodology revolution


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Product Life cycle development

Idea StageIdea can be fromanywhere Idea should be in syncwith the companys

objective Core Resources availableatCompanys reach.

Business caseMarketing Responsibility Market analysis Costing and ROI workedout Competitive analysis anddifferentiators identified

Product FeasibilitySystem EngineeringResponsibility Application scenarios Feature definition Feasibility with Engineering Product specification,HW/SF/DSP needs identified


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Product Life cycle development (Contd.)

Product commit Management commitsto invest Engineering commits todevelop

Tape Out decision Marketing Responsibility Market analysis Costing and ROI workedout Competitive analysis anddifferentiators identified

Chip Validation and EngineeringSamples System EngineeringResponsibility Application scenarios Feature definition Feasibility with Engineering Product specification,

HW/SF/DSP needs identified

Product Release System EngineeringResponsibility Application scenarios Feature definition Feasibility with Engineerin Product specification,HW/SF/DSP needs identifie


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A Typical Design Flow - Simplified

HDL Capture

HDL Synthesis

Schematic Capture

HDL Simulation

RTL SIM - OK ?N

Y

Gate SIM - OK ?N

Y

A

B

Front End Design

Tech_Dbase

Design Concept

Back End Design

Floor Plan

SC & Block P&R

Y

Gate SIM - OK ?N

Y

C

D

Net & ParasiticsExtraction

Back Annotation

Pad Ring &Power P&R

Mask Data Generation

To Si Foundry

Tech_Dbase

Tech_Dbase

Tech_Dbase


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Skill Set Requirement

VLSI specific skills:

Understanding of the basic CMOS process

VLSI design flow and entry/exit criteria for each phase

Capability to visualize the logic for a function.

HDL coding to realize the logic

EDA Tool flow and usage

Scripting skills for data analysis

C+ programming skills for co verification

Logic parameters and their relevance

Additional knowledge

Processor architecture Interfacing

Timing requirements

Clocking strategy


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Opportunities

Product development Services Design houses

Board design houses

System integration services

Test houses

Repair and maintenance services Verification services

Product companies Total Solutions

Fabrication houses Quicker shuttles

Characterization

Certification bodies

Consultancy services


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Opportunities

Larger system development

State of Art development suites

Close relationship with customers and suppliers

Challenges at all phases of the development

Opportunity to become Multi skilled

World connect Need to do distributed development

taking advantage of geographic locations

Global coordination


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What does this mean?

Do it ..

Right First time

Communicate clearly

Quick

Defined matured process

Compliant to process

Acquire multiple skills

Learn new development suites

Learn different languages

Analyze every issue


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Some Tips for You!

Find application for your task

Communicate Well

Be open for Learning

Get broader perspective

Detailing

Be a perfectionist

Plan you career in advance

Be patient

Develop good attitude

Be a good Team player
http://var/www/apps/conversion/tmp/scratch_3/CustomerReq.ppthttp://var/www/apps/conversion/tmp/scratch_3/CustomerReq.ppt


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Summary

VLSI - Revisited

Understand the core device - MOS

Shrinking MOS / Scaling Design Description Domains : Behavior , Structure & Physical.

RTL Design , Synchronous Sequential Machine , FSM

System Design Parameters Performance , Die Size , Design Effort , Test Generation Effort.

Design Strategies

SOC

Product development Cycle

Typical Design Flow

Getting ready for Semiconductor Industry


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Get yourselves equipped to be a part of excitingfast growing field

VLSI needs you, Get Ready!

vlsi for electricals - veena

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