vlsi clc design.ppt

7/29/2019 VLSI CLC Design.ppt

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VLSI Combinational Circuit Design

Dr.LeDungHanoi University of Science and Technology

Dr. Le Dung Hanoi University of Science and Technology

Alargedigitallogiccircuit

canbeimplementedby

SSI, MSI and LSI

off-the-shelf partsVLSI Application-specific

integrated circuit (ASIC)

SingleICMul:pleICs


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An example of the off-the-shelf parts design


Designing with off-the-shelf parts

Theoff-the-shelfparts=CommercialSSI,MSIandLSImodularlogicintegratedcircuits(74xxx,4xxx)

QuicklyassemblingacircuitboardThenumberofpartsandthecostpergatecanbecomeunacceptablylarge


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VLSI ASIC design

UsingsingleVLSIIC+ReducePCBspaceandpowerrequirements

+Reducetotalcost

Usinghardwaredescrip:onlanguageandCADtoolsfordesigning

Designingapproaches+Full-customdesign

+Semi-customdesign


Full-custom design (1)

Gatebygatedesigningwiththephysicallayoutofeachindividualtransistorandtheinterconnec:onsbetweenthem.

Eachtransistorandeachconnec:onisdesignedindividuallyas

asetofrectangles


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Full-custom design (2)

+Boththecircuitperformanceandthesiliconareacan

beop:mized(usingECADtools)

-Extremelylabor-intensivetoimplement

-Highcostofmasksets

-Increasingmanufacturinganddesign:me

Time-to-marketcompe::on


Semi-custom design

Semi-customdevice+haspredesignedparts

Semi-customdesignapproachesStandardcellbaseddesign

GatearraybaseddesignProgrammabledevicesbaseddesign


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Standard cell based design (1)

Libraryofstandardcells+Eachcellisagate

+Sameheight,variablewidth,interleavedbyrou:ngchannels

+Allinputsatthetop,alloutputsatthebo]om

Adesignerselectscellsfromadesignlibarary,specifyingwheretheyshouldbeplacedontheICandthen

dicta:nghowtheyshouldbeinterconnected.

Fasterdesignofmorecomplexbuildingblocks Siliconfoundriesdesignandsellsuchop:mizedlibraries

fortheirprocessingtechnology


Basic process standard cell based design

Technology

mapping


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HardwareDescrip:onLanguage Synthesis

Translate HDL descriptions into logic gate networks in a particular library


LogicSynthesisPhases

Logic optimization transforms current gate-levelnetwork into an equivalent gate-level network moresuitable for technology mapping.

Technology mapping transforms the gate-levelnetwork into a netlist of gates (from library) which

minimizes total cost.


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Libraryofstandardcell

INVERTER 2 1

NAND2 3 1.4

NAND3 4 1.8

NAND4 5 2.2

AOI21 4 1.8

CELLS COST DELAY SYMBOLPATTERN


CMOS AND-OR-Invert Gate

Anexampleofstandardcelltechnologymapping(1)



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Anexampleofstandardcelltechnologymapping(2)

Synthesis


Netlist of gates (from library)

which minimizes total cost.

Phasesofsynthesis(1/3)

1. Independenttransformaons(opmizaon)



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da

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Original netlist


Decomposionusingbasefuncons DecomposetoanetworkNAND2/NOT

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Original netlist


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Subject Graph


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Whatistechnologymapping?

Technologymappingistheproblemofopmisinganetworkforareaordelay,usingonlylibrarycells.

Mapping

library

rule


Netlist of gates (from library)

which minimizes total cost.

Original netlist


d

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efgh

TechnologymappingGreedyalgorithmGreedysearch


Subject Graph


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Technologymapping Greedysearch


Subject Graph


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Technologymapping-Greedysearch


Subject Graph


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Technologymapping Usingprincipleofop:mality


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Subject Graph


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Subject Graph


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Subject Graph

Sea of gates

Cell I/O buffer

Fixed transistorlayer

Customized

metal layer for

connecting gate


Gatearraybaseddesign+ A gate array or uncommitted logic array (ULA) circuit is prefabricatedwith a number of unconnected logic gates (cells).

+ CMOS transistors with fixed length and width are placed at regularpredefined positions and manufactured on a wafer, usually called a

master slice ( sea of gates).+ Creation of a circuit with a specified function is accomplished by

adding a final surface layer or layers of metal interconnects to the chips

on the master slice late in the manufacturing process, joining theseelements to allow the function of the chip to be customized as desired

reducing the designing time reducing the mask costs

+ Disadvantages

- slow clock speed- wasted chip area


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Gatearraybaseddesignflow

Designentry

Placement

Rou:ng

Simula:on

Timingsimula:on

Fabrica:on(metal1mask) Tes:ng

Library of cellsTechnologymapping


ProgrammableDeviceBasedDesign

Based on programmable devices:The interconnection layers are personalized by electronic means for a

specific application. This work usually can be done by end-users.

F0 = AB+ AC

F1 = B + AC

F2 = AB+ BCF3 = AC + B


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ProgrammableElements

+ Fuse

+ Antifuse

+ Switch+ Volatile

+ Non-volatile

+ One Time Programmable

+ Reprogrammable (Memory-based)


ProgrammableDevices

Simple Programmable Logic Device:+ Programmable read only memory (PROM)

+ Field Programmable logic array (FPLA or PLA)

+ Programmable array logic (PAL)

+ Generic array logic (GAL)

Complex programmable logic device (CPLD)Field programmable gate array (FPGA)Field programmable interconnect (FPIC)


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BasicSPLDorganiza:on

AND

array

OR

arrayOutput

options

Product

terms

Sum

terms

Feedback terms

Inputs Outputs


Fuse-basedprogrammableANDORArray


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OutputPolarityOp:ons


Bidirec:onalPinsandFeedbackline


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PLDDesignProcess


Combina:onalCircuitisimplementedonSPLD


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PROM=Read-Only-Memory


PROM=PLDwithfixedANDarray


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Full-adderonPROM


PAL


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Combina:onalCircuitisimplementedPAL


FPLA

Programmable

OR arrayProgrammable

AND array


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Combina:onalCircuitisimplementedonFPLA(1)

Minimizeeachfunc:onseparately

8productterms

F1=bd+bc+ab

F2=c+abd

F3=bc+abc+abd

Mul:ple-OutputOp:miza:on

5productterms

F1=abd+abd+abc+bc

F2=abd+bc+bc

F3=abd+abc+bc


Combina:onalCircuitisimplementedonFPLA(2)

F1=abd+abd+abc+bc

F2=abd+bc+bc

F3=abd+abc+bc


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Exercise

Implement the twofunctions with PLA

PLA


GenericArrayLogicarchitecture

Output logic macrocell (OLMC)


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CPLDarchitecture

AND-OR

Plane

O I/O

Switch matrix

I/O O

AND-OR

Plane

AND-OR

Plane

O I/O I/O

AND-OR

Plane

O


FPGAarchitecture(1)


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FPGAarchitecture(2)


FPGAarchitecture(3)

Switch Matrix and interconnection

Long lines :

-Across whole chip-High fan-out, low skew-Suitable for global signals (CLK) and buses-2 tri-states per CLB for busses


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FPGAarchitecture(4)Configurable Logic Block (CLB)

5 logic inputs

Data input (DI)Clock (K)

Clock enable (EC)Direct reset (RD)

2 outputs (X,Y)


FPGAarchitecture(5)

I/O Block (IOB)


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FPGAdevelopmenttoolkit

vlsi clc design.ppt

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