vhdl report

Circuit

Design With

VHDL

Problems Solution

Chapter 2 – Chapter 12

M.Zanaty

Demonstrator

Faculty of Engineering

Assiut University

Contents Pages

Introduction---------------------------------------------------------------------------------- 1

Chapter 2: “Code Structure” ------------------------------------------------------------ 2

Chapter 3: “Data Types” ------------------------------------------------------------------ 5

Chapter 4:”Operators and Attributes” ------------------------------------------------ 9

Chapter 5: “Concurrent Code”----------------------------------------------------------- 13

Chapter 6:”Sequential Code”------------------------------------------------------------ 22

Chapter 7: “Signals and Variables”----------------------------------------------------- 43

Chapter 8:”State Machines”-------------------------------------------------------------- 50

Chapter 9:”Additional Circuits Design”----------------------------------------------- 63

Chapter 10: ”Component and Packages”--------------------------------------------- 84

Chapter 11:”Functions and Procedures”---------------------------------------------- 93

Chapter 12:”Additional Sysytems Design”------------------------------------------- 111

Conclusion ------------------------------------------------------------------------------------ 126

Refrences -------------------------------------------------------------------------------------- 127

Cicuit Desgn with VHDL

- 1 -

Introduction

This report is organized as following.First, it is divided into chapter 2 to

chapter 12. Within each chapter, VHDL code is presented at the beginning of each

problem. Then, simulation results for these codes is also included. For some

problems, more than one solution is presented. Second, a conclusion is made

about the main confronts that I have faced. Finally, a list of refrences is included.

Regarding the software tools, ISE 9.2i Design suite is used. However, due to

bugs introduced with ISE Simulator 9.2i. I have upgradted to the next version ISE

Design suite 10.1. Sometimes, ModelSim is also used for checking some codes.

With respect to FPGA, All the codes are synthesized and implemented-

some of them- for Spartan3an xc3s700AN. The same kind of FPGA we have within

our lab.

Finally, on solving the problems, some postulations are made. For instance,

some problems required a delay of 10ms. To simplify this, I have made a delay

only of several few cycles (5 cycles).


- 2 -

Chapter 2: “Code Structure”

Problem 2.1-------------------------------------------------------------------------------------3

Problem 2.2-------------------------------------------------------------------------------------3


- 3 -

Problem 2.1: Multiplexer

1 ---------------------------------------

2 LIBRARY IEEE;

3 USE IEEE.std_logic_1164.ALL ;

4 ---------------------------------------

5 ENTITY mux IS

6 PORT (a , b : in STD_LOGIC_VECTOR (7 DOWNTO 0);

7 sel : IN std_logic_vector (1 downto 0) ;

8 c : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

9 END mux ;

10 ---------------------------------------

11 ARCHITECTURE example OF mux IS

12 BEGIN

13 PROCESS (a, b, sel )

14 BEGIN

15 IF (sel = "00") THEN

16 c <= "00000000";

17 ELSIF (sel=”01”) THEN

18 c <= a;

19 ELSIF (sel = "10") THEN

20 c <= b;

21 ELSE

22 c <= (OTHERS => 'z');

23 END if;

24 END processs ;

25 END example ;

Problem 2.2: Logic Gates

a.) entity p2 is

port(a,b,c: in std_logic;

d: out std_logic);

end p2;

architecture Behavioral of p2 is

begin

d <= a nand ((a and b)or(not c));

end Behavioral;

b.) Eqn = ((!b and c)+ !a)

Table 2-1 Truth Table generated by Compiler

A C B D

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

Figure2-1 Simulation results P2.2


- 4 -

Chapter 3 : “Data Types”

Problem 3.1------------------------------------------------------------------------------------------- 5

Problem 3.2------------------------------------------------------------------------------------------- 5

Problem 3.3------------------------------------------------------------------------------------------- 6

Problem 3.4------------------------------------------------------------------------------------------- 6

Problem 3.5------------------------------------------------------------------------------------------- 7


- 5 -

Problem 3.1

Table 3-1 Dimensions of Given signals

Signal Dimension Numeric Example

A Scalar 1 /0

B Scalar 1/0/u/x/z/L/H

X 1D “01001111”

Y 2D {‘1’,’0’,’0’,’1’,’0’,’0’,’0’,’0’,

,’1’,’0’,’1’,’1’,’0’,’1’,’1’,’1’,

,’1’,’1’,’1’,’1’,’0’,’0’,’0’,’0’,

,’1’,’0’,’1’,’0’,’1’,’1’,’0’,’1’}

W 2D {“10010000”,

“10110111”,

“11110000”,

“10101101”}

Z 1D “10010101”

Problem 3.2

Table 3.2

scalar,scalar Different Data types

Scalar, Scalar Legal same data type

scalar,scalar Legal Same data type

scalar,scalar Illegal OUT of range

scalar,scalar illegal wrong index

scalar,scalar legal correct index

vector,vector illegal width mismatch

scalar, vector illegal different data types

1D,1D illegal wrong index

1D,2D illegal dimension mismatch

1D,1D legal same dimension

1D,1D illegal wrong index

1D,1D Legal correct index

1D,1D illegal incompatible

scalar,scalar illegal incompatible

scalar,scalar illegal incompatible

2D,2D Legal

scalar, scalar legal

1D,1D legal

1D,2D illegal different data types

2D,1D illegal different dimensions

1D,1D illegal incompatible

1D,1D wrong index


- 6 -

Problem 3.3

Possible Subtypes:

Subtype my_integer is integer range 0 to 99;

Subtype sys_logic is std_logic range ‘0’ to ‘z’;

Subtype my_array1 is array1 range 2 downto 1 of array1;

Subtype my_array2 is array2 range (2 to 1, 5 downto 3) of array2;

Problem 3.4

• Code

--------------------------------------------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity p4 is

port(address: integer range 0 to 7;

outp: out std_logic_vector (3 downto 0));

end p4;

--------------------------------------------------------------------------------------------------------------------------------


type rom is array (0 to 7) of std_logic_vector (3 downto 0);

constant memory : rom:=("0000","0001","0011",

"0010","0110","0111",

"0101","0100");

begin

outp <= memory(address);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

-----------------------------------------------------------------------------------------------------------------------------

Figure 3.1 Simulation results problem 3.4


- 7 -

Problem 3.5

• Code

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------------------------------------------------------

entity p5 is

port(a,b: in std_logic_vector (7 downto 0);

c: out std_logic_vector (7 downto 0));

end p5;

--------------------------------------------------------------------------------------------------------------------------------


begin

c<= a+b;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure 3-2 Simulation results P3.5


- 8 -

Chapter4 : “Operators and Attributes”

Problem 4.1------------------------------------------------------------------------------------------------ 9

Problem 4.2------------------------------------------------------------------------------------------------ 9

Problem 4.3------------------------------------------------------------------------------------------------ 9

Problem 4.4----------------------------------------------------------------------------------------------- 10

Problem 4.5------------------------------------------------------------------------------------------------ 11


- 9 -

SIGNAL a : BIT := '1';

SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";

SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";

SIGNAL d : BIT_VECTOR (7 DOWNTO 0);

SIGNAL e : INTEGER RANGE 0 TO 255;

SIGNAL f : INTEGER RANGE -128 TO 127;

Problem 4.1: Operators (fill in the blanks)

x1 <= a & c; -> x1 <= “10010”;

x2 <= c & b; -> x2 <=”00101100”

x3 <= b XOR c; -> x3 <=”11110”

x4 <= a NOR b(3); -> x4 <= ‘0’

x5 <= b sll 2; -> x5 <= “0000”

x6 <= b sla 2; -> x6 <= “0000”

x7 <= b rol 2; -> x7 <= “0011”

x8 <= a AND NOT b(0) AND NOT c(1); -> x8 <= ‘1’

d <= (5=>'0', OTHERS=>'1'); -> d<= “11011111”

Problem 4.2

c'LOW -> 0

d'HIGH -> 7

c'LEFT -> 0

d'RIGHT -> 7

c'RANGE -> 3 downto 0

d'LENGTH ->8

c'REVERSE_RANGE ->0 to 3

Problem 4.3

Table 4-1 Problem 4.3

operation Legal / illegal reason b(0) AND a legal Same data type

a + d(7) illegal Arithmetic operator on bit data type

NOT b XNOR c legal Same data type with equal width

c + d illegal Arithmetic operator on bit data type

e – f legal Arithmetic operator on integer data

IF (b<c) ... legal

IF (b>=a) ... legal

IF (f/=e) ... legal

IF (e>d) ... legal

b sra 1 legal

c srl -2 legal

f ror 3 illegal NOT bit data type

e*3 legal

5**5 legal

f/4 legal No synthesis support

e/3 legal No synthesis support

d <= c illegal Width msimatch

d(6 DOWNTO 3) := b illegal Signals not variables

e <= d illegal Different data type

f := 100 illegal Signal not variable


- 10 -

Problem 4.4

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

generic(n: integer := 3);

port(ena: in std_logic;

sel: in std_logic_vector (n-1 downto 0);

x: out std_logic_vector (2**n-1 downto 0));

end p4;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(ena, sel)

variable tmp: integer range 0 to x'high;

variable tmp1: std_logic_vector (x'high downto 0) := (others => '1');

begin

tmp1 := (others => '1');

if (ena='1') then

for i in sel'range loop

if (sel(i) = '1') then

tmp:=tmp*2 +1;

else

tmp:= tmp*2;

end if;

end loop;

tmp1(tmp) := '0';

x<= tmp1;

tmp:=0;

else

x<= (others => '0');

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure 4-1: Simulation results for problem 4.3


- 11 -

Problem 4.4b

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p4b is

Generic (n: integer :=3);

port(ena: in std_logic;

sel: integer range 0 to 2**n-1;

x: out std_logic_vector (2**n-1 downto 0));

end p4b;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of p4b is

begin

process(ena,sel)

begin

x<= "11111111";

if(ena='1') then

x(sel) <= '0';

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 4.5

Table 4-2: Problem 4.5

Attributes Operators Generic

x’HIGH := n: integer :=7

sel’range <=

Output’range =>

Input’range +

Output’high *

xor

Figure 4-2: Simulation Results for Problem 4.4


- 12 -

Chapter 5:”Concurrent Code”

Problem 5.1--------------------------------------------------------------------------------------------- 13

Problem 5.2--------------------------------------------------------------------------------------------- 13

Problem 5.3-------------------------------------------------------------------------------------------- 15

Problem 5.4--------------------------------------------------------------------------------------------- 15

Problem 5.5--------------------------------------------------------------------------------------------- 17

Problem 5.6--------------------------------------------------------------------------------------------- 18

Problem 5.7--------------------------------------------------------------------------------------------- 19

Problem 5.8-------------------------------------------------------------------------------------------- 20


- 13 -

Problem 5.1

• Code

-----------------------------------------------my _data_type Package-------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package my_data_types is

--------------------------------------------------------------------------------------------------------------------------------

type vector_array is array (natural range <>) of

std_logic_vector (7 downto 0);

end my_data_types;

--------------------------------------------------Main code---------------------------------------------------------------

library IEEE;




use work.my_data_types.ALL;

--------------------------------------------------------------------------------------------------------------------------------

entity p1 is

GENERIC (n : integer := 2);

PORT (x : in vector_array (0 to 2**n-1);

y : out std_logic_vector (7 downto 0);

sel: in integer range 0 to 2**n-1 );

end p1;

--------------------------------------------------------------------------------------------------------------------------------


begin

y <= x(sel);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

Problem 5.2a

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p2 is

port( clk : in std_logic;

r: in std_logic_vector (7 downto 0);

y: out std_logic_vector (2 downto 0));

end p2;

--------------------------------------------------------------------------------------------------------------------------------


begin

y <= "111" when r(7)= '1' else

"110" when r(6)= '1' else

"101" when r(5)= '1' else


- 14 -

"100" when r(4)= '1' else

"011" when r(3)= '1' else

"010" when r(2)= '1' else

"001" when r(1)= '1' else

"000";

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 5.2b

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p52a is

port( r: in std_logic_vector (7 downto 0);


end p52a;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of p52a is

begin

y(2) <= r(7) or r(6) or r(5) or r(4);

y(1) <= r(7) or r(6) or((r(3) or r(2)) and (not r(5) and not r(4)));

y(0) <= r(7) or (not r(6) and (r(5) or (not r(4) and ((r(3) or (not r(2) and r(1)))))));

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure 5.1 Simulation results for problem 5.2a

Figure 5.2 Simulation results for problem 5.2b


- 15 -

Problem 5.3

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p3b is

port(a,b: in integer range 0 to 255;

x: out integer range 0 to 2**15-1;

y: out integer range 0 to 255);

end p3b;

--------------------------------------------------------------------------------------------------------------------------------


begin

x<= a*b;

y <= a/2;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 5.4

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

port (clk: in std_logic;

a,b : in std_logic_vector (7 downto 0);

sum: out std_logic_vector (7 downto 0);

cout : out std_logic;

cin: in std_logic);

end p4;

--------------------------------------------------------------------------------------------------------------------------------


signal c : std_logic_vector (7 downto 0) := "00000000";

begin

sum(0)<= a(0)xor b(0)xor cin;

Figure 5.3 Simulation results for problem 5.3


- 16 -

c(0) <= (a(0) and cin) or (b(0) and cin) or (a(0) and b(0));

G1: for i in 1 to sum'high generate

sum(i) <= a(i) xor b(i) xor c(i-1);

c(i) <= (a(i) and c(i-1))or(b(i) and c(i-1))or(a(i) and b(i));

end generate G1;

cout <= c(7);

end Behavioral;

• Simulation

-

------------------------------------------------Another Solution-------------------------------------------------------

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p54b is


sum : out std_logic_vector (7 downto 0);

cout: out std_logic);

end p54b;

--------------------------------------------------------------------------------------------------------------------------------


signal longa,longb,result: std_logic_vector (8 downto 0);

begin

longa <= '0' & a;

longb <= '0' & b;

result <= longa + longb;

sum <= result(7 downto 0);

cout <= result(8);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation


Figure 5-5 Simulation results for problem 5.4


- 17 -

Problem 5.5

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p55 is

port(a,b: in std_logic_vector(7 downto 0);

cin: in std_logic;

sel: in std_logic_vector (1 downto 0);

outp: out std_logic_vector (7 downto 0);

cout_sign : out std_logic);

end p55;

--------------------------------------------------------------------------------------------------------------------------------


signal longa,longb,result: std_logic_vector (8 downto 0);

signal carry: std_logic_vector (8 downto 0) := (others => '0');

begin

carry(0) <= cin;

longa <= ('0' & a) when (sel(0)='0' or (sel(0)='1' and a(7)='0')) else

('1' & a);

longb <= ('0' & b) when (sel(0)='0' or (sel(0)='1' and b(7)='0')) else

('1' & b);

with sel select

result <= longa+longb+carry when "00",

signed(longa)+signed(longb)+signed(carry) when"01",

longa-longb when "10",

signed(longa) - signed(longb) when others;

outp <= result(7 downto 0);

cout_sign <= result(8);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure 5-.6 Simulation results for problem 5.5


- 18 -

Problem 5.6

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p6b is

port (b: in std_logic_vector (3 downto 0);

g: out std_logic_vector (3 downto 0));

end p6b;

--------------------------------------------------------------------------------------------------------------------------------


begin

g <= b xor ('0' & b(b'high downto 1));

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

-----------------------------------------Another Solution----------------------------------------------------------------

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p6 is

port (b: in std_logic_vector (3 downto 0);

g: out std_logic_vector (3 downto 0));

end p6;

--------------------------------------------------------------------------------------------------------------------------------


begin

with b select

g <= "0001" when "0001",

"0011" when "0010",

"0010" when "0011",

"0110" when "0100",

"0111" when "0101",

"0101" when "0110",

"0100" when "0111",

"1100" when "1000",



- 19 -

"1101" when "1001",

"1111" when "1010",

"1110" when "1011",

"1010" when "1100",

"1011" when "1101",

"1001" when "1110",

"1000" when "1111",

"0000" when others;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 5.7

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p7 is

port (inp : in std_logic_vector (3 downto 0);

outp : out std_logic_vector (3 downto 0);

shift : in std_logic);

end p7;

--------------------------------------------------------------------------------------------------------------------------------


begin

outp <= inp when shift= '0' else

inp (inp'high-1 downto 0) & '0';

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation




- 20 -

Problem 5.8

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p58 is


sel: in std_logic;

x1,x2,x3: out std_logic);

end p58;

--------------------------------------------------------------------------------------------------------------------------------


signal tmp1,tmp2:std_logic;

begin

tmp1 <= '1' when ((a>b and sel='0')or (signed(a)> signed(b) and sel='1')) else

'0';

tmp2 <= '1' when ((a=b and sel='0')or (signed(a)= signed(b) and sel='1')) else

'0';

x1<= tmp1; x2<= tmp2;

x3 <= not(tmp1 or tmp2);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 21 -

Chapter 6:”Sequential Code”

Problem 6.1 ------------------------------------------------------------------------------------------- 22

Problem 6.2 ------------------------------------------------------------------------------------------ 22

Problem 6.3 ------------------------------------------------------------------------------------------ 23

Problem 6.4 ------------------------------------------------------------------------------------------ 26

Problem 6.5 ------------------------------------------------------------------------------------------ 27

Problem 6.6-------------------------------------------------------------------------------------------- 27

Problem 6.7 ------------------------------------------------------------------------------------------- 29

Problem 6.8 ------------------------------------------------------------------------------------------- 32

Problem 6.9 -------------------------------------------------------------------------------------------- 33

Problem 6.10 ------------------------------------------------------------------------------------------ 34

Problem 6.11------------------------------------------------------------------------------------------- 35

Problem 6.12 ------------------------------------------------------------------------------------------ 35

Problem 6.13------------------------------------------------------------------------------------------ 36

Problem 6.14 ------------------------------------------------------------------------------------------ 37

Problem 6.15 ------------------------------------------------------------------------------------------ 38

Problem 6.16 ------------------------------------------------------------------------------------------ 39

Problem 6.17 ------------------------------------------------------------------------------------------ 40


- 22 -

Problem 6.1

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p661 is

port(clk: in std_logic;

count: out integer range 0 to 255);

end p661;

--------------------------------------------------------------------------------------------------------------------------------


signal count1, count2: integer range 0 to 127 := 0;

begin

process(clk)

begin

if (clk'event and clk='1') then

count1 <= count1+1;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(clk)

begin


count2 <= count2+1;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

count <= count1+count2;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 6.2

• Code

library IEEE;






- 23 -

--------------------------------------------------------------------------------------------------------------------------------

entity p62 is

generic ( n:integer := 4);

port(clk,rst,din: in std_logic;

dout: out std_logic :='0');

end p62;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(clk,rst)

variable tmp: std_logic_vector (n-1 downto 0) := (others => '0');

begin

if (rst='1') then

tmp := (others => '0');

dout <= '0';

elsif (clk'event and clk='1') then

for i in tmp'high downto 1 loop

tmp(i) := tmp(i-1);

end loop;

tmp(0) := din;

dout <= tmp(tmp'high);

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 6.3

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p3 is

generic(n : integer := 3);

port(r: in std_logic_vector (2**n-1 downto 0);

outp: out std_logic_vector (n-1 downto 0));



- 24 -

end p3;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(r)

begin

if(r(7)='1') then

outp <= "111";

elsif(r(6)='1') then

outp <= "110";


outp <= "101";


outp <= "100";


outp <= "011";


outp <= "010";


outp <= "001";

else

outp<= "000";

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation


Problem 6.3b

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p63b is

port(r: in std_logic_vector (3 downto 0);

outp: out std_logic_vector(1 downto 0));

end p63b;

--------------------------------------------------------------------------------------------------------------------------------


- 25 -


begin

process(r)

begin

case r is

when "1000"|"1001"|"1010"|"1011"|"1100"|"1101"|"1110"|"1111" => outp <= "11";

when "0100"|"0101"|"0110"|"0111" => outp <= "10";

when "0010"|"0011" => outp <= "01";

when others => outp <= "00";

end case;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

--------------------------------------------------------Another solution------------------------------------------------------

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

port (din: in std_logic_vector (7 downto 0);

dout: out integer range 0 to 7);

end p4;

--------------------------------------------------------------------------------------------------------------------------------


begin

process (din)

variable internal : integer range 0 to 7;

begin

internal:= 0;

for i in din'range loop

if (din(i)= '1') then

internal := i;

exit;

end if;

end loop;

dout <= internal;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

Figure 6-4 Simulation results for problem 6.3b


- 26 -

• Simulation

Problem 6.4

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p5 is

generic (n: integer := 8);

port (clk : in std_logic;

clkout: out std_logic := '1');

end p5;

--------------------------------------------------------------------------------------------------------------------------------


begin

process (clk)

variable count : integer range 0 to 7 := 0;

begin


count:= count+1;

if (count=n/2) then

clkout<= '0';

elsif (count = n) then

clkout<= '1';

count := 0;

end if;

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure 6-5 Simulation results for problem 6.3b



- 27 -

Problem 6.5

It is possible to multiply the frequency using PLL within the FPGA. Actually, you can do 2

multiplication by sensing both the risng edge and falling edge of the clock using HDL.

Problem 6.6

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p6 is

port (start,stop,rst, clk : in std_logic;

sec1,sec2: out integer range 0 to 59;

min : out integer range 0 to 9;

digit1,digit2,digit3: out std_logic_vector(6 downto 0));

end p6;

--------------------------------------------------------------------------------------------------------------------------------


begin

process (clk,start,stop,rst)

variable tmin, tsec1,tsec2: integer :=0;

begin

if (rst = '1') then

tsec1 :=0;

tsec2 :=0;

tmin :=0;

elsif (clk'event and clk = '1') then

if (start = '1' and stop = '0') then

tsec1 := tsec1 + 1;

if (tsec1 = 10) then

tsec1 := 0;

tsec2 := tsec2+1;

if (tsec2 = 6) then

tsec2 := 0;

tmin := tmin+1;

if (tmin = 10) then

tmin :=0;

tsec1 :=0;

tsec2 := 0;

end if;

end if;

end if;

end if;

end if;

case tsec1 is


- 28 -

when 0 => digit1 <= "1111110"; --7E

when 1 => digit1 <= "0110000"; --30

when 2 => digit1 <= "1101101"; --6D

when 3 => digit1 <= "1111001"; --79

when 4 => digit1 <= "0110011"; --33

when 5 => digit1 <= "1011011"; --5B

when 6 => digit1 <= "1011111"; --5F

when 7 => digit1 <= "1110000"; --70

when 8 => digit1 <= "1111111"; --7F

when 9 => digit1 <= "1111011"; --7B

when OTHERS => NULL;

end case;

case tsec2 is

when 0 => digit2 <= "1111110"; --7E

when 1 => digit2 <= "0110000"; --30

when 2 => digit2 <= "1101101"; --6D

when 3 => digit2 <= "1111001"; --79

when 4 => digit2 <= "0110011"; --33

when 5 => digit2 <= "1011011"; --5B


end case;

case tmin is

when 0 => digit3 <= "1111110"; --7E

when 1 => digit3 <= "0110000"; --30

when 2 => digit3 <= "1101101"; --6D

when 3 => digit3 <= "1111001"; --79

when 4 => digit3 <= "0110011"; --33

when 5 => digit3 <= "1011011"; --5B

when 6 => digit3 <= "1011111"; --5F

when 7 => digit3 <= "1110000"; --70

when 8 => digit3 <= "1111111"; --7F

when 9 => digit3 <= "1111011"; --7B


end case;

min<= tmin;

sec1 <= tsec1;

sec2 <= tsec2;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------


- 29 -

• Simulation

Problem 6.7

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p67 is

port(p,clk:in std_logic;

sec1: out integer range 0 to 9;

sec2: out integer range 0 to 5;

min : out integer range 0 to 9;

digit1,digit2,digit3: out std_logic_vector(6 downto 0));

end p67;

--------------------------------------------------------------------------------------------------------------------------------


signal start,stop,rst: std_logic := '0';

begin

--------------------------------------------------------------------------------------------------------------------------------

process(p)

variable flip : std_logic := '0';

begin

if (p'event and p='1') then

if(flip='0') then

start<='1';

stop<='0';

flip:='1';

else

start<='0';

stop<='1';

flip:='1';



- 30 -

end if;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(p,clk)

variable count: integer := 0;

begin

if(clk'event and clk='1') then

if(p='1') then

count := count+1;

if (count=5) then

rst <= '1';

end if;

else

count:=0;

end if;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process (clk,start,stop,rst)

variable tmin, tsec1,tsec2: integer :=0;

begin

if (rst = '1') then

tsec1 :=0;

tsec2 :=0;

tmin :=0;

elsif (clk'event and clk = '1') then

if (start = '1' and stop = '0') then

tsec1 := tsec1 + 1;

if (tsec1 = 10) then

tsec1 := 0;

tsec2 := tsec2+1;

if (tsec2 = 6) then

tsec2 := 0;

tmin := tmin+1;

if (tmin = 10) then

tmin :=0;

tsec1 :=0;

tsec2 := 0;

end if;

end if;

end if;

end if;

end if;

case tsec1 is

when 0 => digit1 <= "1111110"; --7E

when 1 => digit1 <= "0110000"; --30

when 2 => digit1 <= "1101101"; --6D


- 31 -

when 3 => digit1 <= "1111001"; --79

when 4 => digit1 <= "0110011"; --33

when 5 => digit1 <= "1011011"; --5B

when 6 => digit1 <= "1011111"; --5F

when 7 => digit1 <= "1110000"; --70

when 8 => digit1 <= "1111111"; --7F

when 9 => digit1 <= "1111011"; --7B


end case;

case tsec2 is

when 0 => digit2 <= "1111110"; --7E

when 1 => digit2 <= "0110000"; --30

when 2 => digit2 <= "1101101"; --6D

when 3 => digit2 <= "1111001"; --79

when 4 => digit2 <= "0110011"; --33

when 5 => digit2 <= "1011011"; --5B


end case;

case tmin is

when 0 => digit3 <= "1111110"; --7E

when 1 => digit3 <= "0110000"; --30

when 2 => digit3 <= "1101101"; --6D

when 3 => digit3 <= "1111001"; --79

when 4 => digit3 <= "0110011"; --33

when 5 => digit3 <= "1011011"; --5B

when 6 => digit3 <= "1011111"; --5F

when 7 => digit3 <= "1110000"; --70

when 8 => digit3 <= "1111111"; --7F

when 9 => digit3 <= "1111011"; --7B


end case;

min<= tmin;

sec1 <= tsec1;

sec2 <= tsec2;

end process;

end Behavioral;

• Simulation



- 32 -

Problem 6.8

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p8b is

port (p: out std_logic;

din : in std_logic_vector (7 downto 0));

end p8b;

--------------------------------------------------------------------------------------------------------------------------------


begin

--------------------------------------------------------------------------------------------------------------------------------

process (din)

variable tmp : std_logic_vector (7 downto 0) := (others => '0');

begin

tmp(0):= din(0);

for i in 1 to din'high loop

tmp(i) := din(i) xor tmp(i-1);

end loop;

p<= tmp(din'high);

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

---------------------------------------------------------Another Solution----------------------------------------------------

• Code

library IEEE;


--------------------------------------------------------------------------------------------------------------------------------

entity p68 is


port(din: in std_logic_vector (n-1 downto 0);

p: out std_logic);

end p68;

--------------------------------------------------------------------------------------------------------------------------------



- 33 -


begin

process(din)

variable tmp : std_logic := '0';

begin

tmp :='0';


if(din(i)='1') then

tmp:=not(tmp);

end if;

end loop;

p <= tmp;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

--------------------------------------------------------------------------------------------------------------------------------

Problem 6.9

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p9 is


port (din: in std_logic_vector (2**n-1 downto 0);

count : out std_logic_vector (n-1 downto 0));

end p9;

--------------------------------------------------------------------------------------------------------------------------------


begin

process (din)

variable tmp: std_logic_vector (n-1 downto 0);

begin

tmp := (others => '0');


if (din(i)= '1')then

tmp := tmp +1;

end if;



- 34 -

end loop;

count <= tmp;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 6.10

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p10 is


port(din : in std_logic_vector (n-1 downto 0);

dout : out std_logic_vector (2**n-1 downto 0) := "00000000");

end p10;

--------------------------------------------------------------------------------------------------------------------------------


begin

process (din)

variable count : integer range 0 to 2**n-1;

begin

dout <= (others => '0');

count := 0;


if din(i) = '1' then

count := count+1;

end if;

end loop;

dout(count) <= '1';

end process;

end Behavioral;

• Simulation




- 35 -

Problem 6.11

• Code

library IEEE;




use work.my_data_types.all;

--------------------------------------------------------------------------------------------------------------------------------

entity p611 is

generic (m: integer := 3);

port(x: in vector_array (2**m-1 downto 0);

sel: in std_logic_vector (m-1 downto 0);

y: out std_logic_vector (2**m-1 downto 0));

end p611;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(x,sel)

variable tmp : integer range 0 to x'high;

begin

for i in sel'range loop

if(sel(i)='1')then

tmp := tmp*2+1;

else

tmp:= 2*tmp;

end if;

end loop;

y <= x(tmp);

end process;

end Behavioral;

Problem 6.12

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity problem6 is


port(inp: in std_logic_vector (n-1 downto 0);

outp: out std_logic_vector (n-1 downto 0);

shift: in std_logic);

end problem6;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of problem6 is

begin

process(inp,shift)


- 36 -

begin

if (shift = '1') then

outp <= inp(n-2 downto 0) & '0';

else

outp <= inp;

end if;

end process;

end Behavioral;

• Simulation

Problem 6.13

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p613 is



cin: in std_logic;


end p613;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(sel,a,b,cin)

begin

if (sel(3)='0') then

case sel(2 downto 0)is

when "000" => y <= a;

when "001" => y <= a+1;

when "010" => y <= a-1;

when "011" => y <= b;

when "100" => y <= b+1;

when "101" => y <= b-1;

when "110" => y <= a+b;

when others => y <= a+b+cin;

end case;

else



- 37 -

case sel(2 downto 0)is

when "000" => y <= not(a);

when "001" => y <= not(b);

when "010" => y <= a and b;

when "011" => y <= a or b;

when "100" => y <= a nand b;

when "101" => y <= a nor b;

when "110" => y <= a xor b;

when others => y <= a xnor b;

end case;

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 6.14

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p614a is



cin: in std_logic;



end p614a;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(sel,a,b)

variable carry: std_logic_vector (7 downto 0) := (others =>'0');

begin

carry(0) := cin;

case sel is



- 38 -

when "00" => outp <= a+b+carry;

when "01" => outp <= signed(a)+signed(b) + signed(carry);

when "10" => outp <= a-b;

when others => outp <= signed(a) - signed(b);

end case;

end process;

end Behavioral;

• Simulation

Problem 6.15

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p165 is


sel: in std_logic;

agtb:out std_logic;

bgta:out std_logic;

aeqb:out std_logic);

end p165;

--------------------------------------------------------------------------------------------------------------------------------


begin

process(a,b,sel)

variable tmp: std_logic :='0';

begin

agtb <= '0';

bgta <= '0';

aeqb <= '0';

if (sel='0') then

if (a>b) then

agtb <= '1';

elsif(a=b) then

aeqb <= '1';



- 39 -

else

bgta <= '1';

end if;

else

if (signed(a)>signed(b)) then

agtb <= '1';

elsif(signed(a)= signed(b)) then

aeqb <= '1';

else

bgta <= '1';

end if;

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 6.16

a.) Two different data types: tmp in inteher while C0 is std_logic.

b.) Ripple adder using concurrent statements.

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p166 is


cin: in std_logic;

s: out std_logic_vector (7 downto 0);


end p166;

--------------------------------------------------------------------------------------------------------------------------------


signal carry: std_logic_vector (8 downto 0) := (others =>'0');

begin

carry(0) <= cin;



- 40 -

G1: for i in 0 to a'high generate

s(i) <= a(i) xor b(i) xor carry(i);

carry(i+1) <= (a(i) and b(i))or(a(i)and carry(i))or(b(i)and carry(i));

end generate;

cout <= carry(carry'high);

end Behavioral;

• Simulation

Problem 6.17

• Architecture 1 ARCHITECTURE arch1 OF dff IS BEGIN PROCESS (clk, rst) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END arch1; ----------------------------------------------------It works greatly with asynchronous reset-------------------------------------

• Architecture 2 ARCHITECTURE arch2 OF dff IS BEGIN PROCESS (clk) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END arch2; ----------------------------------------It has a problem------------------------------------------------------------------

The problem is mainly with reset function. It is reported that this FF has asynchronous reset.

However, this process will sense the variations of rst signals only on clock change.

--------------------------------------------------------------------------------------------------------------------------------

• Architecture 3 ARCHITECTURE arch3 OF dff IS BEGIN PROCESS (clk) BEGIN



- 41 -

IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT) THEN q <= d; END IF; END PROCESS; END arch3; ----------------------------------------------It has a problem---------------------------------------------------------------------------- It has two defects, the first one is the asynchronous reset function as it won’t work properly-explained in previous architecture- Besides, on synthesis this circuit, XST halts as it doesn’t work with this clock event. ------------------------------------------------------------------------------------------------------------------------------------------------

• Architecture 4 ARCHITECTURE arch4 OF dff IS BEGIN PROCESS (clk) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk='1') THEN q <= d; END IF; END PROCESS; END arch4; ------------------------------------------It may work but not properly-----------------------------------------------

It has the same problem of the previous architecture concerning the asynchronous reset. In

addition, no FF will be inferred as no signal is assigned at the transition of another signal. Thus, it

will be combinational circuit. However, due to incomplete truth table of clk status, a kind of

memory will be generated (a latch will be formed for the q to hold its previous value).

The following warning will be reported: “Found 1-bit latch for signal <q>.”

--------------------------------------------------------------------------------------------------------------------------------

• Architecture 5 ARCHITECTURE arch5 OF dff IS BEGIN PROCESS (clk, rst, d) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk='1') THEN q <= d; END IF; END PROCESS; END arch5; --------------------------------------------------------It won’t work properly-----------------------------------------------------------The same as previous beside, this circuit will have an input running the process at each time: This is actually tends to be combinational circuit. ------------------------------------------------------------------------------------------------------------------------------------------------


- 42 -

Chapter 7:”Signals and Variables”

Problem 7.1 ----------------------------------------------------------------------------------- 43

Problem 7.2 ------------------------------------------------------------------------------------ 43

Problem 7.3------------------------------------------------------------------------------------- 44

Problem 7.4------------------------------------------------------------------------------------- 45

Problem 7.5------------------------------------------------------------------------------------- 46

Problem 7.6-------------------------------------------------------------------------------------- 47

Problem 7.7-------------------------------------------------------------------------------------- 48


- 43 -

CONSTANT max : INTEGER := 10;

SIGNAL x: INTEGER RANGE -10 TO 10;

SIGNAL y: BIT_VECTOR (15 DOWNTO 0);

VARIABLE z: BIT;

Problem 7.1

• x <= 5; -----------> Legal

• x <= y(5); ----------- > Illegal Different data types

• z <= '1'; ----------- > Illegal Wrong data assignment z:=’1’;

• z := y(5); ----------------> Legal

• WHILE i IN 0 TO max LOOP...--------------> Illegal For in in 0 to max loop

• FOR i IN 0 TO x LOOP... ----------------------> Legal

• G1: FOR i IN 0 TO max GENERATE...----------------> Legal

• G1: FOR i IN 0 TO x GENERATE...------------------------> Legal

Problem 7.2

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity datadelay is

port ( d : in std_logic_vector (3 downto 0);

clk: in std_logic;

sel: in integer range 0 to 3;


end datadelay;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of datadelay is

type array_1 is array (0 to 3) of std_logic_vector (3 downto 0);

signal q : array_1 := ("0000","0000","0000","0000") ;

begin

process (clk, sel)

begin

if (clk'event and clk = '1') then

q <= d & q(0 to 2);

end if;

end process;

y <= q(sel);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Figure7-1 Simulation results for problem 7.2


- 44 -

Problem 7.3

• Architecture1 ENTITY dff IS PORT ( d, clk: IN BIT; q, qbar: BUFFER BIT); END dff; ------- Solution 1 ------------------- ARCHITECTURE arch1 OF dff IS SIGNAL temp: BIT; BEGIN PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN temp <= d; q <= temp; qbar <= NOT temp; END IF; END PROCESS; END arch1; -------------------------------------------------It won’t work Properly-------------------------------------------------

Both q and qbar will be delayed by one clock cycle form the input signal d.

--------------------------------------------------------------------------------------------------------------------------------

•

•

•

•

•

• Architecture2 ARCHITECTURE arch2 OF dff IS SIGNAL temp: BIT; BEGIN PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN temp <= d; END IF; q <= temp; qbar <= NOT temp; END PROCESS; END arch2; -----------------------------------------------It won’t work Properly-------------------------------------------------------------------- It will be delayed by half clock cycle. ------------------------------------------------------------------------------------------------------------------------------------------------

Figure7-2 Simulation results for problem 7.3 arc1



- 45 -

• Architecture3 ARCHITECTURE arch3 OF dff IS SIGNAL temp: BIT; BEGIN PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN temp <= d; END IF; END PROCESS; q <= temp; qbar <= NOT temp; END arch3; -----------------------------------------------------------It works well--------------------------------------------------------------------

Problem 7.4

• Architecture1 ARCHITECTURE arch1 OF dff IS BEGIN PROCESS (clk) VARIABLE temp: BIT; BEGIN IF (clk'EVENT AND clk='1') THEN temp := d; q <= temp; qbar <= NOT temp; END IF; END PROCESS; END arch1; -----------------------------------------------------It works well--------------------------------------------------------------------------

• Architecture2 ARCHITECTURE arch2 OF dff IS BEGIN PROCESS (clk) VARIABLE temp: BIT; BEGIN `IF (clk'EVENT AND clk='1') THEN




- 46 -

temp := d; q <= temp; qbar <= NOT q; END IF; END PROCESS; END arch2; ----------------------------------------------Not ok----------------------------------------------------------------------------------------- Qbar will be delayed by one clock cycle form the input ------------------------------------------------------------------------------------------------------------------------------------------------

• Architecture3 ARCHITECTURE arch3 OF dff IS BEGIN PROCESS (clk) VARIABLE temp: BIT; BEGIN IF (clk'EVENT AND clk='1') THEN temp := d; q <= temp; END IF; END PROCESS; qbar <= NOT q; END arch3; ------------------------------------------It Works-------------------------------------------------------------------------------------------

Problem7.5

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p75 is


outp: out integer range 0 to 15);

end p75;




- 47 -

--------------------------------------------------------------------------------------------------------------------------------


begin

process(clk)

variable tmp: integer range 0 to 16;

begin


tmp :=tmp+1;

outp := tmp;

if (tmp=16) then

tmp :=0;

end if;

outp <= tmp;

end if;

end process;

end Behavioral;

• Simulation

Problem 7.6

• Code

LIBRARY ieee;

USE ieee.std_logic_1164.all;

--------------------------------------------------------------------------------------------------------------------------------

ENTITY decoder IS

PORT ( ena : IN STD_LOGIC;

sel : IN INTEGER RANGE 0 TO 7;

x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

END decoder;

--------------------------------------------------------------------------------------------------------------------------------

ARCHITECTURE ok OF decoder IS

BEGIN

PROCESS (ena, sel)

variable tmp: std_logic_vector(7 downto 0)

BEGIN

tmp:= (OTHERS => '1');

IF (ena='1') THEN

tmp(sel) := ‘0’;

END IF;

x <= tmp;

Figure7-8 Simulation results for problem 7.5


- 48 -

END PROCESS;

END ok;

--------------------------------------------------------------------------------------------------------------------------------

Problem 7.7

• RTL Schematic

• Technology Schematic

Figure7-9 RTL schematic for FF(q and qbar)

Figure7-9b Technology schematic for FF(q and qbar)


- 49 -

Chapter 8 :“State Machines”

Problem 8.1 ------------------------------------------------------------------------------------------------ 50

Problem 8.2 ----------------------------------------------------------------------------------------------- 51

Problem 8.3------------------------------------------------------------------------------------------------ 56

Problem 8.4------------------------------------------------------------------------------------------------ 58

Problem 8.6----------------------------------------------------------------------------------------------- 59

Problem 8.7------------------------------------------------------------------------------------------------ 60


- 50 -

Problem 8.1

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p1 is


rst,inp: in std_logic;


end p1;

-------------------------------------------------------------------------------------------------------------------------------


TYPE state is (one, two, three, four);

signal nx_state, pr_state: state;

begin

process (clk)

begin

if (rst='1') then

pr_state <= one;


pr_state <= nx_state;

end if;

end process;

process (pr_state,inp)

begin

case pr_state is

when one =>

outp <= "00";

if (inp='1') then

nx_state <= two;

else

nx_state <= one;

end if;

when two =>

outp <= "01";

if (inp='1') then

nx_state <= four ;

else

nx_state <= three;

end if;

when three =>

outp <= "10";

if (inp='1') then

nx_state <= four ;

else

nx_state <= three;


- 51 -

end if;

when four =>

outp <= "11";

if (inp='1') then

nx_state <= one ;

else

nx_state <= two;

end if;

end case;

end process;

end Behavioral;

• Simulation

Problem 8.2

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p2 is


out2:out std_logic;

out1: out std_logic);

end p2;

--------------------------------------------------------------------------------------------------------------------------------


TYPE state is (one, two, three,four);

signal nx_state,pr_state,nx_state1,pr_state1,nx_state2,pr_state2,nx_state3,pr_state3: state;

signal outa, outb, outc : std_logic := '0';

begin

--------------------------------------------------------------------------------------------------------------------------------

process(clk)

begin



pr_state1 <= nx_state1;

Figure 8.1 Simulation Results for problem 8.1


- 52 -


end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process (clk)

begin

if (clk'event and clk ='0') then


end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_state)

begin

case pr_state is

when one =>

nx_state <= two;

out1 <= '0';

when two =>

nx_state <= three;

out1 <= '1';

when three =>

nx_state <= four;

out1 <= '0';

when four =>

nx_state <= one;

out1 <= '0';

end case;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_state1)

begin

case pr_state1 is

when one =>

nx_state1 <= two;

outa <= '0';

when two =>

nx_state1 <= three;

outa <= '1';

when three =>

nx_state1 <= four;

outa <= '0';

when four =>

nx_state1 <= one;

outa <= '0';

end case;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_state2)


- 53 -

begin

case pr_state2 is

when one =>

nx_state2 <= two;

outb <= '0';

when two =>

nx_state2 <= three;

outb <= '0';

when three =>

nx_state2 <= four;

outb <= '1';

when four =>

nx_state2 <= one;

outb <= '0';

end case;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_state3)

begin

case pr_state3 is

when one =>

nx_state3 <= two;

outc <= '0';

when two =>

nx_state3 <= three;

outc <= '0';

when three =>

nx_state3 <= four;

outc <= '1';

when four =>

nx_state3 <= one;

outc <= '0';

end case;

end process;

--------------------------------------------------------------------------------------------------------------------------------

out2 <= outa or (outc and outb);

end Behavioral;

• Simulation



- 54 -

Problem 8.3

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p93b is

port(go,clk,stop: in std_logic;

up: out std_logic := '0';

down: out std_logic := '1');

end p93b;

--------------------------------------------------------------------------------------------------------------------------------


type state is (start,wait1,pressed,wait0,released);

signal pr_state, nx_state: state;

begin

process(clk)

begin



end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_state,go,clk,stop)

variable count: integer :=0;

variable flip : std_logic :='0';

begin

if(pr_state = wait1 or pr_state = wait0) then


count := count+1;

flip := '0';

if(count= 5) then

count := 0;

flip := '1';

end if;

end if;

end if;

if(stop='1') then

up <= '0';

down <= '1';

nx_state <= start;

else

case pr_state is

when start =>

nx_state <= start;

down <= '1';

up <= '0';


- 55 -

if(go='1') then

nx_state <= wait1;

down <= '0';

up <= '0';

else

nx_state <= wait0;

up <= '0';

down <='0';

end if;

when wait1 =>

if (flip = '1') then

nx_state <= pressed;

up <='1';

down <= '0';

else

nx_state <= wait1;

up <= '0';

down <= '0';

end if;

when pressed =>

if (go='0') then

nx_state <= wait0;

up <= '0';

down <= '0';

else

nx_state <= pressed;

up <= '1';

down <= '0';

end if;

when wait0 =>

if (flip='1') then

nx_state <= released;

down <='1';

up <= '0';

else

nx_state <= wait0;

down <= '0';

up <= '0';

end if;

when released =>

if (go='1') then

nx_state <= wait1;

down <= '0';

up <= '0';


- 56 -

else

nx_state <= released;

down <= '1';

up <= '0';

end if;

end case;

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 8.4

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity key_pad is

port(clk,rst: in std_logic;

row: in std_logic_vector (3 downto 0);

col: out std_logic_vector (2 downto 0);

new_data: out std_logic :='0';

data: out std_logic_vector (6 downto 0));

end key_pad;

architecture Behavioral of key_pad is

signal pressed : std_logic :='0';

signal scan : std_logic_vector (3 downto 0) := "0000";

signal count: std_logic_vector (1 downto 0) := "00";

signal digit: std_logic_vector (3 downto 0);

begin

--------------------------------Scanning--------------------------------------------------------------------

process(clk,pressed,rst)

begin

if (rst='1') then



- 57 -

scan <= "0000";

elsif(clk'event and clk='1') then

if (pressed = '0') then

scan <= scan + 1;

if(scan = "1011") then

scan <= "0000";

end if;

end if;

end if;

end process;

col <= "110" when scan(3 downto 2) = "00" else

"101" when scan(3 downto 2) = "01" else

"011" when scan(3 downto 2) = "10" else

"111";

pressed <= not (row(0)) when (scan(1 downto 0) = "00") else

not (row(1)) when (scan(1 downto 0) = "01") else

not (row(2)) when (scan(1 downto 0) = "10") else

not (row(3));

with scan select

digit <= "0000" when "0111",

"0001" when "0000",

"0010" when "0100",

"0011" when "1000",

"0100" when "0001",

"0101" when "0101",

"0110" when "1001",

"0111" when "0010",

"1000" when "0110",

"1001" when "1010",

"1010" when "0011",

"1011" when "1011",

"1111" when others;

-------------------------------Debouncing & Encoding---------------------------------------------------------

process(clk)

begin

if(pressed='0') then

count <= "00";

elsif(clk'event and clk='1') then

if(count/="11") then

count<= count+1;

end if;

end if;

if(count="10" and pressed='1') then

new_data<= '1';

case digit is

when "0000" => data <= "0110000";

when "0001" => data <= "0110001";


- 58 -

when "0010" => data <= "0110010";

when "0011" => data <= "0110011";

when "0100" => data <= "0110100";

when "0101" => data <= "0110101";

when "0110" => data <= "0110110";

when "0111" => data <= "0110111";

when "1000" => data <= "0111000";

when "1001" => data <= "0111001";

when "1010" => data <= "0111010";

when "1011" => data <= "0111011";

when others => data <= (others =>'0');

end case;

else

new_data <= '0';

data <= (others =>'0');

end if;

end process;

end Behavioral;

• Simulation

Problem 8.6

• Code

library IEEE;




entity p86 is


out1,out2: out std_logic);

end p86;



- 59 -


signal s1,s2,s3 : std_logic := '0';

begin

process (clk)


begin


s1 <= '0';

s2 <= '0';

count := count +1;

if (count= 1) then

s1 <= '1';

elsif (count = 2) then

s2 <= '1';


count:=0;

end if;

end if;

end process;

process (clk)


begin

s3 <= '0';


count:= count+1;

if (count = 2) then

s3 <= '1';


count := 0;

end if;

end if;

end process;

out1 <= s1;

out2 <= s1 or (s2 and s3);

end Behavioral;

• Simulation



- 60 -

Problem 8.7

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p87b is


outp: out std_logic);

end p87b;

--------------------------------------------------------------------------------------------------------------------------------


signal s1 :std_logic := '1';

signal s2: std_logic := '0';

begin

process (clk)


begin


count := count +1;

if (count= 1) then

s1 <= '1';


s1 <= '1';


s1 <= '0';

count:=0;

end if;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process (clk)


begin


count:= count+1;

if (count = 1) then

s2 <= '0';


s2 <= '1';


s2 <= '1';

count := 0;

end if;

end if;

end process;

outp <= s1 and s2;


- 61 -

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 62 -

Chapter 9: “Additional Circuits Design”

Problem 9.1----------------------------------------------------------------------- 63

Problem 9.2------------------------------------------------------------------------ 63

Problem 9.3------------------------------------------------------------------------ 64

Problem 9.4------------------------------------------------------------------------ 68

Problem 9.5------------------------------------------------------------------------- 70

Problem 9.6------------------------------------------------------------------------- 71

Problem 9.7------------------------------------------------------------------------- 75

Problem 9.8------------------------------------------------------------------------- 79


- 63 -

Problem 9.1

• Solution

Actually, the main problem with this code is that “IT DOESn’t work as shifter”. Here is how it

works.First, it replaces the first shift bits of the input vector with zeros. Then, it works on shifting

the remaining bits by one place only . This can be illustrated by the following example. Consider

this input vector “11010001” shifted by 2bits.

Table 9-1 : Example for problem 9.1

Input vector Required Output Actual Output

1 0 1

1 1 0

0 0 1

1 0 0

0 0 0

0 1 0

0 0 0

1 0 0

In addition, it has some problems with syntax as it deals with the input shift as an

integer(putting it in loop range – permitted only for integers) , However it is defined as

std_logic_vector. This means a conversion statement is required.

Finally, the loop range must be constant values, this will be rejected within the synthesis

process.

Problem 9.2

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p2 is

Generic (n : integer := 3);

port (a,b: in std_logic_vector (n downto 0);

r: out std_logic_vector (n downto 0);

err: out std_logic;

q: out std_logic_vector (n downto 0));

end p2;

--------------------------------------------------------------------------------------------------------------------------------


SUBTYPE long IS STD_LOGIC_VECTOR (2*n DOWNTO 0);

TYPE vec_array IS ARRAY (n DOWNTO 0) OF long;

SIGNAL a_input, b_input: vec_array;

signal tmp : std_logic_vector (2*n downto 0);

begin

err <= '1' when (b= "0000") else


- 64 -

'0';

b_input(n)(2*n downto n) <= b;

b_input(n)((n-1) downto 0) <= (others =>'0');

a_input(n)(n downto 0) <= a;

a_input(n)(2*n downto (n+1)) <= (others =>'0');

G1: For i in (n-1) downto 0 generate

b_input(i) <= '0' & b_input(i+1)(2*n downto 1);

r(i+1) <= '1' when (a_input(i+1) >= b_input(i+1)) ELSE

'0';

a_input(i) <= (a_input(i+1)-b_input(i+1)) when (a_input(i+1) >= b_input(i+1)) ELSE

a_input(i+1);

end generate;

r(0) <= '1' when (a_input(0) >= b_input(0)) ELSE

'0';

tmp <= a_input(0)-b_input(0)when (a_input(0) >= b_input(0)) ELSE

a_input(0);

q <= tmp(n downto 0);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 9.3

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p93 is

PORT ( clk, rst: IN STD_LOGIC;

nickel_in, dime_in, quarter_in,coin_valid: IN std_logic;

no_dime: IN STD_LOGIC;

coin_accepted: OUT std_logic :='0';

candy_out, nickel_out, dime_out: OUT STD_LOGIC);

end p93;

--------------------------------------------------------------------------------------------------------------------------------




- 65 -

TYPE state IS (st0, st5, st10, st15, st20, st25,

st30, st35, st40, st45);

SIGNAL present_state, next_state: STATE;

SIGNAL accept: std_logic := '0';

begin

--------------------------------------------------------------------------------------------------------------------------------

PROCESS (rst, clk)

BEGIN

IF (rst='1') THEN

present_state <= st0;

ELSIF (clk'EVENT AND clk='1') THEN

present_state <= next_state;

coin_accepted <= accept;

END IF;

END PROCESS;

-------------------------------------------------------------------------------------------------------------------------------

PROCESS (present_state, nickel_in, dime_in, quarter_in,coin_valid)

variable valid: std_logic := '0';

variable change: std_logic_vector(1 downto 0) :="00";

BEGIN

If (accept='1') then

valid:='0';

elsif(coin_valid'event and coin_valid='1') then

valid:='1';

end if;

accept <= '0';

CASE present_state IS

WHEN st0 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in='1' and valid='1') THEN next_state <= st5; accept <= '1';

ELSIF (dime_in='1' and valid='1') THEN next_state <= st10; accept <= '1';

ELSIF (quarter_in='1' and valid='1') THEN next_state <= st25; accept <= '1';

ELSE next_state <= st0;

END IF;

WHEN st5 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';





END IF;

WHEN st10 =>


- 66 -

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';





END IF;

WHEN st15 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';





END IF;

WHEN st20 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';





END IF;

WHEN st25 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '0';

next_state <= st0;

WHEN st30 =>

candy_out <= '1';

nickel_out <= '1';

dime_out <= '0';

next_state <= st0;

WHEN st35 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '1';

next_state <= st0;

if(no_dime='1') then

nickel_out <= '1';


- 67 -

dime_out <= '0';

next_state <= st40;

change:="01";

end if;

WHEN st40 =>

candy_out <= '0';

nickel_out <= '1';

dime_out <= '0';

next_state <= st35;

if(change ="01") then

next_state <= st0;

change := "00";

end if;

WHEN st45 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '1';

next_state <= st35;

if(no_dime='1') then

nickel_out <= '1';

dime_out <= '0';

next_state <= st40;

change:="11";

end if;

END CASE;

END PROCESS;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 68 -

Problem9.4

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

port (clk,din,rst: in std_logic;

data_out : out std_logic_vector (7 downto 0);

err, data_ok: out std_logic := '0');

end p4;

--------------------------------------------------------------------------------------------------------------------------------


type state is (start, zero, one, two, three, four, five, six, seven, parity, stop);

signal pr_state,nx_state: state;

signal reg: std_logic_vector (7 downto 0) := (others => '0');

signal tmp,err_tmp : std_logic := '0';

signal data_ok_r: std_logic := '0';

begin

process (clk,rst)

begin

if (rst='1') then

pr_state <= start;



data_out <= reg;

err <= err_tmp;

data_ok <= data_ok_r;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(clk,din)

begin

case pr_state is

when start =>

if (din = '1') then

nx_state <= zero;

reg <= (others => '0');

data_ok_r <= '0';

err_tmp <= '0';

else

nx_state <= start;

end if;

when zero =>

nx_state <= one;

reg(0) <= din;


- 69 -

when one =>

nx_state <= two;

reg(1) <= din;

when two =>

nx_state <= three;

reg(2) <= din;

when three =>

nx_state <= four;

reg(3) <= din;

when four =>

nx_state <= five;

reg(4) <= din;

when five =>

nx_state <= six;

reg(5) <= din;

when six =>

nx_state <= seven;

reg(6) <= din;

when seven =>

nx_state <= parity;

reg(7) <= din;

when parity =>

tmp <= (reg(0)xor reg(1) xor reg(2) xor reg(3) xor reg(4) xor reg(5) xor reg(6) xor reg(7)

xor din);

if (tmp='1') then

err_tmp<='1';

nx_state <= start;

else

nx_state <= stop;

err_tmp <='0';

end if;

when stop =>

if (din = '0') then

err_tmp <='0';

data_ok_r <='1';

else

err_tmp <='1';

data_ok_r <= '0';

end if;


- 70 -

nx_state <= start;

end case;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 9.5

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p5 is

port(data_in: in std_logic_vector (7 downto 0);

data_ready: in std_logic;

clk: in std_logic;

dout: out std_logic);

end p5;

--------------------------------------------------------------------------------------------------------------------------------


signal p: std_logic := '0';

signal reg: std_logic_vector (11 downto 1) := (others => '1');

begin

process(data_in)

variable tmp: std_logic_vector (7 downto 0);

begin

tmp(0):= data_in(0);

for i in 1 to 7 loop

tmp(i) := data_in(i) xor tmp(i-1);

end loop;

p <= tmp(7);

end process;

--------------------------------------------------------------------------------------------------------------------------------

process (clk)

variable count: integer range 0 to 11:=0;



- 71 -

variable flag: std_logic := '0';

begin


if (data_ready = '1' and flag= '0') then

flag :='1';

count := count+1;

reg <= ('1'& p & data_in(7 downto 0) & '0');

elsif (flag='1') then

reg <= ('0'& reg(11 downto 2));

count := count+1;

if (count = 11) then

count :=0;

flag :='0';

end if;

end if;

end if;

dout <= reg(1);

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 9.6

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p6 is

port(clk,stop, direction: in std_logic;

speed: in std_logic_vector (1 downto 0);

dout: out std_logic_vector (6 downto 0));

end p6;

--------------------------------------------------------------------------------------------------------------------------------


constant time21: integer := 2;



- 72 -




constant time1 : integer := 1;

type states is (a,ab,b,bc,c,cd,d,de,e,ef,f,fa);

signal pr_state, nx_state: states;

signal count : integer range 0 to 6 := 0;

signal tim: integer:= 0;

signal flip: std_logic:='0';

begin

process(clk)

begin


if ((flip= '0' and count = time1) or (flip='1' and count=tim))then


count <= 0;

else

count <= count+1;

end if;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(speed)

begin

case speed is

when "00" =>

tim <= time21;

when "01" =>

tim <= time22;

when "10" =>

tim <= time23;

when others =>

tim <= time24;

end case;

end process;

--------------------------------------------------------------------------------------------------------------------------------

PROCESS (pr_state, direction, stop)

begin

if(stop='1') then

nx_state <= pr_state;

else

case pr_state is

when a =>

dout <= "1000000"; -- Decimal 64

flip<='1';

if (direction='0') then

nx_state <= ab;

else


- 73 -

nx_state <= fa;

end if;

when ab =>

dout <= "1100000"; -- Decimal 96

flip<='0';


nx_state <= b;

else

nx_state <= a;

end if;

when b =>

dout <= "0100000"; -- Decimal 32

flip<='1';


nx_state <= bc;

else

nx_state <= ab;

end if;

when bc =>

dout <= "0110000"; -- Decimal 48

flip<='0';


nx_state <= c;

else

nx_state <= b;

end if;

when c =>

dout <= "0010000"; -- Decimal 16

flip<='1';


nx_state <= cd;

else

nx_state <= bc;

end if;

when cd =>

dout <= "0011000"; -- Decimal 24

flip<='0';


nx_state <= d;

else

nx_state <= c;

end if;

when d =>

dout <= "0001000"; -- Decimal 8

flip<='1';


nx_state <= de;


- 74 -

else

nx_state <= cd;

end if;

when de =>

dout <= "0001100"; -- Decimal 12

flip<='0';


nx_state <= e;

else

nx_state <= d;

end if;

when e =>

dout <= "0000100"; -- Decimal 4

flip<='1';


nx_state <= ef;

else

nx_state <= de;

end if;

when ef =>

dout <= "0000110"; -- Decimal 6

flip<='0';


nx_state <= f;

else

nx_state <= e;

end if;

when f =>

dout <= "0000010"; -- Decimal 2

flip<='1';


nx_state <= fa;

else

nx_state <= ef;

end if;

when fa =>

dout <= "1000010"; -- Decimal 66

flip<='0';


nx_state <= a;

else

nx_state <= f;

end if;

END CASE;

end if;

END PROCESS;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------


- 75 -

• Simulation

------------------------------------------------------------------------------------------------------------------------------------------

Problem 9.7

• Code

library IEEE;




entity p7 is

port(clk,rst,speed: in std_logic;

leds: out std_logic_vector (7 downto 0) := (others => '0');

data1,data2: out std_logic_vector (6 downto 0 ):= (others => '0');

speed_in: in std_logic;

buzzer: out std_logic := '0');

end p7;


type states is (start,thirty_five,forty_five, fifty_five, sixty, sixty_five, seventy, seventy_five,

eighty);

signal pr_speed, nx_speed : states;

signal inst_speed, limit_speed,limit_speed_tmp: integer range 0 to 99:= 0;

signal led_tmp: std_logic_vector (7 downto 0):= "00000000";

begin

process(clk, rst)

begin

if (rst='1') then

pr_speed <= thirty_five;


pr_speed <= nx_speed;

leds <= led_tmp;

limit_speed <= limit_speed_tmp;

end if;

end process;



- 76 -

process(pr_speed,speed)

begin

if (speed'event and speed = '1') then

case pr_speed is

when start =>

nx_speed <= thirty_five;

led_tmp <= "10000000";

limit_speed_tmp <=35;

when thirty_five =>

nx_speed <= forty_five;

led_tmp <= "01000000";


when forty_five=>

nx_speed <= fifty_five;

led_tmp <= "00100000";


when fifty_five =>

nx_speed <= sixty;

led_tmp <= "00010000";


when sixty =>

nx_speed <= sixty_five;

led_tmp <= "00001000";

limit_speed_tmp<=65;

when sixty_five =>

nx_speed <= seventy;

led_tmp <= "00000100";

limit_speed_tmp<=70;

when seventy =>

nx_speed <= seventy_five;

led_tmp <= "00000010";


when seventy_five =>

nx_speed <= eighty;

led_tmp <= "00000001";


when eighty =>

nx_speed <= thirty_five;

led_tmp <= "00000001";


end case;

end if;

end process;

process(speed_in,clk)

variable ten, unit: integer := 0;

variable counter: integer := 0;

variable check: std_logic := '0';


- 77 -

begin

if (speed_in = '1') then

counter := counter + 1;

else

if (counter/=0)then

inst_speed <= 3*counter;

counter := 3*counter;

if (counter >10) then

for i in 0 to 9 loop

counter := counter-10;

ten := ten+1;

if (counter <10)then

exit;

end if;

end loop;

else

ten := 0;

end if;

unit := counter;

counter:= 0;

case unit is

when 0 => data1 <= "1111110";

when 1 => data1 <= "0110000";

when 2 => data1 <= "1101101";

when 3 => data1 <= "1111001";

when 4 => data1 <= "0110011";

when 5 => data1 <= "1011011";

when 6 => data1 <= "1011111";

when 7 => data1 <= "1110000";

when 8 => data1 <= "1111111";

when 9 => data1 <= "1111011";

when others => null;

end case;

case ten is

when 0 => data2 <= "1111110";

when 1 => data2 <= "0110000";

when 2 => data2 <= "1101101";

when 3 => data2 <= "1111001";

when 4 => data2 <= "0110011";

when 5 => data2 <= "1011011";

when 6 => data2 <= "1011111";

when 7 => data2 <= "1110000";

when 8 => data2 <= "1111111";

when 9 => data2 <= "1111011";

when others => null;

end case;


- 78 -

ten := 0;

unit := 0;

end if;

end if;

end process;

process(inst_speed,limit_speed,clk)

variable counter: integer := 0;

begin

if (inst_speed >= limit_speed) then

buzzer <= '1';

elsif (inst_speed > (limit_speed-3)) then

if (counter < 4) then

counter := counter +1;

buzzer <= '1';

elsif (counter < 8)then

counter := counter +1;

buzzer <= '0';

else

counter := 0;

end if;

else

buzzer <= '0';

end if;

end process;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 79 -

Problem 9.8

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p8 is

port(clk,stop: in std_logic;


end p8;

--------------------------------------------------------------------------------------------------------------------------------


CONSTANT time1: INTEGER := 4; -- actual value is 80

CONSTANT time2: INTEGER := 2; -- actual value is 30

TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);

SIGNAL present_state, next_state: STATES;

SIGNAL count: INTEGER RANGE 0 TO 5;

SIGNAL flip: std_logic;

signal random: std_logic_vector (6 downto 0):="1110110";

signal pr_random, nx_random: std_logic_vector (3 downto 0):= "0001";

BEGIN

--------------------------------------------------------------------------------------------------------------------------------

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1' AND stop/='1') THEN

IF ((flip='1' AND count=time1) OR

(flip='0' AND count=time2)) THEN

count <= 0;

present_state <= next_state;

ELSE

count <= count + 1;

END IF;

END IF;

END PROCESS;

--------------------------------------------------------------------------------------------------------------------------------

PROCESS (present_state,stop)

BEGIN

if (stop='1') then

dout <= random;

next_state <= present_state;

else

CASE present_state IS

WHEN a =>

dout <= "1000000"; -- Decimal 64

flip<='1';

next_state <= ab;


- 80 -

WHEN ab =>

dout <= "1100000"; -- Decimal 96

flip<='0';

next_state <= b;

WHEN b =>

dout <= "0100000"; -- Decimal 32

flip<='1';

next_state <= bc;

WHEN bc =>

dout <= "0110000"; -- Decimal 48

flip<='0';

next_state <= c;

WHEN c =>

dout <= "0010000"; -- Decimal 16

flip<='1';

next_state <= cd;

WHEN cd =>

dout <= "0011000"; -- Decimal 24

flip<='0';

next_state <= d;

WHEN d =>

dout <= "0001000"; -- Decimal 8

flip<='1';

next_state <= de;

WHEN de =>

dout <= "0001100"; -- Decimal 12

flip<='0';

next_state <= e;

WHEN e =>

dout <= "0000100"; -- Decimal 4

flip<='1';

next_state <= ef;

WHEN ef =>

dout <= "0000110"; -- Decimal 6

flip<='0';

next_state <= f;

WHEN f =>

dout <= "0000010"; -- Decimal 2


- 81 -

flip<='1';

next_state <= fa;

WHEN fa =>

dout <= "1000010"; -- Decimal 66

flip<='0';

next_state <= a;

END CASE;

end if;

END PROCESS;

--------------------------------------------------------------------------------------------------------------------------------

process(stop)

begin

if (stop'event and stop='1') then

pr_random <= nx_random;

case pr_random is

when "0000" => random <= "1111110";

when "0001" => random <= "0110000";

when "0010" => random <= "1101101";

when "0011" => random <= "1111001";

when "0100" => random <= "0110011";

when "0101" => random <= "1011011";

when "0110" => random <= "1011111";

when "0111" => random <= "1110000";

when "1000" => random <= "1111111";

when "1001" => random <= "1111011";

when "1010" => random <= "1110110";

when "1011" => random <= "1001101";

when "1100" => random <= "1001100";

when "1101" => random <= "1001111";

when "1110" => random <= "1001101";

when "1111" => random <= "1000111";

when others => NULL;

end case;

end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------

process(pr_random)

variable fb: std_logic:= '0';

begin

fb := pr_random(0) xor pr_random(1);

nx_random <= fb & pr_random(3 downto 1);

end process;

end Behavioral;


- 82 -

• Simulation



- 83 -

Chapter 10:”Packages and Components”

Problem 10.1------------------------------------------------------------------------------ 85

Problem 10.2------------------------------------------------------------------------------ 87

Problem 10.3------------------------------------------------------------------------------ 88

Problem 10.4----------------------------------------------------------------------------- 90


- 84 -

Chapter 10

Library work.my_components is used throughout this chapter.

----------------------------------------------------------Package my_components-----------------------------------------------

library IEEE;


package my_components is

component arith_unit is



cin: in std_logic;

x: out std_logic_vector (7 downto 0));

end component;

------------------------------------------------------------------------------------------------------------------------------------------

component logic_unit is




end component;

------------------------------------------------------------------------------------------------------------------------------------------

component mux is

port (x1,x2: in std_logic_vector (7 downto 0);

sel: in std_logic;


end component;

------------------------------------------------------------------------------------------------------------------------------------------

component CLA_adder is


cin: in std_logic;



end component;

---------------------------------------------------------------------------------------------------------------------------------------

component PGU is


p,g: out std_logic_vector (3 downto 0));

end component;

--------------------------------------------------------------------------------------------------------------------------------------

component CLAU is

port (p: in std_logic_vector (3 downto 0);

g: in std_logic_vector (3 downto 0);

cin: in std_logic;


cout : out std_logic);

end component;

--------------------------------------------------------------------------------------------------------------------------------------


- 85 -

component FAU is

port (a, b, cin: in std_logic;

s, cout: out std_logic);

end component;

-----------------------------------------------------------------------------------------------------------------------------------------

component and_2 is

port(a,b: in std_logic;

r: out std_logic);

end component;

-----------------------------------------------------------------------------------------------------------------------------------------

end my_components;

----------------------------------------------------------------------------------------------------------------------------------------

Problem 10.1

• Code

------------------------------------arith_unit-------------------------------------------------------------------------------

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity arith_unit is



cin: in std_logic;


end arith_unit;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of arith_unit is

begin

with sel select

x <= a when "000",

b when "001",

a+1 when "010",

b+1 when "011",

a-1 when "100",

b-1 when "101",

a+b when "110",

a+b+cin when others;

end Behavioral;

------------------------------------logic_unit-------------------------------------------------------------------------------

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity logic_unit is




- 86 -


end logic_unit;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of logic_unit is

begin

with sel select

x <= not(a) when "000",

not(b) when "001",

a and b when "010",

a or b when "011",

a nand b when "100",

a nor b when "101",

a xor b when "110",

not (a xor b) when others;

end Behavioral;

------------------------------------mux--------------------------------------------------------------------------------------

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity mux is

port (x1,x2: in std_logic_vector (7 downto 0);

sel: in std_logic;


end mux;

--------------------------------------------------------------------------------------------------------------------------------

architecture Behavioral of mux is

begin

with sel select

y <= x1 when '0',

x2 when others;

end Behavioral;

-----------------------------------Main Code------------------------------------------------------------------------------

library IEEE;




use work.my_components.ALL;

--------------------------------------------------------------------------------------------------------------------------------

entity p1 is



cin: in std_logic;


end p1;

--------------------------------------------------------------------------------------------------------------------------------


- 87 -


signal x1,x2: std_logic_vector (7 downto 0):= (others => '0');

begin

U1: arith_unit port map(a,b,sel(2 downto 0),cin,x1);

U2: logic_unit port map(a,b,sel(2 downto 0),x2);

U3: mux port map(x1,x2,sel(3),y);

end Behavioral;

• Simulation

Problem 10.2

• Code

-----------------------------------------------FAU-----------------------------------------------------------------------

library IEEE;




entity FAU is



end FAU;

architecture Behavioral of FAU is

begin

s <= a xor b xor cin;

cout <= (a and b) or (b and cin) or (a and cin);

end Behavioral;

--------------------------------------Main Code----------------------------------------------------------------------

library IEEE;




use work.my_components.all;

--------------------------------------------------------------------------------------------------------------------------------

entity p3 is

port (a,b: in std_logic_vector (3 downto 0);

cin: in std_logic;



end p3;



- 88 -


signal tmp: std_logic_vector (4 downto 0) := "00000";

begin

tmp(0) <= cin;

G1: for i in a'range generate

U1: FAU port map(a(i),b(i),tmp(i),s(i),tmp(i+1));

end generate;

cout <= tmp(tmp'high);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

`

Problem 10.3

• Code

--------------------------------------------PGU-----------------------------------------------------------------------------

library IEEE;




entity PGU is


p,g: out std_logic_vector (3 downto 0));

end PGU;

architecture Behavioral of PGU is

begin

G1: for i in a'range generate

p(i) <= a(i) xor b(i);

g(i) <= a(i) and b(i);

end generate;

end Behavioral;

--------------------------------------------CLAU---------------------------------------------------------------------------

library IEEE;




entity CLAU is

port (p: in std_logic_vector (3 downto 0);

g: in std_logic_vector (3 downto 0);

cin: in std_logic;



- 89 -


cout : out std_logic);

end CLAU;

architecture Behavioral of CLAU is

signal c: std_logic_vector (4 downto 0);

begin

G1:for i in p'range generate

s(i)<= p(i) xor c(i);

end generate;

c(0) <= cin;

c(1) <= (cin AND p(0)) OR g(0);

c(2) <= (cin AND p(0) AND p(1)) OR (g(0) AND p(1)) OR g(1);

c(3) <= (cin AND p(0) AND p(1) AND p(2)) OR(g(0) AND p(1) AND p(2)) OR(g(1) AND p(2)) OR g(2);

c(4) <= (cin AND p(0) AND p(1) AND p(2) AND p(3)) OR (g(0) AND p(1) AND p(2) AND p(3)) OR

(g(1) AND p(2) AND p(3)) OR (g(2) AND p(3)) OR g(3);

cout <= c(4);

end Behavioral;

-----------------------------Main Code------------------------------------------------------------------------------------

library IEEE;





--------------------------------------------------------------------------------------------------------------------------------

entity p2b is

port (a,b: in std_logic_vector (3 downto 0);

cin: in std_logic;



end p2b;

--------------------------------------------------------------------------------------------------------------------------------


signal p,g: std_logic_vector (3 downto 0) := "0000";

begin

U1: PGU port map (a,b,p,g);

U2: CLAU port map (p,g,cin,s,cout);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 90 -

Problem 10.4

• Code

------------------------------------------------counter-------------------------------------------------------------------

library IEEE;




entity counter is


outp: out std_logic_vector (3 downto 0):= "0000");

end counter;

architecture Behavioral of counter is

begin

process(clk,rst)

variable reg: std_logic_vector (3 downto 0) := "0000";

begin

if (rst = '1') then

reg:= "0000";


reg:= reg + 1;

end if;

outp <= reg;

end process;

end Behavioral;

------------------------------------------------reg-------------------------------------------------------------------------

library IEEE;




entity reg is

port( store : in std_logic;

inp: in std_logic_vector (3 downto 0);

outp: out std_logic_vector (3 downto 0) := "0000");

end reg;

architecture Behavioral of reg is

begin

process (store)

begin

if (store'event and store='1') then

outp <= inp;


- 91 -

end if;

end process;

end Behavioral;

--------------------------------------------------Main Code-------------------------------------------------------------

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

port (clk,stop: in std_logic;


end p4;

--------------------------------------------------------------------------------------------------------------------------------


component counter is



end component;

component reg is

port(store : in std_logic;

inp: in std_logic_vector (3 downto 0);


end component;

signal tmp: std_logic_vector (3 downto 0) := "0000";

begin

U1: counter port map(clk,stop,tmp);

U2: reg port map(stop, tmp,outp);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 92 -

Chapter 11: “Functions and procedures:

Problem11.1 --------------------------------------------------------------------------------------- 98

Problem11.2--------------------------------------------------------------------------------------- 98

Problem11.3---------------------------------------------------------------------------------------- 100

Problem11.4----------------------------------------------------------------------------------------- 101

Problem11.5---------------------------------------------------------------------------------------- 102

Problem11.6----------------------------------------------------------------------------------------- 105

Problem11.7---------------------------------------------------------------------------------------- 106

Problem11.8---------------------------------------------------------------------------------------- 109


- 93 -

All functions required within this chapter were written in package my_functions

-----------------------------------------------my_functions---------------------------------------------------------------

library IEEE;



--------------------------------------------------------------------------------------------------------------------------------

package my_functions is

constant limit: integer := 255;

function conv_std_logic (arg :integer; size: integer) return std_logic_vector;

function conv_int (signal vector: std_logic_vector) return integer;

function logic_shift(signal vector: std_logic_vector; shift: integer) return std_logic_vector;

function shift_int (signal i1: integer; signal shift: integer; size: integer) return integer;

function mult_signed(signal i1,i2: signed) return signed;

function bcd_to_ssd(signal i1: integer) return std_logic_vector;

procedure stat(signal i1,i2,i3,i4,i5,i6,i7,i8: in integer range 0 to limit; signal min, max: out integer

range 0 to limit;signal ave: out std_logic_vector(7

downto 0));

function "+"(signal a,b: std_logic_vector) return std_logic_vector;

end my_functions;

--------------------------------------------------------------------------------------------------------------------------------

package body my_functions is

------------------------------------------------------------------------------------------------------------

function conv_std_logic (arg :integer; size: integer) return std_logic_vector is

variable tmp: integer range 0 to 2**size-1;

variable result: std_logic_vector (size-1 downto 0);

begin

tmp := arg;

for i in result'range loop

if (tmp >= 2**i) then

result(i):= '1';

tmp := tmp-2**i;

else

result(i) := '0';

end if;

end loop;

return result;

end conv_std_logic;

------------------------------------------------------------------------------------------------------------

function conv_int (SIGNAL vector: STD_LOGIC_VECTOR) return integer is

variable result: integer RANGE 0 TO 2**vector'LENGTH-1;

begin

if (vector(vector'HIGH)='1') THEN


- 94 -

result:=1;

else

result:=0;

end if;

for i in (vector'HIGH-1) downto (vector'LOW) LOOP

result:=result*2;

if(vector(i)='1') then

result:=result+1;

end if;

end loop;

return result;

end conv_int;

------------------------------------------------------------------------------------------------------------

function logic_shift(signal vector: std_logic_vector; shift: integer) return std_logic_vector is

variable tmp: std_logic_vector (vector'high downto 0);

begin

tmp:= vector;

for i in 1 to vector'high loop

if (i <= shift) then

tmp := tmp(tmp'high-1 downto 0) & '0' ;

else

exit;

end if;

end loop;

return tmp;

end logic_shift;

------------------------------------------------------------------------------------------------------------

function shift_int (signal i1: integer; signal shift: integer; size: integer) return integer is

variable tmp,result: integer range 0 to 2**size-1;

variable vector: std_logic_vector (size-1 downto 0);

begin

tmp := i1;

for i in vector'range loop


vector(i):= '1';

tmp := tmp-2**i;

else

vector(i) := '0';

end if;

end loop;



- 95 -


vector := vector(vector'high-1 downto 0) & '0' ;

else

exit;

end if;

end loop;


result:=1;

else

result:=0;

end if;


result:=result*2;


result:=result+1;

end if;

end loop;

return result;

end shift_int;

------------------------------------------------------------------------------------------------------------

function mult_signed(signal i1,i2: signed) return signed is

constant max : integer := i1'length+i2'length-1;

variable tmp: signed (max downto 0) := (max downto i1'length => '0') & i1(i1'length-1 downto 0);

variable prod: signed (max downto 0) := (others => '0');

begin

for i in 0 to i1'high loop

if (i2(i) = '1') then

prod:= prod+tmp;

tmp := tmp(max-1 downto 0)&'0';

end if;

end loop;

return prod;

end mult_signed;

------------------------------------------------------------------------------------------------------------

function bcd_to_ssd(signal i1: integer) return std_logic_vector is

variable tmp: std_logic_vector(6 downto 0);

begin

case i1 is

when 0 => tmp := "1111110";

when 1 => tmp := "0110000";

when 2 => tmp := "1101101";


- 96 -

when 3 => tmp := "1111001";

when 4 => tmp := "0110011";

when 5 => tmp := "1011011";

when 6 => tmp := "1011111";

when 7 => tmp := "1110000";

when 8 => tmp := "1111111";

when 9 => tmp := "1111011";


end case;

return tmp;

end bcd_to_ssd;

------------------------------------------------------------------------------------------------------------


range 0 to limit; signal ave: out std_logic_vector (7 downto 0))is

variable tmp1,tmp2,tmp3: integer range 0 to limit;

begin

tmp1 := i1;

tmp2 := i1;

if(tmp1 < i2) then

tmp1 := i2;

end if;

if(tmp1<i3) then

tmp1:=i3;

end if;

if(tmp1<i4)then

tmp1:=i4;

end if;

if(tmp1<i5)then

tmp1:=i5;

end if;

if(tmp1<i6)then

tmp1:=i6;

end if;

if(tmp1<i7)then

tmp1:=i7;

end if;

if(tmp1<i8)then

tmp1 := i8;

end if;

if(tmp2 > i2) then

tmp2 := i2;


- 97 -

end if;

if(tmp2>i3) then

tmp2:=i3;

end if;

if(tmp2>i4)then

tmp2:=i4;

end if;

if(tmp2>i5)then

tmp1:=i5;

end if;

if(tmp2>i6)then

tmp2:=i6;

end if;

if(tmp2>i7)then

tmp2:=i7;

end if;

if(tmp2>i8)then

tmp2:= i8;

end if;

tmp3:= i1+i2+i3+i4+i5+i6+i7+i8;

for i in 7 downto 0 loop

if(tmp3 > 8*2**i)then

ave(i) <= '1';

tmp3 := tmp3-8*2**i;

else

ave(i) <= '0';

end if;

end loop;

min <= tmp1;

max <= tmp2;

end stat;

------------------------------------------------------------------------------------------------------------

function "+"(signal a,b: std_logic_vector) return std_logic_vector is

variable tmp : std_logic_vector(a'high+1 downto 0);

variable c: std_logic_vector(a'high+1 downto 0);

begin

c(0) := '0';

for i in a'reverse_range loop

tmp(i) := a(i)xor b(i)xor c(i);

c(i+1) := (a(i) and b(i))or(c(i) and b(i))or(a(i) and c(i));

end loop;


- 98 -

tmp(a'high+1) := c(a'high+1);

return tmp;

end "+";

end my_functions;

--------------------------------------------------------------------------------------------------------------------------------

Problem 11.1

• Code

library IEEE;




use work.my_functions.ALL;

entity p1 is

port(d_in: in integer range 0 to 15;

d_out: out std_logic_vector (3 downto 0));

end p1;


begin

d_out <= conv_std_logic(d_in,4);

end Behavioral;

• Simulation

Problem 11.2

• Code

-----------------------------------------not_int function-----------------------------------------------------------------

function not_int(signal i1:integer; size: integer) return integer is

variable tmp: integer range 0 to 2**size-1;

variable result: std_logic_vector (size-1 downto 0);

variable r : integer;

begin

tmp := i1;

for i in result'range loop

Figure 11.1 Simulation results for Problem 11.1


- 99 -


result(i):= '1';

tmp := tmp-2**i;

else

result(i) := '0';

end if;

end loop;

result := not(result);

if (result(result'HIGH)='1') THEN

r:=1;

else

r:=0;

end if;

for i in (result'HIGH-1) downto (result'LOW) LOOP

r:=r*2;

if(result(i)='1') then

r:=r+1;

end if;

end loop;

return r;

end not_int;

---------------------------------------------------Main code--------------------------------------------------------------

library IEEE;





--------------------------------------------------------------------------------------------------------------------------------

entity p2 is

port (inp:in integer range 0 to 15;

outp:out integer range 0 to 15);

end p2;

--------------------------------------------------------------------------------------------------------------------------------


constant size: integer := 4;

begin

outp <= not_int(inp,size);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------


- 100 -

• Simulation

Problem 11.3

• Code

--------------------------------logic_shift function--------------------------------------------------------------------

function logic_shift(signal vector: std_logic_vector; shift: integer) return std_logic_vector is

variable tmp: std_logic_vector (vector'high downto 0);

begin

tmp:= vector;



tmp := tmp(tmp'high-1 downto 0) & '0' ;

else

exit;

end if;

end loop;

return tmp;

end logic_shift;

----------------------------------------------Main Code-------------------------------------------------------------------

library IEEE;





--------------------------------------------------------------------------------------------------------------------------------

entity p3 is

port (inp: in std_logic_vector (3 downto 0);

outp: out std_logic_vector (3 downto 0);

shift: in integer range 0 to 4);

end p3;

--------------------------------------------------------------------------------------------------------------------------------


begin

outp <= logic_shift(inp,shift);

end Behavioral;



- 101 -

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 11.4

• Code

------------------------------------------------------------shift_int---------------------------------------------------------

function shift_int (signal i1: integer; signal shift: integer; size: integer) return integer is

variable tmp,result: integer range 0 to 2**size-1;

variable vector: std_logic_vector (size-1 downto 0);

begin

tmp := i1;

for i in vector'range loop


vector(i):= '1';

tmp := tmp-2**i;

else

vector(i) := '0';

end if;

end loop;



vector := vector(vector'high-1 downto 0) & '0' ;

else

exit;

end if;

end loop;


result:=1;

else

result:=0;

end if;


result:=result*2;




- 102 -

result:=result+1;

end if;

end loop;

return result;

end shift_int;

------------------------------------------------------------Main Code-----------------------------------------------------

library IEEE;




use work.my_functions.all;

--------------------------------------------------------------------------------------------------------------------------------

entity p4 is

Generic (n: integer :=4);

port(inp: in integer range 0 to 15;

outp: out integer range 0 to 15;

shift: in integer range 0 to 4);

end p4;

--------------------------------------------------------------------------------------------------------------------------------


begin

outp <= shift_int(inp, shift,n);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation

Problem 11.5

• Code

----------------------------------------------mult_signed-----------------------------------------------------------------

library IEEE;




package my_functions is



- 103 -

function mult_signed (signal a,b : in signed) return signed;

end my_functions;

package body my_functions is

function mult_signed (signal a,b : in signed) return signed is

constant max: integer := 4;

variable a1: unsigned (2 downto 0);

variable b1: unsigned (2 downto 0);

variable aa : unsigned (4 downto 0);

variable prod: unsigned (4 downto 0);

variable result : signed (5 downto 0);

begin

if(a(a'high)='1') then

for i in a1'range loop

if (a(i)='1') then

a1(i) := '0';

else

a1(i) := '1';

end if;

end loop;

a1 := a1+1;

else

a1 := conv_unsigned(a(a1'high downto 0),a'high);

end if;

if(b(b'high)='1') then

for i in b1'range loop

if (b(i)='1') then

b1(i) := '0';

else

b1(i) := '1';

end if;

end loop;

b1 := b1+1;

else

b1 := conv_unsigned(b(b1'high downto 0),b'high);

end if;

prod:=(others =>'0');

aa :=(max DOWNTO a1'LENGTH => '0')& a1(a1'LENGTH-1 DOWNTO 0);

for i in 0 to a1'LENGTH-1 loop

if (b1(i)='1') then prod := prod + aa;

end if;

aa := aa(max-1 downto 0) & '0';

end loop;


- 104 -

if(a(a'high)= b(b'high)) then

prod(prod'high) := '0';

else

prod(prod'high) := '1';

end if;

if (prod(prod'high)= '1') then

for i in prod'high-1 downto 0 loop

if (prod(i)='1') then

prod(i) := '0';

else

prod(i) := '1';

end if;

end loop;

prod := prod+1;

end if;

result := conv_signed(prod,6);

return result;

end mult_signed;

end my_functions;

--------------------------------------------------Main Code---------------------------------------------------------------

library IEEE;





--------------------------------------------------------------------------------------------------------------------------------

entity p115 is

port(a,b: in signed (3 downto 0);

prod: out signed (5 downto 0));

end p115;

--------------------------------------------------------------------------------------------------------------------------------


begin

prod <= mult_signed(a,b);

end Behavioral;

• Simulation



- 105 -

Problem 11.6

• Code

----------------------------------------------bcd_to_ssd------------------------------------------------------------------

function bcd_to_ssd(signal i1: integer) return std_logic_vector is

variable tmp: std_logic_vector(6 downto 0);

begin

case i1 is

when 0 => tmp := "1111110";

when 1 => tmp := "0110000";

when 2 => tmp := "1101101";

when 3 => tmp := "1111001";

when 4 => tmp := "0110011";

when 5 => tmp := "1011011";

when 6 => tmp := "1011111";

when 7 => tmp := "1110000";

when 8 => tmp := "1111111";

when 9 => tmp := "1111011";


end case;

return tmp;

end bcd_to_ssd;

-----------------------------------------------Main Code------------------------------------------------------------------

library IEEE;




use work.my_functions.All;

--------------------------------------------------------------------------------------------------------------------------------

entity p6 is


digit1,digit2: out std_logic_vector(6 downto 0):="0000000");

end p6;

--------------------------------------------------------------------------------------------------------------------------------


signal s1,s2 : integer range 0 to 9 := 0;

begin

process(clk,rst)

variable tmp1, tmp2 : integer range 0 to 10 := 0;

begin

if(rst='1') then

tmp1:= 0;


- 106 -

tmp2:= 0;


tmp1:= tmp1+1;

if (tmp1 = 10) then

tmp1 := 0;

tmp2 := tmp2 +1;

if (tmp2 = 10) then

tmp2:= 0;

end if;

end if;

end if;

s1<= tmp1;

s2<= tmp2;

digit1 <= bcd_to_ssd(s1);

digit2 <= bcd_to_ssd(s2);

end process;

end Behavioral;

• Simulation

Problem 11.7

• Code

-------------------------------------------Procedure Stat-----------------------------------------------------------------


range 0 to limit; signal ave: out std_logic_vector (7

downto 0))is

variable tmp1,tmp2,tmp3: integer range 0 to limit;

begin

tmp1 := i1;

tmp2 := i1;

if(tmp1 < i2) then

tmp1 := i2;

end if;

if(tmp1<i3) then



- 107 -

tmp1:=i3;

end if;

if(tmp1<i4)then

tmp1:=i4;

end if;

if(tmp1<i5)then

tmp1:=i5;

end if;

if(tmp1<i6)then

tmp1:=i6;

end if;

if(tmp1<i7)then

tmp1:=i7;

end if;

if(tmp1<i8)then

tmp1 := i8;

end if;

if(tmp2 > i2) then

tmp2 := i2;

end if;

if(tmp2>i3) then

tmp2:=i3;

end if;

if(tmp2>i4)then

tmp2:=i4;

end if;

if(tmp2>i5)then

tmp1:=i5;

end if;

if(tmp2>i6)then

tmp2:=i6;

end if;

if(tmp2>i7)then

tmp2:=i7;

end if;

if(tmp2>i8)then

tmp2:= i8;

end if;

tmp3:= i1+i2+i3+i4+i5+i6+i7+i8;

for i in 7 downto 0 loop


- 108 -

if(tmp3 > 8*2**i)then

ave(i) <= '1';

tmp3 := tmp3-8*2**i;

else

ave(i) <= '0';

end if;

end loop;

min <= tmp1;

max <= tmp2;

end stat;

-----------------------------------------Main Code------------------------------------------------------------------------

library IEEE;





--------------------------------------------------------------------------------------------------------------------------------

entity p7 is

port(i1,i2,i3,i4,i5,i6,i7,i8: in integer range 0 to 255;

max,min,ave: out integer range 0 to 255);

end p7;

--------------------------------------------------------------------------------------------------------------------------------


signal av: std_logic_vector(7 downto 0) := (others =>'0');

begin

stat(i1,i2,i3,i4,i5,i6,i7,i8,max,min,av);

ave<= conv_int(av);

end Behavioral;

• Simulation



- 109 -

Problem 11.8

• Code

--------------------------------------------“+”-----------------------------------------------------------------------------

function "+"(signal a,b: std_logic_vector) return std_logic_vector is

variable tmp : std_logic_vector(a'high+1 downto 0);

variable c: std_logic_vector(a'high+1 downto 0);

begin

c(0) := '0';

for i in a'reverse_range loop

tmp(i) := a(i)xor b(i)xor c(i);

c(i+1) := (a(i) and b(i))or(c(i) and b(i))or(a(i) and c(i));

end loop;

tmp(a'high+1) := c(a'high+1);

return tmp;

end "+";

---------------------------------------------Main Code--------------------------------------------------------------------

library IEEE;



--------------------------------------------------------------------------------------------------------------------------------

entity p8 is


result: out std_logic_vector (7 downto 0);


end p8;

--------------------------------------------------------------------------------------------------------------------------------


signal tmp: std_logic_vector (8 downto 0);

begin

tmp <= a+b;

result <= tmp(result'high downto 0);

cout <= tmp(tmp'high);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 110 -

Chapter 12: “Additional System Designs”

Problem 12.1 ----------------------------------------------------------------- 112

Problem 12.2 ----------------------------------------------------------------- 115

Problem 12.3------------------------------------------------------------------ 119

Problem 12.4------------------------------------------------------------------ 121

Problem 12.5------------------------------------------------------------------- 123


- 111 -

Problem12.1

• Code

--------------------------------------------------------and_2---------------------------------------------------------------

library IEEE;




entity and_2 is

port(a,b: in std_logic;

r: out std_logic);

end and_2;

architecture Behavioral of and_2 is

begin

r <= (a and b);

end Behavioral;

--------------------------------------------------------FAU------------------------------------------------------------------

library IEEE;




entity FAU is



end FAU;

architecture Behavioral of FAU is

begin

s <= a xor b xor cin;

cout <= (a and b) or (b and cin) or (a and cin);

end Behavioral;

------------------------------------------------top_row--------------------------------------------------------------------

library IEEE;





entity top_row is

port( a: in std_logic;

b: in std_logic_vector (3 downto 0);

s,cout: out std_logic_vector (2 downto 0);

p: out std_logic);

end top_row;


- 112 -

architecture Behavioral of top_row is

begin

U1: and_2 port map (a,b(3),s(2));



U4: and_2 port map (a,b(0),p);

cout <= (others => '0');

end Behavioral;

-------------------------------------------------mid_row-------------------------------------------------------------------

library IEEE;





entity mid_row is

port(a: in std_logic;

b: in std_logic_vector (3 downto 0);

sin, cin: in std_logic_vector (2 downto 0);

sout,cout: out std_logic_vector (2 downto 0);

p: out std_logic);

end mid_row;

architecture Behavioral of mid_row is

signal and_out: std_logic_vector (2 downto 0);

begin

U1: and_2 port map(a,b(3),sout(2));

U2: and_2 port map(a,b(2),and_out(2));



U5: FAU port map(sin(2),and_out(2),cin(2),sout(1), cout(2));

U6: FAU port map(sin(1),and_out(1),cin(1),sout(0), cout(1));

U7: FAU port map(sin(0),and_out(0),cin(0), p , cout(0));

end Behavioral;

------------------------------------------Last_row--------------------------------------------------------------------------

library IEEE;





entity last_row is

port(sin,cin: in std_logic_vector (2 downto 0);


- 113 -

p: out std_logic_vector (3 downto 0));

end last_row;

architecture Behavioral of last_row is

signal local: std_logic_vector (3 downto 0);

begin

local(0) <= '0';

U1: FAU port map(sin(0),cin(0),local(0),p(0),local(1));

U2: FAU port map(sin(1),cin(1),local(1),p(1),local(2));

U3: FAU port map(sin(1),cin(1),local(2),p(2),p(3));

end Behavioral;

-------------------------------------------Main Code----------------------------------------------------------------------

library IEEE;





entity p1 is


p: out std_logic_vector (8 downto 0));

end p1;


type matrix is array (0 to 3) of std_logic_vector (2 downto 0);

signal s, c: matrix;

begin

U1: component top_row port map (a(0), b, s(0), c(0), p(0));

U2: component mid_row port map (a(1), b, s(0), c(0), s(1),c(1), p(1));



U5: component last_row PORT MAP (s(3), c(3),p(7 DOWNTO 4));

end Behavioral;

-------------------------------------------------------------------------------------------------------------------------------

• Simulation



- 114 -

Problem 12.2

• Code a

----------------------------------ff8------------------------------------------------------------------------------------------

library IEEE;




entity ff8 is

Generic(n: integer := 7);


din: in std_logic_vector (7 downto 0);


end ff8;

architecture Behavioral of ff8 is

begin

process(clk,rst)

begin

if (rst='1') then

dout<= (others => '0');


dout <= din;

end if;

end process;

end Behavioral;

------------------------------------------------mux4------------------------------------------------------------------------

library IEEE;




entity mux4 is

port(a,b,c,d: in std_logic_vector(7 downto 0);



end mux4;

architecture Behavioral of mux4 is

begin

with sel select

y<= a when "00",

b when "01",

c when "10",

d when "11",


- 115 -

"00000000" when others;

end Behavioral;

----------------------------------------------------Main code (a)----------------------------------------------------

entity p2 is

port( clk,rst: in std_logic;

a: in std_logic_vector (7 downto 0);


y: out std_logic_vector (7 downto 0):= "00000000");

end p2;


Type matrix is array (0 to 3) of std_logic_vector(7 downto 0);

signal q: matrix := ((others => '0'),(others => '0'),(others => '0'),(others => '0'));

begin

U1: ff8 port map(clk,rst,a,q(0));

U2: ff8 port map(clk,rst,q(0),q(1));



U5: mux4 port map(q(0),q(1),q(2),q(3),sel,y);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Simulation a

• Code b

------------------------------------------Main Code (b)-------------------------------------------------------------------

library IEEE;



Figure 12.2 Simulation results for Problem 12.2a


- 116 -



entity p2b is

port( clk,rst: in std_logic;

a: in std_logic_vector (7 downto 0);

y1,y2,y3,y4: out std_logic_vector (7 downto 0));

end p2b;


Type matrix is array (0 to 3) of std_logic_vector(7 downto 0);

signal q: matrix := ((others => '0'),(others => '0'),(others => '0'),(others => '0'));

begin

U1: ff8 port map(clk,rst,a,q(0));




y1<= q(0);

y2<= q(1);

y3<= q(2);

y4<= q(3);

end Behavioral;

• `Simulation b

Code c

---------------------------------------------Main Code--------------------------------------------------------------------

library IEEE;





Figure 12.3 Simulation results for Problem 12.2b


- 117 -

entity p2c is



d_in: in std_logic_vector (b downto 0);

dout: out matrix1 (n-1 downto 0));

end p2c;

architecture Behavioral of p2c is

signal tmp: matrix1 (n downto 0);

begin

tmp(0) <= d_in;

G1:for i in dout'reverse_range generate

Ui:component ff8 port map(clk,rst,tmp(i),tmp(i+1));

end generate;

dout <= tmp(n downto 1);

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

• Code d

--------------------------------------------ff8b------------------------------------------------------------------------------

library IEEE;




entity ff8b is


port(clk,rst,load: in std_logic;

din: in std_logic_vector (7 downto 0);

x: in std_logic_vector (7 downto 0);


end ff8b;

architecture Behavioral of ff8b is

begin

process(clk,rst,load)

begin

if (rst='1') then

dout<= (others => '0');

elsif(load='1') then

dout <= x;


dout <= din;

end if;

end process;

end Behavioral;


- 118 -

-------------------------------------------Main Code----------------------------------------------------------------------

library IEEE;





entity p2d is


port(clk,rst,load: in std_logic;

d_in: in std_logic_vector (b downto 0);

x: in matrix1 (n-1 downto 0);

dout: out matrix1 (n-1 downto 0));

end p2d;

architecture Behavioral of p2d is

signal tmp: matrix1 (n downto 0);

begin

tmp(0) <= d_in;

G1:for i in dout'reverse_range generate

Ui:component ff8b port map(clk,rst,load,x(i),tmp(i),tmp(i+1));

end generate;

end Behavioral;

--------------------------------------------------------------------------------------------------------------------------------

Problem 12.3

• Code

----------------------------------------------mult----------------------------------------------------------------------------

library IEEE;



use IEEE.STD_LOGIC_SIGNED.ALL;

entity mult is


prod: out signed (31 downto 0));

end mult;

architecture Behavioral of mult is

begin

prod <= a*b;

end Behavioral;

----------------------------------------------faur----------------------------------------------------------------------------

library IEEE;



- 119 -



entity faur is



sum: out signed (31 downto 0);

overflow: out std_logic);

end faur;

architecture Behavioral of faur is

signal longs: signed (31 downto 0) := (others => '0');

begin

longs <= a+b;

sum <= longs(31 downto 0);

overflow <= '1' when (a(a'high) = b(b'high) and longs(longs'high)/= b(b'high)) else

'0';

end Behavioral;

-------------------------------------------------Main Code----------------------------------------------------------------

library IEEE;





entity p123 is


overflow: out std_logic;

clk: in std_logic;

y: out signed (31 downto 0) := (others =>'0'));

end p123;


signal tmp,acc,tmp1 : signed(31 downto 0) := (others =>'0');

begin

U1: mult port map(a,b,tmp);

U2: faur port map(acc,tmp,tmp1,overflow);

process(clk)

begin


y <= tmp1;

acc <= tmp1;

end if;

end process;

end Behavioral;


- 120 -

• Simulation

Problem 12.4

• Code

library IEEE;




entity p4 is

generic(n: integer := 4;

m: integer := 4);

port(x_input: in signed (n-1 downto 0);

coeff: in signed (n-1 downto 0);

clk,rst: in std_logic;

load,run: in std_logic;

y: out signed (2*n-1 downto 0);

overflow: out std_logic);

end p4;


Type internal_array is array (1 to m) of signed(n-1 downto 0);

signal coeff_m,xinput_m: internal_array;

begin

process(clk,rst)

variable prod, acc: signed (2*n-1 downto 0);

variable sign_prod, sign_acc : std_logic;

begin

if (rst='1') then

for i in 1 to m loop

xinput_m(i) <= (others => '0');

end loop;


if (load='1') then

coeff_m <= (coeff & coeff_m(1 to m-1));

end if;



- 121 -

if (run='1') then

xinput_m <= (x_input & xinput_m(1 to m-1));

end if;

end if;

acc:= (others => '0');

for i in coeff_m'range loop

prod := coeff_m(i)*xinput_m(i);

sign_prod:= prod(2*n-1);

sign_acc := acc(2*n-1);

acc := acc + prod;

if (sign_prod= sign_acc and acc(2*n-1) /= sign_prod) then

overflow <= '1';

else

overflow <= '0';

end if;

end loop;


y <= acc;

end if;

end process;

end Behavioral;

• Simulation



- 122 -

Problem 12.5

• Code

library IEEE;




entity p5b is


w_load,x_load: in std_logic;

x1,x2,x3: in signed (3 downto 0);

w1_in: in signed (3 downto 0);



y1: out signed (7 downto 0) := (others => '0');



overflow: out std_logic :='0');

end p5b;


type internal_array is array (1 to 3) of signed(3 downto 0);

signal w1,w2,w3,xin: internal_array;

begin

process(clk,x_load,rst)

begin


if(rst='1') then

for i in xin'range loop

xin(i) <= (others => '0');

end loop;

elsif(x_load='1') then

xin(1) <= x1;

xin(2) <= x2;

xin(3) <= x3;

else

xin <= (xin(3) & xin(1 to 2));

end if;

end if;

end process;

process (clk,w_load)

begin



- 123 -

if(w_load='1') then

w1 <= (w1_in & w1(1 to 2));

w2 <= (w2_in & w2(1 to 2));

w3 <= (w3_in & w3(1 to 2));

else

w1 <= (w1(2 to 3) & w1(1));

w2 <= (w2(2 to 3) & w2(1));

w3 <= (w3(2 to 3) & w3(1));

end if;

end if;

end process;

process(clk,rst)

variable count: integer range 0 to 4;

variable prod1,acc1,prod2,acc2,prod3,acc3: signed(7 downto 0);

variable sign1,sign2,sign3: std_logic :='0';

begin

if(rst='1') then

acc1 := (others => '0');

acc2 := (others => '0');

acc3 := (others => '0');

overflow <= '0';

count := 0;

elsif(clk'event and clk='1' and w_load='0') then

count := count+1;

prod1 := w1(1) * xin(1);

prod2 := w2(1) * xin(2);

prod3 := w3(1) * xin(3);

sign1:=acc1(acc1'high);



acc1 := prod1 + acc1;



if((sign1 = prod1(prod1'high) and acc1(acc1'high)/= sign1) or

(sign2 = prod2(prod2'high) and acc2(acc2'high)/= sign2) or

(sign3 = prod3(prod3'high) and acc1(acc3'high)/= sign3)) then

overflow <= '1';

else

overflow <= '0';

end if;

y1 <= acc1;

y2 <= acc2;


- 124 -

y3 <= acc3;

if (count = 3) then

acc1:= (others => '0');

acc2:= (others => '0');

acc3:= (others => '0');

count:= 0;

end if;

end if;

end process;

end Behavioral;

• Simulation



- 125 -

Activation function (Sigmoid function)

• Code

library IEEE;




--------------------------------------------------------------------------------------------------------------------------------

entity p125a is

port(inp: in integer range -8 to 7;

outp: out signed (7 downto 0));

end p125a;

--------------------------------------------------------------------------------------------------------------------------------


Type rom is array (-8 to 7) of signed (7 downto 0);

signal table : rom := ("10000000",--first bit is radix and the others are the mantissa

"10000001",

"10000010",

"10000100",

"10001000",

"10010000",

"10100000",

"11000000",

"00000000",

"01000000",

"00100000",

"00010000",

"00001000",

"00000100",

"00000010",

"00000001");

begin

outp <= table(inp);

end Behavioral;


- 126 -

Conclusion

On solving these problems, I have faced these wrning message some of them I have

solved while others I ignored. The warnings I ignored are the following:

o“Property "use_dsp48" is not applicable for this technology.”

“C:/Xilinx92i/ISEexamples/xx" line 0 duplicate design unit: 'Module|xx”

These warning were safely ignored.

Sveral problems aren’t that clear, in turn, I have made several postpones on my own.

Some of the codes will start worhing in a bizarre way, however after few clock cycles the

system will settle or activating rst (written in VHDL) signal is ebough.

For keypad code, I have written my own code. However, it has some flaws that disturb

its functionality. Thus, I have taken the Keypad driver brought by PICC software and

converted it into VHDL on my own.

For the implementing the sigmoid function, a LUT is implemented for 8 bits width for 16

segment. This code is based on a table given in “Table 11.3. PWL approximation for the

15 segment bipolar sigmoid function” in FPGA Implmentation of Neural Network

byAMOS R. OMONDI


- 127 -

Refrences

[1] RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and

Scalability by Pong P.Chu.

[2] FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version by Pong P.Chu

[3] FPGA Implementations of Neural Networks by Amos R.Omondi

[4] PIC C Software Drivers.

[5] www.forums.xilinx.com

[6] www.edaboard.com

vhdl report

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