verilog tutorial - ece.ucsb.edustrukov/ece154afall2015/labs/verilog.pdf · originally designers...
TRANSCRIPT
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Verilog Tutorial
Adapted from Krste Asanovic
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Verilog Fundamentals
• History
• Data types
• Structural Verilog
• Functional Verilog
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Originally designers used manual translation + bread boards for verification
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Hardware design languages enabled logic level simulation and verification
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Once design were written in HDLs tools could be used for automatic translation
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Primary Verilog data type is a bit-vector where bits can take on one of four values
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The Verilog keyword wire is used to denote a standard hardware net
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Verilog includes ways to specify bit literals in various bases
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Verilog Basics
• Data types
• Structural Verilog
• Functional Verilog
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A Verilog module includes a module name and a port list
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A Verilog module includes a module name and a port list
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A module can instantiate other modules creating a module hierarchy
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A module can instantiate other modules creating a module hierarchy
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A module can instantiate other modules creating a module hierarchy
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Verilog supports connecting ports by position and by name
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Let’s review how to turn our schematic diagram into structural Verilog
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Let’s review how to turn our schematic diagram into structural Verilog
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Verilog Fundamentals
• Data types
• Structural Verilog
• Functional Verilog
– Gate level
– Register transfer level
– High-level behavioral
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Functional Verilog can roughly be divided into three abstraction levels
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Gate-level Verilog uses structural Verilogto connect primitive gates
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Continuous assignments statementsassign one net to another or to a literal
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Using continuous assignments to implement an RTL four input mutliplexer
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Verilog RTL includes many operators in addition to basic boolean logic
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Verilog RTL operators
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Always blocks have parallel inter-block and sequential intra-block sematics
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Always blocks have parallel inter-block and sequential intra-block sematics
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Always blocks have parallel inter-block and sequential intra-block sematics
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Always blocks have parallel inter-block and sequential intra-block sematics
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Always blocks have parallel inter-block and sequential intra-block sematics
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Continuous and procedural assignment statements are very different
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Always blocks can contain more advanced control constructs
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What happens if the case statement is not complete?
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What happens if the case statement is not complete?
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So is this how we make latches and flip-flops?
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To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution sematics
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To understand why we need to know more about Verilog execution sematics
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To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution sematics
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To understand why we need to know more about Verilog execution sematics
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We didn’t model what we expected due to Verilog execution semantics
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Non-blocking procedural assignments add an extra event queue
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Non-blocking procedural assignments add an extra event queue
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The order of non-blocking assignments does not matter
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Common patterns for latch and flip-flop inference
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Writing Good Synthesizable Verilog
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Behavioral Verilog is used to model the abstract function of a hardware
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Verilog can be used to model the high-level behavior of a hardware block
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Delay statements should only be used in test harnesses
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System tasks are used for test harnesses and simulation management
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Which abstraction is the right one?
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Examples
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Mux4: Gate-level structural Verilog
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Mux4: Using continuous assignments
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Mux4: Behavioral style
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Mux4: Using always block
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Mux4: Always block permit more advanced sequential idioms
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Parametrized mux4
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Flip-flops
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Flip-flops with reset
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Register
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Register in terms of Flip-flops
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Static Elaboration: Generate
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A simple state machine for valid/ready signals
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Implementing the control logic finite state machine in Verilog
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Implementing the control signal outputs for the finite state machine
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Implementing the state transitions for the finite state machine
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Take away points