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  • VHDLIMPLEMENTATIONOFFLOATINGPOINTMULTIPLIERBASEDONVEDICMULTIPLICATIONTECHNIQUE

    PRAGATISACHAN

    M.Tech(VLSI)Scholar,ElectronicsandcommunicationEngineering,JayotiVidyapeethWomensUniversityJaipur,Rajasthan,India,sachanpragati.kgi@gmail.com

    ABSTRACT

    Inthispaper,IEEE floatingpoint formatwasastandard formatused inallprocessingelementssinceBinary floatingpointnumbersmultiplication isoneofthebasic functionsused indigitalsignalprocessing(DSP)application. InthatworkVHDLimplementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The idea for designing themultiplier unit is adopted from ancient Indianmathematics "Vedas". The Urdhvatriyakbhyam sutrawill be used for themultiplicationofMantissa.Theunderflowandoverflowcaseswillbehandled.Theinputstothemultiplierin32bitformat.ThemultiplierisdesignedinVHDLorVERILOGandsimulatedusingModelsim.Keywords:VedicMathematics,Urdhvatriyakbhyamsutra,FloatingPointmultiplier,FPGA.1.INTRODUCTION1.1 FLOATING POINT MULTIPLIER FOR IEEEFORMATEMultiplication of two nos using Urdhva Tiryakbhyamsutraisperformedbyverticallyandcrosswise,crosswisemeans diagonal multiplication and vertically meansstraight abovemultiplication and taking their sum.Thefeature is any multibit multiplication can be reduceddowntosinglebitmultiplicationandadditionusingthismethod. On account of these formulas, the carrypropagationfromLSBtoMSBisreducesduetoonestepgeneration of partial product, the efficient use of Vedicmultiplicationmethod inorder tomultiply two floatingpointnumbers.Thisworkpresentsanimplementationofa floating pointmultiplier that supports the IEEE 7542008binaryinterchangeformat.Basedonthediscussionmade above it is very clear that a multiplier is a veryimportant element in any processor design and aprocessor spends considerable amount of time inperforming multiplication and generally the most areaconsuming.Hence,optimizingthespeedandareaofthemultiplier is a major design issue. An improvement inmultiplication speed by using new techniques cangreatlyimprovesystemperformance.Inthenextstageofthe project the design will be designed using VHDL orVERILOG and will be simulated using ModelsimSimulator. The design will be synthesized using XilinxISE12.1 tool.A testbenchwillbeused togenerate thestimulus and the multiplier operation is to beverified.The over flow and under flow flags are toincorporated in the design in order to show the overflow and under flow cases. The theory states that theefficient useofVedicmultiplicationmethod in order tomultiplytwofloatingpointnumbers.Thatthehardwarerequirement is reduced, thereby reducing the powerconsumption. The power consumption upon reducingaffectively may not compromise delay so much.MultiplicationofthefloatingpointnumbersdescribedinIEEE754singleprecisionvalid.Floatingpointmultiplier

    is done using VHDL.Implementation in VHDL(VHSICHardware Description Language) is used because itallow direct implementation on the hardware while inotherlanguagetheyhavetoconvertthemintoHDLthenonly can be implemented on the hardware. In floatingpointmultiplication,addingofthetwonumbersisdonewith the help of various types of adders but formultiplication some extra shifting is needed. Thisfloating pointmultiplication handles various conditionslike overflow, underflow, normalization, rounding. Inthis work they use IEEE roundingmethod for performthe roundingof the resultednumber.Thiswork focusesonly on single precision normalized binary interchangeformat targeted for Xilinx Spartan3 FPGA based onVHDL.ThemultiplierwasverifiedagainstXilinxfloatingpoint multiplier core. It handles the overflow andunderflow cases. Rounding is not implemented to givemore precisionwhenusing themultiplier in aMultiplyandAccumulate(MAC)unit.1.2 VEDICMULTIPLIERFORBINARYNUMBERSThe design of high speed and area efficient BinaryNumber Multiplier often called Binary Vedic Multiplierusing the techniques of Ancient Indian VedicMathematics i.e.Urdhva Tiryagbhyam Sutra. UrdhvaTiryagbhyam Sutra is the Vedic method formultiplication which strikes a difference in the actualprocessofmultiplicationitself,givingminimumdelayformultiplication of all types of numbers, either small orlarge. The work has proved the efficiency of BinaryNumberMultiplierdesignedusingUrdhvaTiryagbhyamSutra where multiplication process enables parallelgeneration of intermediate products and eliminatesunwantedmultiplicationsteps.Further,theVerilogHDLcoding of Urdhva Tiryagbhyam Sutra for 23x23 bitsmultiplication and their implementation in XilinxSynthesis Tool on Spartan 3E kit have been done. Thepropagationtimefortheproposedarchitectureis26.559ns.Theworkthenextendsmultiplicationto1616Vedicmultiplierusing"NikhilamSutra"technique.The1616

    PRAGATI SACHAN et al.

    Volume 3 Issue 4: 2015

    Citation: 10.2348/ijset07150914

    Impact Factor- 3.25

    ISSN (O): 2348-4098

    ISSN (P): 2395-4752

    International Journal of Science, Engineering and Technology- www.ijset.in 914

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