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PR030600-0033 page -1 Using the Using the Anadigm Anadigm ® ® FPAA to Interface FPAA to Interface With Sensors With Sensors Technical Considerations Technical Considerations

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PR030600-0033 page - 1

Using the Using the AnadigmAnadigm®® FPAA to Interface FPAA to Interface With Sensors With Sensors –– Technical ConsiderationsTechnical Considerations

PR030600-0033 page - 2

Sensor Signal Conditioning NeedsSensor Signal Conditioning Needs

Common signal conditioning tasks:AmplificationOffset removal RectificationFiltering

-1

0

1

2

3

4

5

6

0 0.2 0.4 0.6 0.8 1 1.2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.2 0.4 0.6 0.8 1 1.2

PR030600-0033 page - 3

Sensor Signal Conditioning NeedsSensor Signal Conditioning Needs

Common conditioning tasks

sensoramplification filteringoffset-removal

+-

PR030600-0033 page - 4

Operating Limits (1): Operating Limits (1): High Clock FrequenciesHigh Clock Frequencies

Finite OpAmp bandwidthCapacitors must charge or discharge within each half clock-cycleOpAmp speed affects settling-time

Non-zero switch resistance

Similar effect on settling-time

Effect of settling time-constant on filter response

-80.000

-70.000

-60.000

-50.000

-40.000

-30.000

-20.000

-10.000

0.000

10.000

300 320 340 360 380 400 420 440 460

Signal Frequency(kHz)

Gai

n (d

B)

tau=1ns 10ns 15ns 20ns 30ns

PR030600-0033 page - 5

Finite OpAmp GainProvided opamp has high open-loop gain and high input-resistance then:

If open-loop gain is not infinite then:

-+

R1

R2

211RR

G−=

AARR

G111

211

+−=

Effect of opamp gain on filter response

-80

-70

-60

-50

-40

-30

-20

-10

0

10

300 320 340 360 380 400 420 440 460

Signal Frequency (kHz)

Gai

n (d

B)

A=1M A=10K A=1K A=100

Operating Limits (2): Operating Limits (2): High Signal FrequenciesHigh Signal Frequencies

PR030600-0033 page - 6

Operating Limits (3): Operating Limits (3): Low Clock FrequenciesLow Clock Frequencies

“Droop”The charge that should be stored on a node is:

Q = C.VThis charge will be changed (+ or -) by leakage:∆QL = IL.T

So, the error will beError = IL.T/ C.V

For a specified max error:

T < (C.V)min.Error(IL)max

+-

So, using some approximate values:– C ≅ 10-11 (farad)– V ≅ 10-3 to 1 (volt)– So, CV ≅ 10-11 to 10-14 (coulomb)– IL ≅ 10-15 to 10-18 (amperes)

For a leakage errors of 0.1% or less: T < (C.V)min.Error / (IL)max ≅ 10-14.10-3 / 10-15 ≅ 10-2 (secs)

We can obtain leakage errors of 0.1% or less for millivolt signals, for sampling frequencies in the low kHz range.

PR030600-0033 page - 7

Offset VoltagesOffset Voltages

Offset errorsSlight mismatches inside the opamp require balancing with a small input voltage Output voltage will have a DC error

-+

Vos

Vin

Vout

V=Vos

R2

R1

++−= 1

12

12.

RRV

RRVV osinout

Vin = 0

PR030600-0033 page - 8

Offset CompensationOffset Compensation

“Half-cycle” building blocks allow cancellation of offset voltage

GainHalfGainHoldRectifierHalfRectifierHoldSumDiff

“Offset-compensated” in one clock phase only (return-to-zero or hold-with-offset in other phase)

Gain-Bandwidth Product (GBP) and slew-rate are not infinite!

Selection of high-gain will limit max clock frequency (and vice versa) of RTZ CAMs

-

+

Vos

Vout = Vos

Vin-VosVos

-

+

+ -

Vos

Vout = Vin

-VosVos - Vin

Vin

+ -

PR030600-0033 page - 9

Achieving HighAchieving High--gaingain

Cascade stages – high-gain at front-end for low-noise

Use offset-compensated CAMs when implementing large gains

Remember GBP limitations – select appropriate clock frequency (but watch anti-aliasing requirements)

Vs

k1 k2 k3

Vout= k1k2k3.Vs + VNoiseV1= k1.Vs + V1Noise

++=

321211

321.kkk

Vkk

Vk

VKV noisenoisenoisenoise

PR030600-0033 page - 10

Phase SelectionPhase Selection

Some CAMs have outputs which are only valid (or offset-compensated) in one phaseMake sure input-sampling and output-valid phases match!

PR030600-0033 page - 11

Output Waveforms (1)Output Waveforms (1)

Staircase outputs:

Use high fclock/fsignal ratio to reduce step size and clock noiseKeep fcorner/fsignal > 30 if using output cell filterIf output is being sampled (eg by ADC), steps may be desirable !

PR030600-0033 page - 12

Output Waveforms (2)Output Waveforms (2)

“Final-value” outputsDifferentiator (and transimpedance amplifier) outputs only reach their final value at the end of a clock phaseFinal-value CAM outputs need capturing by CAMswhich sample in one-phase and produce a valid output in the next

HoldNon-inverting GainHalfNon-inverting SumDiffNon-inverting SumFilter

PR030600-0033 page - 13

Input LevelsInput Levels

Internal signal ground is 2 volts (VMR)

Center inputs on 2V if possible (use Wheatstone bridge?)Input range 0 – 4VConvert external single-ended signals to internal differential signals for max dynamic range

VMR

+V

+V

FPAA

FPAA

PR030600-0033 page - 14

Offset RemovalOffset Removal

Single-ended signals – apply offset to 2nd

input pin

Differential signals –apply offset internally

Using differential signals gives better CM noise immunity

+V

+V

FPAA

FPAA

+Voffset

PR030600-0033 page - 15

Using the Chopper InputUsing the Chopper Input

“Chopping” modulates the input signal with a square wave

Low freq noise and DC offsets are pushed out to the clock freq (for easy filtering)

Slewing and settling limitations mean the chopper output is not “ideal”

To recover the “ideal” output, sample in phase2 at twice the chopper frequency

To boost the gain, use offset-compensated CAMs, sampling in phase2 at twice the chopper frequency

PR030600-0033 page - 16

Noisy EnvironmentsNoisy EnvironmentsUse differential signals where noise can be made common-modeUse modulated sensor stimulus and synchronous demodulation (lock-in detection)

OUTCLK

VMR

Clockgenerator

PR030600-0033 page - 17

Phase DetectionPhase Detection

Synchronous demodulation

0.860.50

-0.86-0.50

0.860.50

-0.86-0.50

0.860.50

-0.86-0.50

Clockgenerator

4.fc

2.fc fc

sin(2.π.fc.t + 30)

sin(30o)

cos(30o)

PR030600-0033 page - 18

AntiAnti--aliasing and Clock Selectionaliasing and Clock Selection

Input signal should be band-limited to << fclock/2prevents hf noise adding to lf noiseUse a clock at least 5–10 times faster than the maximum signal

Use continuous-time not SC filteringattenuation at fclock/2 should attenuate any hf signals by the required SNRKeep fcorner/fsignal > 30 if using input cell filter

Lock-in detection averages out noise & signals except at harmonics of the modulation frequency

Anti-aliasing not necessary (but will improve SNR if used)

PR030600-0033 page - 19

TemperatureTemperature--sensing (1)sensing (1)

ThermistorsResistances range from 100 to 1MohmTypical current < 100uA to avoid self-heating

PR030600-0033 page - 20

TemperatureTemperature--sensing (2)sensing (2)

ThermocouplesSmall voltage/degree CProne to high levels of CM noise

VMR

PR030600-0033 page - 21

TemperatureTemperature--sensing (3)sensing (3)Thermopiles

Serially-interconnected thermocouples with “hot” and “cold” junctions“Hot” junction sensitive to received IR radiationClose proximity of junctions gives low sensitivity to ambient temperature

VMR

10K

PR030600-0033 page - 22

PositionPosition--sensing (1)sensing (1)

Strain gaugesTypical output < 10 mV/V “Half bridge” has strain gauges in two arms:

doubles the output and compensates for thermal effects

“Full bridge” has strain gauges in four arms:

re-doubles output and compensates for thermal effects

+V

fchop= 1kHzfLP = 4Hz

PR030600-0033 page - 23

PositionPosition--sensing (2)sensing (2)

LVDT• Sensitivity ranges:

• 0.05 mV/V/0.001” for long stroke LVDTs• 10 mV/V/0.001” for short stroke LVDTs

Various signal processing techniques (eg): Rectify and filter AC signals, then:

Calculate (VA + VB)/Vprimary (insensitive to the amplitude of the driving signal, and gives some noise rejection). Calculate the ratio of the difference and the sum of the secondary voltages i.e. (VA – VB) / (VA+VB)

Measure the phase of the combined VA + VB secondary voltage i.e. -180 degrees at one extreme, zero degrees at the null position, and +180 degrees at the other extreme.

~

VA VB

PR030600-0033 page - 24

LVDTLVDT--sensingsensing

VB

VA

PR030600-0033 page - 25

MagneticMagnetic--sensingsensing

Hall effect devicesUsually driven with a constant current

Differential output voltage, superimposed on a common-mode voltage approximately equal to half the excitation voltage.

Typical sensitivity:1-100 mV/kG(Refrigerator magnet: 200 gauss)

Typical element resistance: 1 to 10 ohms

Typical excitation current: 20 to 200 mA.

Typical linearity:0.1% to 2%.

Ibias

PR030600-0033 page - 26

OpticalOptical--sensingsensing

Photodiode/transistorPhoto-generated current develops a voltage across a feedback “resistor”Transimpedance is dependent on absolute capacitor values, not a capacitor ratioTransimpedance CAM output is only valid at the end of each clock phase –follow by an appropriate CAM

Iin

Iin

PR030600-0033 page - 27

Sensor LinearizationSensor Linearization

Analog core cell.

SAR ADC LUT

interface

0.000.050.100.150.200.250.300.35

0 10 20 30 40 50 60 70 80

Temperature (C)

Volta

ge

Sensor output isnon-linear Signal dependent gain

0

5

10

15

20

25

0.00 0.10 0.20 0.30

Voltage

Gai

n

Linear temperature/voltage characteristic

0

0.5

1

1.5

2

2.5

3

0 10 20 30 40 50 60 70 80

Temperature (C)

Volta

ge

NTC thermistor-based sensor

PR030600-0033 page - 28

Sensor LinearizationSensor Linearization

TransferFunctionCAM

Quantizes gain – use full-scale input and output for minimum non-linearityWhen the input signal is nearly linear, use “delta” information rather than “direct”

PR030600-0033 page - 29

Hardware MultiplexingHardware MultiplexingState-driven dynamic reconfiguration:

microprocessor

Configurationdata

sensor #1

sensor #2

sensor #3

sensor #4

sensor #5

sensor #6

sensor #7

1 2 3 4 5 6 7