upt - lecture 9 - intel memory interface

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Brey: The Intel Microprocessors, 7e

Memory Interface Barry B. Brey

[email protected]


There are two types of memory, RAM and ROM.

ROM is read-only memory and could be an EPROM or FLASH (EEPROM) memory.

RAM is read/write memory and could be SRAM (static) or DRAM (dynamic).

All memory devices have address inputs that select a location on the memory. Address lines are number from A0 to as many as required to address the locations on the memory.


All memory device has data pins that are numbered usually from D0 to D7. D0 is the least significant bit and most memory devices have 8-bit width. Even the latest DDR memory for your computer has memory devices that are 8-bits in width, eight devices form a 64-bit wide memory.

All memory device has a set of control inputs. The output enable (#OE) input is used to cause a read and the write enable (#WE) input causes a write. Neither of these inputs do anything unless the chip select input (#CS) is also true.


A0

A1

A2

.

.

.

An

O0

O1

O2

.

.

.

Om

WE

OE CS

Write

Read Select

Output

or

Input/Output

connection

Address

connections

Generic memory device interface


Read Only Memory

Non Volatile

Types ◦ PROM

◦ EPROM

◦ RMM (Read Mainly Memory) known as Flash or EEPROM

◦ EAROM (Electrically Alterable ROM) or NOVRAM (Non volatile RAM)


EPROM 2716 2Kx8


The number of memory address pins are determined by the number of memory locations on a device.

A few number to remember are that a 1K memory device has 10 address pins and a 1M device has 20 address pins.

By doing so, you can easily figure out how many address pins are on a memory. Every time the number of locations doubles, one additional address pin is needed. A 4K device requires 12 pins. A 16 M device contains 24 address pins.


Many memory device are 8-bits width.

A 4K x 8 memory contains 4,096 (4K) memory locations that each contain 8-bits.

A 16M x 4 memory has 16 M memory locations that are each 4-bits wide.

A 512M byte DDR memory for your PC is organized as a 64M x 64 memory. It contains eight 64M x 8 memory devices.


Static RAM

Dynamic RAM

SIMM & DIMM RAM Modules


A static RAM is a memory device that retains data for as long as power is applied. A static Ram memory cell contains a pair of inverters connected as illustrated below.

In0 In1

Output


Some DRAMs contain multiplexed address inputs to reduce the number of address connections on the memory device.

Suppose we have a 1M x 8 DRAM. This would normally require 20 address connections, but since the address inputs are multiplexed it only contains 10 address inputs.

A0-A9 (row) is sent to memory through the 13 address input and then A10-A19 (col) is sent to the same address pins.


74LS157.pdf


30 pins SIMM 4Mx9

(8 + 1 parity bit)

72 pins SIMM 4Mx36

(32 + 4 parity bits)

SIMM

Single In-line Memory Module


DIMM

Dual In-line Memory Module

16MB(2Mx64), 32MB(4Mx64), 64MB(8Mx64), 128MB(16Mx64)

DRAM, EDO, SDRAM


When memory is interfaced, the address signals not decoded by the memory device must be externally decoded.

For example, a 32K x 8 memory device has 15 address inputs (A0-A14). If it is connected to a microprocessor with 20 address signals there is a mismatch. The extra address pins (A15-A19) are decoded using a decoded to select the memory device for a unique location in the memory.


Suppose we wish to place the 32K x 8 memory device at location 10000H. A 32K memory device contains 8000H memory locations so it begins at 10000H and ends at 17FFFH, which are 8000H locations.

A few numbers to remember are 1000H is 4K and 10000H is 64K. These numbers help to determine address ranges of memory devices. 100000H is 1M might also be a good number to remember.


Location 10000H-17FFFH appear as follows in binary.

10000H = 0001 0000 0000 0000 0000

17FFFH = 0001 0111 1111 1111 1111

Since the memory takes care of A0-A4 we are left with

0001 0 (A19-A15)

This is the number decoded (that is unique) to this area of memory.


Decoding 0001 0


A0-A10

RD

IO / M

D0-D7


Even though integrated decoders are less common than they once were, they still have some application in embedded systems.

Two common decoders are the 74HCT138 and the 74HCT139. The ‘138 in particular is common because of the six input connections.


Note 1: G2= G2A + G2B


Decodificación de 8

EPROMS 2764 para una

sección de memoria de

8K x 8 para el 8088.

Rango F0000H a FFFFFH

74LS

138

A13

A14

A15

A16

A17

A18

A19


D0 - - D7

A0 - - A14

A18

A19

A15

A16

A17

RD

IO/M


128K x 8 Nmos

EPROM Memory

D0 – D7

A0 – A16

A17 A18

IO/#M

A19

#RD #WR

128K x 8 CMOS SRAM with

Data Retention and Low Power

74HCT139

74HCT139


Many modern systems use programmable logic decoders in place or integrated decoders.

These PLD may be called PLDs, GALs, PLAs, PALs, CPLDs, etc. They are all programmable logic devices that today use VHDL for programming.

The next slide show one of the most common low cost (49¢) devices the PAL16L8.


D0 - D7

A0 - A16

IO/#M

A17 A18 A19

#RD #WR

A GAL 22V10 decoding 2

memory devices


library ieee;

use ieee.std_logic_1164.all;

entity DECODER_10_17 is

port (

A19, A18, A17, MIO : in STD_LOGIC;

ROM, RAM, AX19 : out STD_LOGIC

);

end;

architecture V1 of DECODER_10_17 is

begin

ROM <= A19 or A18 or A17 or MIO;

RAM <= A18 and A17 and (not MIO);

AX19 <= not A19;

end V1;


Flash Memory 28F400 interfaced

to an 80888 Microprocessor


16-bit wide memory is organized in two 8-bit wide memory banks because each byte is a memory location and this is the only organization that allows any byte to be read or written.

Banks are selected by the microprocessor through bank selection signals called Bank Enable signals. A 16-bit wide memory has a #BLE and a #BHE signal.

8086 to 80386SX


BHE (BLE)


In these systems there are two ways to carry out the bank selection:

◦ Separate address decoders

It is more expensive

Better energy use

◦ Separate write pulses

Simple

Less expensive


Separate address

decoders 8086, 80186, 80286 and

80386SX

BLE = (A0)

BHE = New signal in 80386SX

processers

M/IO BHE

BLE


Separate write signals.

A0 may be the #BLE signal (microprocessor dependent).

#HWR Escritura en banco alto

#LWR Escritura en banco bajo

Se usa un pulso de escritura separado

para cada banco

Esta técnica requiere un solo decodificador

para una memoria de 16 bits de ancho


Decodificador de

memoria de 16 bits

D8 – D15

D0 – D7

A1 – A15

#MRDC

A23

A22

A21

A20

A19

A18

A17

A16

A0(#BLE)

#BHE

#MWTC


library ieee;

use ieee.std_logic_1164.all;

entity DECODER_10_28 is

port (

A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC : in STD_LOGIC;

SEL, LWR, HWR : out STD_LOGIC

);

end;

architecture V1 of DECODER_10_28 is

begin

SEL <= A23 or A22 or A21 or A20 or A19 or (not A18) or (not A17) or A16;

LWR <= A0 or MWTC;

HWR <= BHE or MWTC;

end V1;


Un sistema de memoria para 8086 que contiene una EPROM de 64KB y una SRAM de 128 KB


Un sistema de memoria para el 80386SX que contiene una EPROM de 256K y una SRAM de 128K


library ieee; use ieee.std_logic_1164.all; entity DECODER_10_30 is port ( A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC : in STD_LOGIC; LWR, HWR, RB0, RB1, RB2, RB3 : out STD_LOGIC ); end; architecture V1 of DECODER_10_30 is begin LWR <= A0 or MWTC; HWR <= BHE or MWTC; RB0 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or A16; RB1 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or not(A16)); RB2 <= not(A23 and A22 and A21 and A20 and A19 and A18 and A17); RB3 <= not(A23 and A22 and A21 and A20 and A19 and A18 and not(A17)); end V1;


Serious banks, four banks or 8-bit wide memory are required to build a functioning 32-bit wide memory system. Since memory is addressed by byte the memory must be organized in 8-bit wide banks.


Data alignment becomes more important with wider memory. If a 16-bit number is stored at location 3, it requires 2 write. The first write data to byte 3 and the second to byte 4, which is in a different bank.

In the assembler use align 2 for words. In C++ use declspec(align(2)) (no semicolon) This prevents any misalignment of data. Align 4 is used for doublewords and align 8 is used for quadwords. (for SIMD data use align 16 for octalwords.)


Organización de memoria para los microprocesadores 80386DX y 80486


Señales de escritura de banco para los microprocesadores 80386DX y 80486 (nuevas)


Un pequeño sistema de

memoria de 256 K

interconectado al

microprocesador 80486


library ieee; use ieee.std_logic_1164.all; entity DECODER_10_30 is port ( A30, A29, A28, A27, A26, A25, A24, A23, A22, A21, A19, BE0, BE1, BE2, BE3, MWTC : in STD_LOGIC; RB0, RB1, WR0, WR1, WR2, WR3 : out STD_LOGIC ); end; architecture V1 of DECODER_10_30 is begin WR0 <= BE0 or MWTC; WR1 <= BE1 or MWTC; WR2 <= BE2 or MWTC; WR3 <= BE3 or MWTC; RB0 <= A30 or A29 or A28 or A27 or A26 or A25 or A24 or A23 or A22 or A 21 or A19; RB1 <= A30 or A29 or A28 or A27 or A26 or A25 or A24 or A23 or A22 or A 21 or not(A19); end V1;


More banks! 64-bit wide memory is organized as a 8 bank wide system. Are there wider memory systems? Yes, the Itanium has a 128-bit wide memory system!


Organización de memoria de los microprocesadores Pentium y Pentium II


Una pequeña memoria de 512 KB interconectada a los microprocesadores Pentium y Pentium II


library ieee; use ieee.std_logic_1164.all; entity DECODER_10_36 is port ( A31, A30, A29, A28, A27, A26, A25, A24, A23, A22: in STD_LOGIC; SEL: out STD_LOGIC ); end; architecture V1 of DECODER_10_36 is begin SEL <= not(A31 and A30 and A29 and A28 and A27 and A26 and A25 and A24 and A23 and A22); end V1;


Dynamic RAM is internally structured as very wide words. IN the next slide the memory is structured as 1024 bit wide words to reduce the amount of time spent looking up a new location. This is important in DRAM because of its slow access time. Dynamic RAM has an access time of at best 40 ns or so.

Many methods have been employed to reduce this access time such as wide internal memory where many bytes are accessed at a time then passed to the outside world through high speed multiplexers.


La estructura interna de una DRAM de 256 K x 1

Cada una de las 256 palabras tiene 1024 bits de ancho

upt - lecture 9 - intel memory interface

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memory devices

types of memory

wide memory

readwrite memory

number of memory locations

number of memory address

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