unsigned divider rtl model

8/18/2019 Unsigned Divider RTL Model

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Unsigned Divider Assignment 6 : EE224

Name :- Yogesh Mahajan Roll No. :- 14D070022

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Set quotient to 0

Align leftmost digits in dividend and divisor

Repeat

o If that portion of the dividend above the divisor is greater than or equal to the

divisor

Then subtract divisor from that portion of the dividend and

Concatenate 1 to the right hand end of the quotient

Else concatenate 0 to the right hand end of the quotient

o

Shift the divisor one place right

Until dividend is less than the divisor

quotient is correct, dividend is remainder

STOP

Division by 0 gives quotient “11111111”, so “11111111” is considered as don’t care state.


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rest : if(tsrt == '1') theninit q,r = 0; areg = a; breg = b;count = 8

goto updateend if

update : if(count == '0') then

goto doneStateelse

areg =


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--16 Bit Divider RTL Model---Control Path------------------------------------------------

library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.numeric_std. ALL;

entity controlPath is port (clk,rst : in std_logic;

start : in std_logic; done : out std_logic; T : out std_logic_vector(4 downto 0); S : in std_logic_vector(1 downto 0));

end entity;

architecture behave of controlPath is

type FSMstate is (rest,update,comp,sub,doneState); signal fsm_state : FSMstate;

begin

process(fsm_state,start,clk,rst,S) variable next_state : FSMstate; variable Tvar : std_logic_vector(4 downto 0); variable done_var : std_logic;

begin

if(clk'event and (clk = '1')) then if(rst = '1') then

fsm_state --- setup all registers if(start = '1') then

next_state := update; Tvar(0) := '1';

end if;


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when update => --- shift registers & checking shifts if(S(1) = '1') then -- 8 shifts done

Tvar(4) := '1'; -- update output in next state next_state := doneState;

else

Tvar(1) := '1'; next_state := comp;

end if;

when comp => -- compare if B < regD Tvar(2) := '1'; next_state := sub;

when sub => next_state := update; if(S(0) = '1') then -- subtractions when B done_var := '1'; next_state := rest;

end case;

T


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port (A: in std_logic_vector(3 downto 0); B: out std_logic_vector(3 downto 0));

end component;

component sub8bit is port( A,B : in std_logic_vector(7 downto 0);

sub : out std_logic_vector(7 downto 0)); end component;

component cmp8 is port (A,B : in std_logic_vector(7 downto 0);

g,e,l: out std_logic); end component;

component DataRegister is generic (data_width:integer); port (Din: in std_logic_vector(data_width-1 downto 0);

Dout: out std_logic_vector(data_width-1 downto 0); enable,clk : in std_logic);

end component;

signal count0 : std_logic; signal count,count_in,dcrCount : std_logic_vector(3 downto 0); signal areg,lsa,areg_in : std_logic_vector(7 downto 0); signal breg,breg_in : std_logic_vector(7 downto 0); signal rreg,lsr,subb,rreg_in : std_logic_vector(7 downto 0); signal qreg,qreg_in,lsq : std_logic_vector(7 downto 0); signal quotient_in,remainder_in : std_logic_vector(7 downto 0); signal

countEnable,aregEnable,bregEnable,rregEnable,qregEnable,resultEnable : std_logic;

signal g,e,l : std_logic;

------------process begins------------------------------------- begin

--set operations complete------- count0


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aregEnable


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qr : DataRegister generic map(data_width => 8) port map(qreg_in,qreg,qregEnable,clk);

--result Logic--------- resultEnable


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component dataPath is port( clk,rst : in std_logic;

t : in std_logic_vector(4 downto 0); s : out std_logic_vector(1 downto 0);

a,b : in std_logic_vector(7 downto 0); quotient,remainder : out std_logic_vector(7 downto 0));

end component;

signal t : std_logic_vector(4 downto 0); signal s : std_logic_vector(1 downto 0);

begin

cp : controlPath port

map(clk,rst,input_ready,divider_ready,output_ready,output_accepted,t,s);

dp : dataPath port map(clk,rst,t,s,dividend,divisor,quotient,remainder);

end structure; ---------------------------------------------------------------

--Divider components-------------------------------------------

--shiftCounter8------------------------------------------------

library ieee; use ieee.std_logic_1164.all;

entity shiftCount8 is port (A: in std_logic_vector(3 downto 0);

B: out std_logic_vector(3 downto 0)); end entity shiftCount8;

architecture Serial of shiftCount8 is begin

process(A) variable borrow: std_logic;

begin

borrow := '1';

for I in 0 to 3 loop B(I)


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use ieee.std_logic_1164.all;

entity lshift8 is port ( A : in std_logic_vector(7 downto 0);

B : out std_logic_vector(7 downto 0)); end entity;

architecture structure of lshift8 is

begin

B(7 downto 1)


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component compBlock is port(gp,ep,lp : in std_logic;

ak,bk : in std_logic; g,e,l : out std_logic);

end component;

signal gTmp,eTmp,lTmp : std_logic_vector(6 downto 0);

begin

cmp7 : compBlock port map('0','1','0',A(7),B(7),gTmp(0),eTmp(0),lTmp(0));

cmp6 : compBlock port map(gTmp(0),eTmp(0),lTmp(0),A(6),B(6),gTmp(1),eTmp(1),lTmp(1));



cmp3 : compBlock port

map(gTmp(3),eTmp(3),lTmp(3),A(3),B(3),gTmp(4),eTmp(4),lTmp(4)); cmp2 : compBlock port map(gTmp(4),eTmp(4),lTmp(4),A(2),B(2),gTmp(5),eTmp(5),lTmp(5));


cmp0 : compBlock port map(gTmp(6),eTmp(6),lTmp(6),A(0),B(0),g,e,l);

end architecture;

---------------------------------------------------------------

-- Register----------------------------------------------------

library ieee; use ieee.std_logic_1164.all; entity DataRegister is

generic (data_width:integer); port (Din: in std_logic_vector(data_width-1 downto 0);

Dout: out std_logic_vector(data_width-1 downto 0);

enable,clk: in std_logic); end entity;

architecture Behave of DataRegister is begin

process(clk)

begin if(clk'event and (clk = '1')) then

if(enable = '1') then Dout

unsigned divider rtl model

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