unit – 2 combinational logic circuits

10CS 33 LOGIC DESIGN

Objectives

• Understand what are combinational logic circuits

• Use the sum-of-products method to design a logic circuit based on a design truth table

• Be able to make Karnaugh maps

Introduction

Logic Circuits are categorized into 2 types (based on whether they contain memory or not):

• Combinational Logic Circuits

o Circuits without memory

• Sequential Logic Circuits

o Circuits with memory

Combinational Logic Circuits

The output of combinational logic circuit depends only on the current inputs

circuit block is as shown below:

There are two fundamental approaches in logic d

• The Sum-of-Products (SOP)

– Solution results in an AND

LOGIC DESIGN UNIT – 2 Combinational Logic Circuits

combinational logic circuits

method to design a logic circuit based on a design truth table

Karnaugh maps and use them to simplify Boolean expressions

are categorized into 2 types (based on whether they contain memory or not):


Circuits without memory

Circuits with memory


The output of combinational logic circuit depends only on the current inputs. A combinational logic

There are two fundamental approaches in logic design. They are:

Products (SOP) Method

Solution results in an AND-OR or NAND-NAND network


method to design a logic circuit based on a design truth table

and use them to simplify Boolean expressions

are categorized into 2 types (based on whether they contain memory or not):

. A combinational logic

Unit – 2 Combinational Logic

Circuits

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10CS 33 LOGIC DESIGN UNIT – 2 Combinational Logic Circuits

• The Product-of-Sums (POS) Method

– Solution results in an OR-AND or NOR-NOR network

We select a simpler circuit because it costs less and is more reliable.

The Sum-of-Products (SOP) Method

Product term

A product term is a conjunction of literals, where each literal is either a Boolean variable or its

complement.

Examples: A . B A’ . B. C’ A

Fundamental product or Minterm

For a function of n variables, a product term in which each of the n variables appears once

(in uncomplemented or complemented form) is called a fundamental product or minterm

Fundamental Products for Two inputs

Consider two inputs A and B. The fundamental products or minterms are listed below:

Inputs Fundamental

products or

minterms A B

0 0 m0 = A’ . B’

0 1 m1 = A’ . B

1 0 m2 = A . B’

1 1 m3 = A . B

Sum-of-Products (SOP) Equation

The SOP equation can be represented by an expression that is a sum of minterms, where each minterm

is ANDed with the value of Y for the corresponding valuation of input variables.

Consider,

Y = m0 . 0 + m1 . 1 + m2 . 1 + m3 . 1

= m1 + m2 + m3

= A’ . B + A . B’ + A . B

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Compact form

Y = f(A, B) = Σ m(1, 2, 3)

Truth Table:

Logic Circuit

For the obtained SOP equation, we can realize the logic circuit by drawing an AND

below:

Another way of realization is by a NAND

Simplified Logic Circuit

Consider the Boolean SOP equation:

Y = A’ . B + A . B’ + A . B


Inputs Output

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

For the obtained SOP equation, we can realize the logic circuit by drawing an AND-OR network

a NAND-NAND network as shown below:

equation:


OR network as shown

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We can simplify it

Y = A’ . B + A . B’ + A . B + A . B

= A’ . B + A . B + A . B’ + A . B

= B . (A’ + A) + A . (B’ + B)

= B . 1 + A . 1 = B + A = (A + B)

Logic Circuit:

Canonical Sum-of-Products Form

If each product term is a minterm, then the expres

or standard SOP form.

Example:

Y = A’ . B + A . B’ + A . B (canonical SOP form)

Y = A + B (simplified form)

3 Variable Example:

Y = A’ . B . C + A . B’ . C + A . B . C’ + A . B . C

= F(A, B, C)

= Σ m(3, 5, 6, 7)

Simplification

Y = A’ . B . C + A . B’ . C + A . B . C’ + A . B . C

Y = B . C . (A’ + A) + A . C .(B’ + B) + A . B . (C’ + C) using Adjacency Theorem

= B . C. 1 + A . C . 1 + A . B . 1

= B . C + A . C + A . B

Y = A . B + A . C + B . C


= A’ . B + A . B’ + A . B + A . B

= A’ . B + A . B + A . B’ + A . B

= B . (A’ + A) + A . (B’ + B)

= B . 1 + A . 1 = B + A = (A + B)

Y = (A + B)

f each product term is a minterm, then the expression is said to be in a canonical sum-

(canonical SOP form)

Y = A’ . B . C + A . B’ . C + A . B . C’ + A . B . C

Y = A’ . B . C + A . B’ . C + A . B . C’ + A . B . C

Y = B . C . (A’ + A) + A . C .(B’ + B) + A . B . (C’ + C) using Adjacency Theorem

A . C . 1 + A . B . 1


-of-products form

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The simplified logic expression is realized using NAND gates as shown below:

Truth Table To Karnaugh Map

A Karnaugh map (K-map) is a visual display of the fundamental products

modification of the Venn diagram and refinement of

by Maurice Karnaugh, an American Physicist

2 – Variable Karnaugh Map

Consider the Venn diagram for the two variables A and B.

The diagram is rewritten as shown below:


The simplified logic expression is realized using NAND gates as shown below:

Truth Table To Karnaugh Map

map) is a visual display of the fundamental products for a SOP solution

m and refinement of Edward Veitch's diagram. K-map

Maurice Karnaugh, an American Physicist.

sider the Venn diagram for the two variables A and B.

The diagram is rewritten as shown below:


for a SOP solution. K-map is a

map was developed

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Next, we obtain the Karnaugh map for two variables as shown below:

A’B’ A’B

AB’ AB

Alternate representation for Karnaugh map is as shown below:

Karnaugh Map Simplification

Consider a two-variable logic circuit. The first step is to convert 2-variable truth table into its Karnaugh

map (K-map).

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Example: Consider a two-variable truth table as given below:

Inputs Output

A B f

0 0 0

0 1 1

1 0 1

1 1 1

The two-variable K-map is drawn as shown below:

Terminology

Literal

A given product term consists of some number of variables, each of which may be in uncomplemented

or complemented form. Each appearance of a variable, either in uncomplemented or complemented, is

called a literal.

Example: The product term AB’C has 3 literals, and the term A’BC’D has 4 literals

Implicant

A product term that indicates the input valuation for which a given function is equal to 1 is called an

implicant of the function. Also there are the implicants that correspond to all possible pairs of minterms

that can be combined (set of 2i minterms, i<=n).

Prime Implicant

An implicant is called prime implicant if it is not a subset of another implicant of the function.

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Essential Prime Implicant

A prime implicant which includes a 1 cell that is not included in any other prime implicant is called an

essential prime implicant.

K-map Simplification Steps

The K-map simplification steps are:

1. Generate all prime implicants for the given function f

2. Find the set of essential prime implicants

3. If the set of essential prime implicants covers all valuations for which function f =1, then this set

is the desired cover of f

Otherwise, determine the nonessential prime implicants that should be added to form a

complete minimum-cost cover

Example:

The map contains 2 pairs of 1s which are prime implicants p1 and p2. They cover all valuations for

which f = 1. Both p1 and p2 are essential.

Consider the essential prime implicant p1.

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As we move from the first 1 to second 1, only one variable goes from complemented to

uncomplemented form i.e. A’ to A; the other variable B does not change. Whenever this happens, you

can eliminate the variable that changes form and we have p1 = B.

Next, consider the essential prime implicant p2.

Similarly p2 = A.

Hence we have the simplified Boolean expression

f(A, B) = A + B

Questions

1. Explain the definition of combinational logic.

2. Write the truth table of the logic circuit having 3 inputs A, B & C and the output expressed as

Y = AB’C + ABC. Also simplify the expression using Boolean Algebra and implement the logic circuit using

NAND gates.

3. Define prime implicant and essential prime implicant.

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Objectives

• Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions

• Understand don’t Care Conditions

• Use the Product-of-Sums Method to design a logic circuit based on a design truth table

• Perform conversion between SOP and POS

3 - Variable Karnaugh Map

Consider a logic equation Y = f(A, B, C). We have 8 fundamental products or minterms as shown below.

We need to arrange them so that they are adjacent.

A B C Minterms

0 0 0 A’B’C’ m0

0 0 1 A’B’C m1

0 1 0 A’BC’ m2

0 1 1 A’BC m3

1 0 0 AB’C’ m4

1 0 1 AB’C m5

1 1 0 ABC’ m6

1 1 1 ABC m7

Adjacent terms differ in the values of only one variable. A given 3-variable minterm will have 3 adjacent

terms.

Example: 3 adjacent terms of minterm ABC are: A’BC, AB’C, ABC’

We use Gray code to position the minterms. In Gray code, consecutive codes differ in one variable only.

Unit – 2

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3- bit Gray Code

The 3-bit Gray code is tabulated below:

G2 G1 G0

0 0 0

0 0 1

0 1 1

0 1 0

1 1 0

1 1 1

1 0 1

1 0 0

The 3 - variable Karnaugh map is drawn as shown making use of the Gray code.

3- Variable K-map Simplification

Example 1:

Consider Y = f(A, B, C) = Σ m (2, 3, 4, 6) = A’BC’ + A’BC + AB’C’ + ABC’

The Karnaugh map for the given logic expression is drawn as shown below:

The simplified expression Y = A’B + AC’

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Example 2:

Simplify Y = f(A, B, C) =Σ m (0, 2, 4, 6).


The simplified expression is Y= C’.

Example 3:

Simplify Y = f(A, B, C) =Σ m (1, 2, 3, 5, 6, 7)


The simplified expression Y= B + C.

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Consider a logic equation Y = f(A, B, C,D). We have 16 fundamental products or minterms and they are

arranged so that they are adjacent (4-bit Gray code is used).

4-Variable K-map Simplification

Example 1:

Simplify Y = f(A, B, C, D) = Σ m (1, 2, 3, 6, 8, 9, 10, 12, 13, 14).

The simplified Boolean equation is Y = A’B’D + AC’ + CD’.

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Example 2:

Simplify Y = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13).

The simplified equation is Y = C’ + A’D’ + B’D’.

Example 3:

Simplify Y = Σ m (3, 4, 5, 7, 9, 13, 14, 15).

Note that the quad covering minterms 5, 7, 13, and 15 is not a prime implicant. We cover the minterms

as shown:

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The simplified logic equation is Y = A’BC’ + A’CD + AC’D + ABC .

Don’t Care Conditions

In some digital systems, certain inputs conditions never occur. The output for the invalid inputs is not

defined and it is indicated by an X in the truth table. The X is called a don’t care condition. X can be

considered to be either 0 or 1, whichever produces a simpler logic circuit.

Example: Truth Table with Don’t Care Conditions

A B C Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 X

1 1 0 X

1 1 1 X

From the truth table, we have Y = Σ m(1, 3) + d(5, 6, 7).

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K-map Simplification with Don’t Care Conditions

Consider simplification of the K-map shown below:

The don’t care terms 5 and 7 are included in the quad cover since they help if greater simplification. The

don’t care term 6 does not help in simplification and is ignored. The simplified equation is

Example 2:

Obtain the simplified logic equation for the given K

The simplified logic equation is Y = A + C

Product-of-Sums Method

The solution from the product-of-sums method

below.

OR-AND network


with Don’t Care Conditions

map shown below:


don’t care term 6 does not help in simplification and is ignored. The simplified equation is

Obtain the simplified logic equation for the given K-map below:

Y = A + C.

sums method results in an OR-AND or NOR-NOR network


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don’t care term 6 does not help in simplification and is ignored. The simplified equation is Y = C.

NOR network as shown

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Sum term

A sum term is a disjunction of literals, where each literal is either a Boolean variable or its complement

Examples: A + B A’ + B + C’

Fundamental Sum or Maxterm

For a function of n variables, a sum term in which each of the

uncomplemented or complemented form) is called a

Fundamental Sums for Two inputs

Product-of-Sums (POS) Equation

Given the truth table, we identify the fundamental sums or Maxterms

get the Product-of-Sums (POS) equation

A

0

0

1

1

NOR-NOR network


A sum term is a disjunction of literals, where each literal is either a Boolean variable or its complement

A’ + B + C’ A

variables, a sum term in which each of the n variables appears once (in

uncomplemented or complemented form) is called a fundamental sum or Maxterm.

Given the truth table, we identify the fundamental sums or Maxterms. Then by ANDing these sums, we

equation. Note that the fundamental sum produces an

Inputs Fundamental sums

or Maxterms B

0 M0 = A + B

1 M1 = A + B’

0 M2 = A’ + B

1 M3 = A’ + B’


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A sum term is a disjunction of literals, where each literal is either a Boolean variable or its complement .

variables appears once (in

Then by ANDing these sums, we

produces an output 0.

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From the above truth table we have

In compact form Y = f(A, B, C) = πM(0, 1, 2)

The logic circuit is as shown below:

The expression can be further simplified. Consider K

expression as Y = A . B and it is realized by a simple AND gate as shown below:


Inputs Output

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

From the above truth table we have Y = (A + B).(A + B’).(A’ + B) = M0.M1.M2

M(0, 1, 2).

is as shown below:

OR-AND network

The expression can be further simplified. Consider K-map simplification. We obtain the simplified

expression as Y = A . B and it is realized by a simple AND gate as shown below:


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. We obtain the simplified

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Canonical Product-of-Sums Form

Consider Y = f(A, B) = (A + B).(A + B’).(A’ + B). It is in canonical POS form. If each sum term is a maxterm,

then the expression is said to be in a canonical product- of-sums form or standard POS form.

POS Simplification

Example:

Reduce the following function using Karnaugh map technique

f(A, B, C, D) = πM(0, 2, 4, 10, 11, 14, 15)

The K-map for the given logic function is drawn as shown below:

The simplified logic equation in POS form is Y = (A + B + D). (A + C + D). (A’ + C’).

Conversion between SOP and POS

SOP and POS occupy complementary locations in a truth table. One representation can be obtained by

the other by

1. Identifying complementary locations

2. Changing minterm to maxterm or reverse

3. Changing summation by product or reverse

Example:

Consider Y = f(A, B, C) = πM(0, 3, 6). The SOP equivalent is Y= Σm(1, 2, 4, 5, 7).

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Questions

1. Simplify the following logic expression using Karnaugh map method.

i) f(A,B,C,D) = ∑m (1, 2, 8, 9, 10, 12, 13, 14)

ii) f(P, Q, R, S) = ∑m (1, 2, 8, 9, 10, 12, 13, 14)

2. Using Karnaugh map simplify the following Boolean expression and give the implementation of the

same using: i) NAND gates only (SOP form) ii) NOR gates only (POS form)

f(A,B,C,D) = ∑m (0, 1, 2, 4, 5, 12, 14)+dc(8, 10).

3. Simplify the following logic equation using Karnaugh map and give the implementation of the

simplified expression:

f(A,B,C,D) = ∑m (7) + d(10, 11, 12, 13, 14, 15)

4. Simplify the following Boolean function by using K-map method in POS form:

f(A,B,C,D) = ∑m (0, 1, 2, 3, 4, 5, 7)

5. Simplify the following using K-map:

f(A,B,C,D) = A’B’C + AD + BD’ + CD’ + AC’ + A’B’

6. Simplify the following using K-map and design it by using NAND gates (use only four gates):

f = w’xz + w’yz + x’yz’ + wxy’z; d = wyz

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Objectives

• Use 5 – Variable Karnaugh Map and Entered Variable Map to simplify Boolean expressions

• Use Quine-McClusky tabular method for simplification of Boolean expressions having more than

4 variables


A given 5-variable minterm will have 5 adjacent terms. One way of drawing Karnaugh map for 5

variables is as shown below. The visual advantage of identifying the adjacent terms is not there.

Example:

The simplified expression is Y = B’D’ + BCDE + ABE’

Entered Variable Map

In entered variable map one of the input variables is placed inside Karnaugh map. This is done

separately noting how the input variable is related with output. This reduces the Karnaugh map size by

one degree. This technique is particularly useful for mapping problems with more than four input

variables.

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Unit – 2

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Example:

Consider the 3 - variable truth table as shown below. The output Y is rewritten in terms of variable C.

A B C Y Y

0 0 0 0 0

0 0 1 0

0 1 0 1 C’

0 1 1 0

1 0 0 0 0

1 0 1 0

1 1 0 1 1

1 1 1 1

The 3 – variable truth table reduces to 2 – variable truth table as shown below:

A B Y

0 0 0

0 1 C’

1 0 0

1 1 1

The 2 – variable Karnaugh map is drawn as shown below:

The Karnaugh map is now called an entered variable map. The simplification of entered variable map is

as illustrated next:

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The product term representing each group is obtained by including map entered variable in the group as

an additional ANDed term. Group 1 gives B.(C’) and group 2 gives AB.1. Therefore, the simplified

expression is obtained as Y = BC’ + AB.

Disadvantage of Karnaugh Map Simplifications

Karnaugh map depends on the user’s ability to identify patterns. It becomes difficult to adapt for

simplification of 5 or more variables.

Simplification by Quine-McClusky Method

Quine-McClusky method is a systematic approach for logic simplification. It was developed by

W. V. Quine and Edward J. McCluskey. It is functionally identical to Karnaugh map. It does not have the

limitation of number of variables. The tabular form makes it more efficient for use in computer

algorithms. It is also called as the tabulation method.

Main Steps

The 2 main steps are:

1. Find all prime implicants of the given Boolean equation.

2. Use the prime implicants in a prime implicant chart to find the essential prime

implicants and other prime implicants that are required to completely cover the given

equation.

Example 1:

Simplify the following function:

Y = f(A, B, C, D) = Σ m(0, 1, 2, 3, 10, 11, 12, 13, 14, 15)

Solution:

Step 1

We find all Prime Implicants.

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In stage 1 of this step, the minterms are put in to different groups depending on the number of 1’s they

have in their binary equivalents. In each group the minterms are ordered in increasing values of their

decimal equivalent.

Finding Number of 1’s

Minterms Binary

rep.

No.

of

1’s

Minterms Binary

rep.

No.

of

1’s

0 0000 0 11 1011 3

1 0001 1 12 1100 2

2 0010 1 13 1101 3

3 0011 2 14 1110 3

10 1010 2 15 1111 4

Stage 1

Stage 1

No. of

1’s

Minterm Binary Representation

0 0 0 0 0 0

1 1 0 0 0 1

2 0 0 1 0

2 3 0 0 1 1

10 1 0 1 0

12 1 1 0 0

3 11 1 0 1 1

13 1 1 0 1

14 1 1 1 0

4 15 1 1 1 1

In stage 2, we form pairs, i.e. compare minterms of group n and group n + 1 ( n varies from 0 to 3).

Where there is only one bit change in the binary representations, the corresponding variable is

eliminated using the adjacency theorem and in its position a dash ( - ) is written. After the stage 2 process the table is obtained as shown:

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Next we go to stage 3 and same process is repeated i.e. pair of pairs is formed. After the stage 3 process

we stop since further comparison is not possible. Next, we check off all minterms or group of minterms

that are covered by larger groups. The unchecked minterms are the prime implicants as shown below:

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Step 2.

We find essential prime implicants using the prime implicant chart. The chart is drawn as shown below.

Prime implicants are shown as rows and minterms as columns. An ‘X’ is placed to indicate the covering

of the minterm by the prime implicant. For example, minterms 0, 1, 2, and 3 are covered by prime

implicant A’B’.

Find the column that has a single ‘X’ and circle it. The associated prime implicant is an essential prime

implicant since it covers at least one minterm not covered by other prime implicants. An asterisk (*) is

placed to indicate that the prime implicant is essential. Then check off all the minterms covered by the

essential prime implicants as shown below:

Since all the minterms are not checked off, we have to find secondary essential prime implicants by

drawing a reduced prime implicant chart. The reduced chart is obtained by removing the essential

prime implicants that are already found and included in the solution and also removing the checked off

minterms.

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The reduced prime Implicant chart is as shown below:

Minterms

PIs

√ √

10 11

B’C X X

**AC X X

We note that column with single ‘X’ is not there. The complexity or cost of both the prime implicants

are same. So we select one of them as secondary essential prime implicants (say, AC). It covers all the

minterms. So we have the solution:

Y = A’B’ + AB + AC

Example 2:

Minimize f(A, B, C, D) = Σ (0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31).

Step 1: Say we have obtained the following prime implicants:

P1: BC’D’ P4: ABDE P7: ABC’D’ P10: A’B’C’E’

P2: C’D’E P5: BCDE P8: A’B’D’E P11: A’B’C’D’

P3: A’C’D’ P6: ABC’E P9: B’C’D’E

Step 2: Prime Implicant Chart

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The prime implicants P5, P7, and P10 are essential. They are included in the solution. They do not cover

all the minterms. So secondary essential prime implicants have to be found by using the reduced prime

implicant chart.

Reduced Prime Implicant Chart (Essential prime implicants removed)

1 8 9 24 25 27

P1

X X X X

P2 X

X

X

P3 X X X

P4

X

P6

X X

P7

X X

P9 X

P11 X

We are not able to find columns with single ‘X’. Now we find the dominance relations.

Column Dominance:

9 > 8

25 > 24

Row Dominance:

P1 > P7

P6 > P4

P2 > P9

P2 > P11

Prime Implicant Chart Reduction Steps:

1. All the dominating columns and dominated rows of a prime-implicant chart can be removed

without affecting the table for obtaining a minimal solution.

2. Dominating column is guaranteed to be covered by the row that covers its dominated column.

3. The columns of the dominated row are guaranteed to be covered by its dominating row.

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Finding Secondary Essential PIs

PI Chart after the dominating columns and the dominated rows are deleted:

Final Solution

Minterm 1 can be covered by P2 or P3. If we select P2, we have the solution:

Y = P1 + P2 + P5 + P6 + P8 + P10.

Questions

1. What are the drawbacks of Karnaugh map?

2. Define prime implicant and essential prime implicant. Find prime implicant and essential prime

implicants for the following function using Quine-McClusky method:

f(a, b, c, d) = ∑m(0, 2, 3, 6, 7, 8, 10 , 12, 13)

3. Find the prime implicants for the following Boolean expressions using Quine Mc Clusky's method.

i. f(w, x, y, z) = ∑m(1, 3, 6, 7, 8, 9, 10, 12, 13, 14)

ii. f(a, b, c, d) = ∑m(1, 2, 8, 9, 10, 12, 13, 14)

ii. f(A, B, C, D) = ∑m(1, 3, 6, 7, 8, 9, 10, 12, 14, 15) + d(11, 13)

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Objectives

• Review of combinational logic circuit design methods

• Analyze hazards in logic circuit and provide solution for them

Problem Solving with Multiple Methods

We can simplify a given Boolean expression using one of following different methods:

• Boolean algebra

• Karnaugh map

• Entered variable map

• Quine-McClusky method

Example:

Get a minimized expression for

Y = f (A, B, C) = Σ m(0, 1, 3, 5)

= A’B’C’ + A’B’C + A’BC + AB’C

Method – 1: Using Boolean Algebra

Y = A’B’C’ + A’B’C + A’BC + AB’C

= (A’B’C’ + A’B’C) + (A’BC + A’B’C) + (AB’C + A’B’C)

= A’B’(C’ + C) + A’C(B’ + B) + B’C(A + A’)

= A’B’.1 + A’C.1 + B’C.1

= A’B’+ A’C + B’C

(using Boolean Axioms: X = X + X and X + X’ =1)

Unit – 2

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Method – 2: Karnaugh Map

The truth table for the given expression:

A B C Y

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0

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Method – 3: Entered Variable Map

A B C Y Y

0 0 0 1 1

0 0 1 1

0 1 0 0 C

0 1 1 1

1 0 0 0 C

1 0 1 1

1 1 0 0 0

1 1 1 0

3 – Variable truth table reduces to 2 – variable truth table.

A B Y

0 0 1

0 1 C

1 0 C

1 1 0

The entered variable map is obtained as shown below:

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Simplification of EVM

Method – 4: Quine McCluskey Method

Y = f (A, B, C) = Σ m(0, 1, 3, 5)

Minterms

Determination of Prime Implicants


4: Quine McCluskey Method

m(0, 1, 3, 5)

Minterms Binary rep. No. of 1’s

0 000 0

1 001 1

3 011 2

5 101 2


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Prime Implicant Chart

Hazards and Hazard Covers

Simplification techniques give minimal expressions for a logic equation

realized using minimum hardware.

prefer to include more terms in the simplified equation

instantaneously. There is a finite propagation delay.

hazards.

Hazard covers are additional terms in a logic equation that prevents hazards

logic circuits hazard may go unnoticed but in sequential logic circuit


Hazards and Hazard Covers

Simplification techniques give minimal expressions for a logic equation. Simplified equations can be

realized using minimum hardware. But to overcome some practical problems, in certain cases we may

prefer to include more terms in the simplified equation. Practical logic circuits do not generate outputs

e is a finite propagation delay. This propagation delay gives rise to several

Hazard covers are additional terms in a logic equation that prevents hazards.

may go unnoticed but in sequential logic circuits it may cause major malfunctioning


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Simplified equations can be

But to overcome some practical problems, in certain cases we may

Practical logic circuits do not generate outputs

This propagation delay gives rise to several

. For combinational

s it may cause major malfunctioning.

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Types of Hazards

Static Hazard

A static hazard exists if an output signal is supposed to remain at a particular logic value when an input

variable changes its value, but instead the signal undergoes a momentary chan

Static-1 Hazard

This type of hazard occurs when Y = A + A’ type of situation

combination of other inputs and A makes a transition 1

An A + A’ condition should always generate logic 1 at

A

1

0

Consider a simple logic circuit as shown:

The NOT gate output takes finite time to become logic 1 following 1

OR gate output goes to logic 0 for a small duration which is unwanted

The width of this logic 0 output is in nanoseconds and is called a glitch



variable changes its value, but instead the signal undergoes a momentary change in its required value

This type of hazard occurs when Y = A + A’ type of situation appears for a logic circuit for certain

combination of other inputs and A makes a transition 1 → 0.

An A + A’ condition should always generate logic 1 at the output, i. e. static -1

A A’ Y = A + A’

1 0 1 + 0 = 1

0 1 0 + 1 = 1


The NOT gate output takes finite time to become logic 1 following 1 → 0 transition at the input A

for a small duration which is unwanted.

A A’ Y = A + A’

1 0 1 + 0 = 1

0 0 0 + 0 = 0

0 1 0 + 1 = 1

The width of this logic 0 output is in nanoseconds and is called a glitch as shown in the figure next.


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ge in its required value.

ppears for a logic circuit for certain

→ 0 transition at the input A. The

as shown in the figure next.

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Static-1 Hazard Cover

Consider an example Y = AC + BC’.

Consider input A = 1, B = 1, and C makes a transition 1

has static-1 hazard.

Consider the Karnaugh map simplification


. Corresponding logic circuit is as shown:

Consider input A = 1, B = 1, and C makes a transition 1 → 0. The output has a glitch and hence the circuit

Consider the Karnaugh map simplification.

Glitch


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and hence the circuit

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The additional term AB ensures Y = 1 for A = 1 and B = 1 and a 1

output. The circuit free from static-

Static-0 Hazard

This type of hazard occurs when Y = A . A’ type of situation appears for a logic c

combination of other inputs and A makes a transition 0

logic 0 at the output, i. e. static-0.


The NOT gate output takes finite time to become logic 0 following 0

AND gate output goes to logic 1 for a s

A

0

1

1

The width of this logic 1 output is in nanoseconds and is called a glitch


term AB ensures Y = 1 for A = 1 and B = 1 and a 1 → 0 transition at C does not affect the

-1 hazard is as shown below:

This type of hazard occurs when Y = A . A’ type of situation appears for a logic circuit for

ombination of other inputs and A makes a transition 0 → 1. An A . A’ condition should always generate

A A’ Y = A . A’

0 1 0 . 1 = 0

1 0 1 . 0 = 0


The NOT gate output takes finite time to become logic 0 following 0 → 1 transition at the input A

AND gate output goes to logic 1 for a small duration which is unwanted.

A’ Y = A . A’

1 0 . 1 = 0

1 1. 1 = 1

0 1 . 0 = 0

logic 1 output is in nanoseconds and is called a glitch as shown in the figure next.


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→ 0 transition at C does not affect the

ircuit for certain

An A . A’ condition should always generate

→ 1 transition at the input A. The

as shown in the figure next.

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Static-0 Hazard Cover

Consider an example Y = (B + C).(A + C’)

Consider the Karnaugh map simplification

The additional term (A + B) ensures Y = 0 for A = 0, B = 0 and a 0

output. The hazard free circuit is as shown next:


Consider an example Y = (B + C).(A + C’). Corresponding logic circuit is as shown:

Consider the Karnaugh map simplification.

(A + B) ensures Y = 0 for A = 0, B = 0 and a 0 → 1 transition at C does not affect the

. The hazard free circuit is as shown next:

Glitch


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→ 1 transition at C does not affect the

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Dynamic Hazard

Dynamic hazard causes glitches on 0

transition is required, the output makes multiple transitions

circuit, where there exists multiple paths for a given signal change to propagate along

Dynamic hazards are encountered in multi

avoided simply by using two-level circuits and ensuring that there are no static hazards

Questions

1. Explain static-0 and static-1 hazard with example.

2. How do you eliminate static hazard? G

3. What is dynamic hazard? Where do you encounter dynamic hazards?


Dynamic hazard causes glitches on 0 → 1 or 1 → 0 transitions of an output signal

transition is required, the output makes multiple transitions. It is caused by the structure of the logic

circuit, where there exists multiple paths for a given signal change to propagate along.

Dynamic hazards are encountered in multi-level circuits. They are not easy to detect

level circuits and ensuring that there are no static hazards

1 hazard with example.

2. How do you eliminate static hazard? Give an example.

3. What is dynamic hazard? Where do you encounter dynamic hazards?


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→ 1 or 1 → 0 transitions of an output signal. When only one

aused by the structure of the logic

.

They are not easy to detect. They can be

level circuits and ensuring that there are no static hazards.

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unit – 2 combinational logic circuits

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