unit 07
TRANSCRIPT
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Department of Communication Engineering, NCTU 1
Unit 7 Multi-Level Gate Circuits/NAND and NOR Gates
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Department of Communication Engineering, NCTU 2
7.1 Multi-Level Gate Circuits
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Department of Communication Engineering, NCTU 3
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
The maximum number of gates cascaded in seriesbetween a circuit input and the output is referred to as thenumber of levels of gates ANR-OR circuit A level of AND gates followed by a
OR at the output OR-AND circuit A level of OR gates followed by a
AND at the output OR-AND-OR circuit A level of OR gates followed by a
level of AND gates followed byOR gate at the output
A function written in SOP form or in POS formcorresponds to a two-level gate circuit
Inverters which are connected directly to input variableswill not be counted when determining the # of levels
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Example: A four-level realization with 6 gates and 13gate inputs
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Another realization of 3 levels of gates. There are sixgates and 19 gate inputs in total
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Example: Find a circuit of AND and OR gates to realize
By Karnaugh map, f = a’c’d + bc’d + bcd’+ acd’(7-1)
( , , , ) (1,5,6,10,13,14)f a b c d m
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Factoring (7-1) yields f=c'd(a'+b)+cd'(a+b) (7-2)
Both realizations use 5 gates, but the later one has fewerinputs with on more level of gate delays
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
An alternative realization in POS form: obtained from the0’s on the Karnaugh map
f'=c'd'+ab'c'+cd+a'b'c (7-3)f=(c+d)(a'+b+c)(c'+d')(a+b+c') (7-4)
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Partially multiplying out (7-4) using (X+Y)(X+Z)=X+YZ :f =[c+d(a'+b)][c'+d'(a+b)] (7-5)=(c+a'd+bd)(c'+ad'+bd') (7-6)
Eq. (7-6) leads to a 3-level AND-OR-AND circuit
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Summaries: If an expression for f’has n-levels, the complement of that
expression is an n-level expression of f To realize f as an n-level circuit with an AND-gate output,
one procedure is to find an n-level expression for f’with anOR operation at the output and then complement theexpression for f’
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7.2 NAND and NOR Gates
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
NAND and NOR gates are frequently used because theyare generally faster and use fewer components than ANDor OR gates
Any logic function can be implemented using onlyNAND or only NOR gates
An n-input NAND gate is
1 2 1 2( )n nF X X X X X X
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Similarly, an n-input NOR gate is
A set of function is said to be functionally complete if anyBoolean function can be expressed in terms of this set ofoperations, e.g. AND, OR and NOT
Any set of logic gates which can realize AND, OR, andNOT is also functionally complete
1 2 1 2( )n nF X X X X X X
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
E.g. AND and NOT form a functionally complete set ofgates, since
NAND is also functionally complete
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7.3 Design of Two-Level CircuitsUsing NAND and NOR Gates
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
A two-level circuit composed of AND and OR gates iseasily converted to a circuit composed of NAND gates orNOR gates. E.g. converting from a minimum SOP
(7-13):AND-OR(7-14):NAND-NAND(7-15):OR-NAND(7-16):NOR-OR
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Obtaining a two-level circuit containing only NOR gatesshould start with the minimum POS for F, instead of SOP
E.g.
(7-18):OR-AND(7-19):NOR-NOR(7-20):AND-NOR(7-21):NAND-AND
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Department of Communication Engineering, NCTU 19
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 20
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Two of the most commonly used circuits are the NAND-NAND and the NOR-NOR
Procedure for designing a min 2-level NAND-NANDcircuit Find a minimum SOP for F Draw the corresponding two-level AND-OR circuit Replacing all gates with NAND gates
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Procedure for designing a min 2-level NOR-NOR circuit Find a minimum POS for F Draw the corresponding two-level OR-AND circuit Replace all gates with NOR gates
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7.4 Design of Multi-Level NAND-and NOR-Gate Circuits
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Department of Communication Engineering, NCTU 23
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
The following procedure may be used to design multi-level NAND-gate circuits Simplify the switching function to be realized Design a multi-level circuit of AND and OR gates. The output gate must be a OR gate AND-gate outputs cannot be used as AND-gate inputs; OR-
gate outputs cannot be used as OR-gates inputs Replace all gates with NAND gates
The procedure for the design of multi-level NOR-gatecircuits is exactly the same as for NAND-gate circuitsexcept that the output gate of the circuit must be an ANDgate, and all gates are replaced with NOR gates
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
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7.5 Circuit Conversion UsingAlternative Gate Symbols
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Alternative representations for an inverter
Alternative representations for AND, OR, NAND andNOR gates
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
The procedure for converting AND-OR circuit to aNAND or NOR circuit Convert all AND gates to NAND gates by adding an
inversion bubble at the output Convert all OR gates to NAND gates by adding inversion
bubbles at the inputs Whenever an inverted output drives an inverted input, these
two inversions cancel Whenever a noninverted gate output drives an inverted gate
input or vice versa, insert an inverter so that the bubble willcancel
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Department of Communication Engineering, NCTU 29
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Example
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7.6 Design of Two-Level, Multiple-Output Circuits
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Department of Communication Engineering, NCTU 32
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Solution of digital design problems often requires therealization of several functions of the same variables. Theuse of some gates in common between two or morefunctions sometimes leads to a more economical circuit
E.g. we have
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
The individual realizations to them are
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Observe that the term ACD is necessary for therealization of F1 and that A’CD is necessary for F3. Ifreplacing CD in F2 by A’CD + ACD, the realization ofCD is unnecessary
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Department of Communication Engineering, NCTU 35
Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
In realizing multiple-output circuits, the use of aminimum sum of prime implicants for each function doesnot necessarily lead to a minimum cost solution
When designing multiple-output circuits, try to minimumthe total number of gates required
E.g.
1
2
3
(2,3,5,7,8,9,10,11,13,15)
(2,3,5,6,7,10,11,14,15)
(6,7,8,9,13,14,15)
f m
f m
f m
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
The corresponding Karnaugh maps are
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
By inspection, we can see that a’bd from f2, abd from f3 and ab’c’from f3 can be used in f1.
Replacing bd with a’bd + abd, the gate needed to realize bdcan be eliminated.
m10 and m11 in f1 are already covered by b’c, and ab’c’fromf3 can be used to cover m8 and m9, thus ab’being eliminated
The minimum solution is therefore
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Determination of essential prime implicants for multiple-output realization The prime implicants essential to an individual function
may not be essential to the multiple-output realization bd is an essential prime implicant of f1 but not of all f’s
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
When searching for a prime implicant to an multiple-outputrealization, Check each 1 which do not appear on the other function maps
Example 1
c’d is essential to f1, bd’is essential to f2
abd is not essential since it appears on both maps
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Logic Design Unit 7 Multi-Level Gate Circuits Sau-Hsuan Wu
Example 2
a’d’and a’bc’are essential to f1
bd’and a’b’c are essential to f2