tutorial(1st assignment)

Middle East Technical UniversityElectrical and Electronics Engineering Department

EE413 – Introduction to VLSI DesignEE413 – Introduction to VLSI Design

TutorialsTutorials

METU MEMSVLSI Research Group

Last updated on 20091028 1

TTABLEABLE OFOF C CONTENTSONTENTS

1. Using PC Laboratory...................................................................................................................................3

1.1. Introduction..........................................................................................................................................3

1.2. Running Cadence..................................................................................................................................3

1.2.1. Initializing Cadence Environment.....................................................................................................................3

1.2.2. Running Cadence ..............................................................................................................................................4

1.2.3. How to Log out?................................................................................................................................................4

2. Schematic Entry of a CMOS Inverter.......................................................................................................5

2.1. Create a New Library...........................................................................................................................5

2.2. Schematics of a CMOS Inverter...........................................................................................................6

3. Transient Simulation of Schematics...........................................................................................................9

4. Basics of Layout Drawing.........................................................................................................................12

4.1. What is LAYOUT?.............................................................................................................................12

4.2. CMOS Process and Layout Drawing Step by Step............................................................................12

4.2.1. Step 1 – Active Regions and Wells.................................................................................................................12

4.2.2. Step 2 – Polysilicon.........................................................................................................................................13

4.2.3. Step 3 – N+ and P+ Diffusion..........................................................................................................................13

4.2.4. Step 4 Contacts..............................................................................................................................................13

4.2.5. Step 5 – Metal Deposition................................................................................................................................14

4.2.6. Final View........................................................................................................................................................14

5. Layout Drawing Using Cadence...............................................................................................................15

5.1. Design Rules.......................................................................................................................................15

5.1.1. Layers...............................................................................................................................................................15

5.1.2. Design Rules Overview...................................................................................................................................15

5.2. Layout of the Inverter.........................................................................................................................17

6. Layout versus Schematic Check (LVS)....................................................................................................24

7. Simulation of the Inverter Layout............................................................................................................28

8. A Sample Design Flow...............................................................................................................................29


1.1. UUSINGSING PC L PC LABORATORYABORATORY

1.1. IntroductionThere are 9 personal computers in this laboratory. Instead of Microsoft Windows OS, Ubuntu is installed on computers. So you will be familiar with Linux environment. The reason for using a Linux OS is it simplifies the procedure for running the Cadence. Different from previous years, Cadence will run on these computers instead of a terminal.

1.2. Running CadenceCadence is one of the most widely used IC design software all over the world. It contains many subprograms each of which is responsible from one step in IC design flow. In the content of this course, you will learn lowlevel (transistor level) design tools of the cadence.

All the users have a user name and a password. Do change your password as soon as possible, and prefer complex passwords containing both letters (with different caps) and numbers, and also punctuations. To change your password open a terminal via Applications Accessories Terminal. In terminal use passwd→ → command. Enter your old password and then enter your new password twice.

In order to run Cadence on UNIX machines, follow the following guidelines:

1.2.1. Initializing Cadence EnvironmentWith the steps in the previous part, you are connected to the server and ready to run Cadence. In order to run Cadence for the first time, you need to initialize your working directory. For this purpose follow the next steps:

0. Turn on the computer if it is not, and log into Ubuntu by using your user name and password.

1. Open a terminal: Applications Accessories Terminal→ →

2. mkdir Cadence

This will make a directory named Cadence.

3. cd Cadence

Enter newly created Cadence directory.

4. ln s /Cadence/DesignKits/XFAB_XC06/cadence/env/bin/tkit .

This command generates a link to the script file required to run Cadence.

5. ./tkit m fb tech xc06

Run cadence for the first time, choose xc06 as the technology, which is XFab 0.6u technology with 2 metal and 1 poly layers.

So, you have a running cadence at the moment. Remember that, the previous steps are for initializing the cadence for the first time, and they should be done once only. Now close cadence by File>Exit.

1.2.2. Running Cadence You have initialized cadence in the previous part. After the first run, you need to do the following things to run cadence:

0. Open a terminal


1. cd Cadence

2. ./tkit m fb &

That is all. Cadence should be running.

1.2.3. How to Log out?When you log out, make sure that no programs are running. If cadence is running for example, close it. Then click on your name at upper right of the screen and click “Log out...”. After this, the login screen should come back. So you logged out from Ubuntu, and it waits for you to login again. Now you can leave.


2.2. SSCHEMATICCHEMATIC E ENTRYNTRY OFOF AA CMOS I CMOS INVERTERNVERTER

In this tutorial, you will start using Cadence and design your first CMOS gate: an inverter. Believe or not, working on the first inverter is the most important part of the overall laboratory work. You will learn much. Do not pass the steps unless you have understood what you are doing. If you get some problem, do not hesitate to ask to your assistant. Do not forget that, you have to learn every step in this tutorial.

2.1. Create a New LibraryBefore starting to your first design, you need to create a library, which will contain all the circuits that you will implement during this laboratory.

1. Start cadence.

2. Open library manager window by Tools>Library Manager... on icfb window.

3. On library manager window, choose File>New>Library.

4. Write down "EE413" to the name of the library as seen on the figure.

5. In save destination, delete /mnt/maxell so that destination begins with /homes/ee413. Then press OK.

6. Each library should be attached to a technology library (or technology file). A technology library contains required information about the technology you are using, like DRCExtractionLVS rules, contact dimensions, etc (you will understand these later :). On the newly appeared window, click on "Attach to an existing techfile" radio button and click OK.

7. Again, a new window will appear to choose the technology library. Choose "TECH_XC06" from the pulldown menu. This is the technology library for XFab 0.6 u process.


2.2. Schematics of a CMOS InverterWe got a new library. Now, we will go on by making a new cell.

1. Click on library "EE413" you have added previously. On the library manager, there are 3 columns as you see. Left most one contains the libraries, the middle one contains the cellviews in the selected library, and the column on the right contains the views of the selected cellview. Libraries are composed of cellviews (which are circuits that you will implement, like inverter, nand, etc.). Each cellview should have different name in a library. Each cellview contains views like schematic, symbol, and layout. These are predefined names and you will learn what they are by following the tutorials.

2. At the moment, there is no cellview in the "EE413" library yet. Click on File –> New –> Cell View in order to create one. Write "inverter" to the Cell Name. Although they are default, be sure that View Name is "schematic", and Tool is "ComposerSchematic". This means that you will use Composer to create your schematic view. Click OK.

3. Virtuoso Schematic Editing window should be opened. As you see, you will work with a black background. You should know that, this schematic tool is one of the best that you will use in the future.

There is a tool box on the left and a pulldown menu on the top of the window. Most of the commands in the menus have shortkeys and you are expected to learn the required shortkeys at least the ones mentioned in the tutorials.

4. Now we will add a transistor. Click on Add>Instance from the menu. The shortcut key for this command is "i". In other words, simply pressing "i" key is same as clicking Add>Instance.

5. "Add Instance" window will be opened like figure below. Write "PRIMLIB" to Library and "nmos4" to Cell. View will be "Symbol" by default, check it. You may browse the libraries using Browse button also. Width, length and other properties of the transistor can be changed in this window, or you can change them later.

Focus to the schematic editor and insert one NMOS transistor. Do the same thing for "pmos4" cell and insert one PMOS transistor. Do not forget that you are making an inverter, so put PMOS transistor to top for better understanding.


2

6. Now, you will add pins of the circuit, which are connections to the outer world, like the input and the output connections of the circuit. Click on Add>Pin or simply press "p" to add the pins of the circuit. You will add 2 pins, A and Q, which will be the input and the output respectively. Do not forget to choose direction of A as input and direction of B as output.

7. Now, you will add vdd and gnd of the circuit. Similar to step 5, add "vdd" and "gnd" cells from "PRIMLIB" library.

8. One point should be noted here. You can zoom in or out by using the buttons on the toolbar on the left, or using Window>Zoom. "f" autozooms the current design. Or you may clickanddrag using 3rd button (right button) of the mouse, which zooms the drawn box. Try and see. Whenever you have zoomed to a wrong place, press “f” in order to fit the circuit.

9. Now, you will draw the connections, or simply wires of the circuit. Click on Add>Wire(narrow) or press "w". Click at the start and end points of the wires. Do not forget to connect bulk connections of transistor as seen in the figure.

10. Your circuit is almost completed. Click on Design>Check and Save in order to check and save whether there is any unconnected pin or not. If you get some warning messages, check the yellow markers. If there is no problem, you will not get any warning or error.

Generating Symbol from Schematics...

11. Every cell should have a symbol view in order to be used in other circuits. Click on Design>Create Cell View>From CellView. Be sure that "To View Name" is "symbol" and "Tool/Data Type" is "ComposerSymbol" as similar to the following figure. Click OK.

12. You will get "Symbol Generation Options" window. Click OK with default settings.

13. A new window will appear showing your new boxshaped symbol view. Inputs are on the left and outputs are on the right. Although cadence does not care, it is not very proper to use this boxshaped symbol as inverter symbol. One can draw his/her own symbol by using "Add>Symbol>Line" and "Circle" and other tools. Although it is not difficult for inverter, it will not be easy to draw proper symbols for the circuits you will design in the future, and you don't want to loose time with drawing boxes, etc.

14. There is a “D_CELLS” library. Click to right mouse button on "INX1" cell's "symbol" view and choose "Copy". A new dialog window will appear in order to choose the source and destination of copying process. Fill "To" part as “EE413”, “inverter” and “symbol” as library, cell, and view. Click on OK. If a new dialog box appears that there is already a symbol view at the destination, click on “Overwrite all” and then “OK” buttons.


15. Check the inverter symbol in EE413 library whether the copy is done correctly or not. The symbol should be a traditional inverter.

16. That's all. You designed the schematics and copied the symbol of the inverter. You are ready to go on with the simulations of this schematics. Before this, let me add a few notes here.

NOTES

1. You can see the properties of transistors or any other components by pressing "q" or clicking on Edit>Properties>Objects, after choosing the object (by clicking on it). When an object is selected, its borders become visible. For the transistors, it is possible change the aspect ratios by changing "Width" and "Length", which are "0.8u" and "0.6u" by default. "u" is used for micro and "m" is used for "mili" here.

2. You can move objects by "m" or "Edit>Move". Copy and deleting objects are similar also. See the menus and shortcuts.

3. It is possible to change the location or shape of the wires by "move (m)" also.


3.3. TTRANSIENTRANSIENT S SIMULATIONIMULATION OFOF S SCHEMATICSCHEMATICS

In the previous tutorials, you have designed the schematics of a CMOS inverter and its symbol view. In this one, you will simulate the schematics and observe its characteristics.

In order to simulate a circuit, you need to define the inputoutput, and the vddgnd. For this purpose, we will generate another cell.

1. Make a new cell "invsim" in "EE413" library with "schematic" view, using File>New>CellView on the library manager window.

2. Add the following components and draw the circuit in the figure.

Library Cell Name

EE413 inverter

PRIMLIB vdd

PRIMLIB gnd

analogLib vdc

analogLib vpulse

analogLib cap

3. You have added your design into this schematic with a few components. Here, "vdc" will be used to apply VDD voltage. "vpulse" will be used for applying a square wave to the input of the inverter and "cap" is capacitive load.

4. Now click on "vdc" and press "q". Remember that "q" is for reviewing and changing the properties of the components. Write "5" to "DC Voltage".

5. Change these properties of "vpulse". Remember that "n" stands for "nano", and "u" stands for "micro".

Property New Value

Voltage 1 0

Voltage 2 5

Delay Time 0

Rise Time 1n

Fall Time 1n

Pulse Width 10u

Pulse Period 20u


Vpulse is used to generate pulsed signals with 2 voltage levels, Voltage1 and Voltage2. The delay time at the beginning of the simulation is determined by Delay Time. Also rise time, fall time, pulse width and pulse period are determined by these properties.

6. Change the capacitance of "cap" to "0.1pF".

7. This is the last view of the circuit. Now, press “check and save” which is the first menu (a check symbol on it) in the tool box on the left of the window.

8. Now, click on "Tools>Analog Environment" in order to run analog simulator.

9. Click on Analyses>Choose. "tran" is chosen as the default analysis time. Write 50u to the "Stop Time". You have programmed the simulator to simulate the transient response of the circuit for 50u seconds. Click OK.

10. Now, it is time to determine the nodes that will be observed. Click on Outputs>To Be Plotted>Select on Schematics. This will let you choose the nodes to be observed. Focus the schematics editor and click on the wires at the input and output of the inverter.

There are 2 types of signals to be observed after the simulation: voltage and current. If you click on wire, you select that wire's voltage as the observed signal. If you click on the node like the input of the inverter, you select the current of that node as the observed signal. You see a circle on that node. You will work on voltage here.

11. Check and Save the schematics.

12. There are 2 waveform viewers, WaveScan and AWD. WaveScan is more advanced and default waveform viewer for the current Cadence version. However, we will prefer AWD since the user interface is simpler and more clear. On the Analog Design Environment dialog, click on Session>Options and choose AWD as the “Waveform Tool”. and click on "Simulation>Run" to


start the simulation. After the simulation is completed, a waveform window will be opened. Do not forget to "Check and Save" the schematics before running the simulation.

13. You should see a waveform similar to the figure on the left. Two different colors represent the input and output of the inverter. As seen, the input signal is inverted, so the operation of the circuit is correct. In order to see these signals separately, click on "Axes>To Strip" at waveform window. You should see a similar waveform to the figure on the right.

14. Which one is input and which one is output? Well, if you click on the wires on the schematics and press "q", you will see the properties of them. You can see the names of the wires there.

15. Now, change these parameters and simulate again.

Pulse Width of vpulse 100n

Pulse Period of vpulse 200n

Capacitance of cap 1p

Simulation time 1u

16. You should find a waveform like this. So, we applied a higher frequency input signal and increased the load. This results in larger rise and fall times at the output of the inverter.

17. There are 2 markers on the waveform window. Press on "a" or "b" in order to locate them. You can measure whatever you want using these markers.

You are done with the simulation of the inverter schematics.


4.4. BBASICSASICS OFOF L LAYOUTAYOUT D DRAWINGRAWING

Till now, you designed your circuit and simulated it in the virtual environment. In order to convert your design to real world, you need to draw the layout of it. Layout drawing is not as easy as drawing wires in the schematics because you need considering the real (physical) structure of the circuit. Do not forget that, layout drawing is quite important and it is a job title in the VLSI design centers.

This tutorial is quite important. Although all the steps here will be lectured by your assistant, try to understand by yourself first in order to gain time.

4.1. What is LAYOUT?Layout is the drawings of masks used during the fabrication of the CMOS chips. Masks are kinds of filters used to shape various layers. Each layer in CMOS fabrication, like Polysilicon layer or metal layer, are shaped with a different mask. Considering our purpose as the designer, we have the ability to change very restricted number of variables during design. For instance we cannot change the thickness of the oxide layer in the gate, but we can change the width of the gate. During layout drawing, we will consider only the width and length of a metal layer, not the thickness.

4.2. CMOS Process and Layout Drawing Step by StepIn this part, we will consider the steps of layout drawing of a CMOS inverter seen in the figure on the right. Do not forget that, the CMOS process steps are much more complex than the ones we will consider in this part. We are skipping many steps since we do not care much about them as the designer. At each step, the physical structure and the layout corresponding to this physical structure are given, and then the process is explained.

4.2.1. Step 1 – Active Regions and Wells

Let's start the CMOS process flow. We have a ptype substrate with single well technology, which means that NMOS transistors are implemented on ptype substrate, and PMOS transistors are implemented on NWELLs. Nwells are the ntype doped regions as seen in the figure above. Normally, front sides of the wafers are initially covered with very thick SiO2 layer (or Si3N4 layer) except the regions where some active elements, like the transistors, will be implemented. A mask is used to shape these openings, which are called as Active Regions. And one mask is used to shape the Nwell region. So two layers are drawn in the layout.


Active regions NWELL

4.2.2. Step 2 – Polysilicon

Next step is to grow and shape polysilicon layer, which will form the gate of the transistor. For this purpose, we need to draw one mask only, which is colored as red.

4.2.3. Step 3 – N+ and P+ Diffusion

In this step, n+ and p+ regions will be doped. Doping is done on entire wafer surface. Since SiO2 and PolySilicon do not pass dopands (or impurities) to the substrate, these regions are not doped. First, a mask is used to determine the regions to be doped with p+ impurities. After p+ doping, the rest of the surface is doped by n+ dopands. So only one mask is used.

One important point should be stated here. Nwell regions should be biased to high potential and psubstrate should be biased to lowest potential in order to minimize the leakage current on the diode formed by Nwell and psubstrate. For this purpose, a structure like the figure above is used, where the Nwell is biased with the same potential to the p+ region on the left. Note that, contact to the Nwell should be n+ in order to decrease schottky effect. See the p+ doping region mask on the right.

4.2.4. Step 4 Contacts

As the next step, the entire wafer surface is again covered by a thick oxide layer in order to prevent the shorts between the substrate and metal layer deposited in the next steps. In order to take connection to the substrate, one should use contacts, which are openings in the oxide layer. There are 3 different contacts and we will learn those later on. This contact is the first one and it connects the substrate to the metal layer (metal layer is not shown here, it will be grown in the next step).


Polysilicon

N+ doping N+ dopingP+ doping

Contacts

Oxide layer is grown to the whole wafer surface and then the contacts are etched away. So only contact openings should be masked as seen on the right.

4.2.5. Step 5 – Metal Deposition

We are almost done with the process. The metal layer is grown and shaped in this step. Note that, the metals where a contact exists touches to the substrate.

4.2.6. Final View

This is it. The process is completed and our layout is ready. As you see, layout is somehow similar to the top view of a chip. Make sure that you understood every step here. Do not hesitate to ask questions, this tutorial is quite important.

Remember the definition of the layout stated at the beginning of the tutorial. It is combination of masks used during the process of the chip. So as the designer, you give the shapes of the layers that you want, and the process engineer produces the corresponding chip for you. As the designer point of view, you do not really care about the thickness of the layers, but you care only the shape of the layers. So you are in a 2D world.


METAL

5.5. LLAYOUTAYOUT D DRAWINGRAWING U USINGSING C CADENCEADENCE

In the previous part, layout drawing basics are given. In this tutorial, the layout will be drawn using Cadence. At the end of the tutorial the design will be checked in order to verify the physical structure of the drawn layout.

5.1. Design RulesIn this laboratory, XFab 0.6 µm, 2 Metal 2 Poly NWELL process will be used (xc06). Each technology has its own layout drawing design rules, and they should be satisfied for successful production. Design Rule Check (DRC) tools are used to determine whether the design rules are satisfied or not.

The following parts summarizes the short descriptions of the layers firstly, and then gives the most important design rules. The details can be obtained from \\battal\413\dr_xc06.pdf.

5.1.1. LayersThere are a number of layers to be used in the layout view. Most of these layers and abbreviated names are summarized below:

NWELL represents nwell

DIFF represents "active" layer, active layers are regions on which transistors can be grown

POLY1 represents the gatepoly layer, which is used for constructing gates of transistors, it is also used as a conductor

PIMP represents p+ doping region

NIMP represents n+ doping region

CONT represents openings in oxide, which are used to get contacts between different layers like activemetal, polymetal

MET1 represents the first metal layer which is the main conducting path for routing

MET2 represents the second metal layer which is the alternative conducting path for routing. Since there are two metal layers, and they are isolated with oxide, two different conduction paths routed with different metals can cross over each other.

VIA represents an opening in oxide between metal1 and metal2, hence connecting metal1 and metal2.

5.1.2. Design Rules OverviewThe table below shows the design rules for various layers. Minimum width shows the minimum producible width of the layers. Spacing and notch similarly show the minimum spacing and notch spaces of the layers.


Layer Min. Width (µm) Spacing (µm) Notch (µm)

NWELL 4 4.8 4.8

DIFF0.6

(1.4 in the transistor)

1.2 1.2

POLY1 0.6 0.8 0.8

CONT 0.6 (fixed) 0.6

MET1 0.9 0.8 0.8

MET2 0.9 0.8 0.8

VIA 0.7 (fixed) 0.6

Further design rules are stated below which are required for drawing a transistor. At the moment, you may not understand all of the rules here. You will get all of these rules while drawing the layout of the inverter.

1. Minimum GATE length 0.6u

2. Minimum POLY1 extension of GATE 0.6u

3. Minimum ACTIVE POLY1 spacing (same transistor) 0.3u

4. Minimum GATE width 1.4u

5. Minimum PPLUS extension of ACTIVE 0.4u

6. Minimum NTUB extension of ACTIVE 1.8u

7. Minimum DIFFUSION CONTACT to GATE spacing 0.5u

8. Minimum ACTIVE extension of DIFFUSION CONTACT 0.4u

9. Minimum BULK CONTACT to PPLUS spacing 0.8u

10. Minimum MET1 extension of CONTACT 0.3u

11. CONTACT crossing VIA is not allowed

12. VIA crossing POLY1 edge is not allowed

The figure on the right illustrates the design rules. The number in the parenthesis refers to the design rule above.

You may not understand the meaning of this figure at the moment. Do not worry, you will understand while going through the steps in the next part.

Come back to this figure after you have completed the whole tutorial.


MinimumWidth

MinimumSpacing

Notch

5 2.21.4(4)

1.2

0.6

0.6(1)

1.5

0.3 (3)

1.8 (6)

POLY1

NWELL

PIMP

DIFFMET1

CONT

0.6(2)

0.5(7) 0.4

(8)

0.3(10)

5.2. Layout of the InverterNow we can start drawing the layout of the inverter. Open Library Manager by Tools>Library Manager on icfb window.

1. First create a new cell view for the inverter. Select File>New>Cell View, and select "Virtuoso" as the tool, also make sure that library name is "EE413" and cell name is "inverter". Click OK.

2. Two new windows will appear. One is named as "LSW" and the other one is the layout window. First of all, focus on layout editor and click on Options>Display. Make sure that “X Snap Spacing” and “Y Snap Spacing” are both 0.05. Then Options>Layout Editor, and uncheck Gravity on.

3. LSW is a palette from which you can select the mask layer you want to draw with. At the moment it lists the layers defined in TECH_XC06 process. Although there are lots of layers listed, only some of them will be used. Some of the layers have two different versions like “POLY1 drw” and “POLY1 pin”. “drw” stands for drawing and “pin” stands for pin. While drawing the layout, only “drw” layers should be used. Those pin layers and other things are generated automatically by the extraction tools.

4. As the first task, we will draw a simple transistor. Click Create>Rectangle (r).

5. Now you should select the layer you want to draw with. Select "DIFF drw" from LSW.

6. Draw a rectangle 3.6 µm wide and 1.4 µm tall, for the dimensions use "dX, dY" displays at the top of the window. In order to draw the rectangle you should first click to the topleft corner and then click to the bottomright corner (just two clicks, no drag).

7. In order to make sure that you have drawn in the right size, use the "ruler". Click Misc>Ruler (k), and in order to focus on the circuit you have drawn press "f" (Fit command). Click on the topleft corner and measure the width and then length of the active. You should read 3.6 µm horizontally and 1.4 µm vertically. If the rectangle is not at the correct size, you should "Stretch" it. ClickEdit>Stretch (s). Move the mouse on the object so that the side you want to stretch is highlighted, then you can click and move the mouse for the new size, click again to fix the moving slide.

You may get difficulty if you are using “s” key instead of the menu. Do some trials.

8. Now select the layer "POLY1 dg" from LSW.

9. Similarly draw a rectangle of 0.6 µm wide and 2.6 µm tall right at the center of the active region. Use Edit>Move ("m") or Edit>Stretch ("s") to fix the position and size of the poly rectangle. The correct figure must look like the following:


10. In order to obtain electrical connection we will place two contacts to the diffusion area: one for drain and one for the source. To form such a contact, you must draw a rectangle of "MET1 drw" and a smaller rectangle of "CONT drw" inside the metal. However these layers can not be arbitrarily placed as explained in the design rules section before. Draw 2 MET1 rectangles with 1.2 µm width, and 2 CONT rectangles 0.6 µm width. The following figure shows the resulting drawing.

11. Now we have built a simple transistor, however did not specify whether it is nMOS or pMOS. For an nMOS transistor active area must be doped with n+, while for a pMOS transistor active area must be doped with p+. Do not forget that this is an nwell process, so pMOS transistors are placed in nwell, while nMOS transistors are directly built on the psubstrate. PIMP and NIMP layers will be used for p+ and n+ doping.

12. Another point is the bulk connections. As you know, transistors are 4 terminal devices. The 4th

terminal of an nMOS transistor is the psubstrate, while that of pMOS transistor is the nwell. Since all the wafer is (hence all the transistors are) built on the same substrate, all nMOS transistors must have the same bulk terminal, which is the most negative voltage level in the circuit: ground, so you


should consider threshold variation effects for transistors whose most negative terminals are connected to voltages other than ground. Similarly all the transistors in the same nwell have one common bulk terminal (usually VDD). However, one can place isolated nwells and can have different bulk voltages for isolated pMOS transistors. Although this is possible, it is usually impractical to place isolated wells, since they should be placed apart from each other.

13. We will also place one other contact for the bulk. In order to bypass Schottky diode effects (metal to silicon direct connection), one should dope the silicon to guarantee a resistive contact (also consider latchup). For an nMOS transistor, bulk connection is made to the psubstrate, so we should dope the active layer with p+ for a resistive contact; similarly for a pMOS transistor, bulk connection is made to the nwell, so we should dope the active layer below the contact with n+.

The figure below displays an nMOS transistor with bulk connection on the left:

The figure below displays a pMOS transistor with bulk connection on the left, and also has an nwell around:

14. Now we have two transistors, what is left is connecting them together. We need to route power lines "VDD" and "ground", then connect the input "A" and output "Q". The overall layout should look like the following:


PIMP NIMP

NWELL

NIMP PIMP

15. This process is specified as double metal, double poly, hence there are two different metals and one poly layer that can be used as conducting paths (the second poly is used for building capacitors). The convention for two metal processes are routing power lines (VDD, gnd) with the first metal, and routing signal paths (like input "A", and output "Q") with second metal. Hence, we will make metal2 contacts for "A" and "Q". In order to connect metal1 to metal2, one should use "via" layer; in order to connect poly1 to metal2 first make a contact from poly1 to metal1 and then make a "via" connection from metal1 to metal2.

Connections between MET1 and MET2, and between POLY1 and MET1 are frequently used, so a simply method is used in cadence. Select Create>Contact (“o”).

There are a number of contact types:

VIA_C: Connection between MET1 and MET2.

P1_C : Connection between POLY1 and MET1.

ND_C : Connection between n+ doped active region and MET1.

PD_C : Connection between p+ doped active region and MET1.

So you may use VIA_C for the output terminal, and P1_C and VIA_C for the input terminal. Still, you may draw these connection by yourselves as seen in the following figures. VIA_C is seen on the left, and P1_C is seen on the right. Note that, you may need to press ShiftF for showing the internal structure of the contacts (CtrlF is for hiding).


Using the information above, take contact to metal2 for both the input and the output. The final layout will look like the following.

16. As you may consider, we have not assigned names for the power and signal lines (remember ports in the schematic) yet. In this step we will create pins for "vdd!, gnd!, A, Q" (the "!" signs are necessary). Click Create>Pin. The following window pops up:


Check “Display pin name” checkbox on the window. Write "vdd!" in "Terminal Name" field, select "metal1_T" from "Pin Type", check only "left, right" in "Access Direction" list. Make sure that “I/O Type” is “input/output”. When you move the mouse over the layout, you will notice a rectangle moving with you. Place this pin onto the metal line at the top of the layout (zoom in with the right mouse button, in order to place that exactly). Similarly place a "gnd!" pin on the metal line at the bottom. Now change the "Pin Type" to "metal2_T" and create pins for "A" and "Q". Do not forget to change I/O Type to input and output when placing A and Q respectively. When you are done "Hide" the pop up window.

17. Now we have to check whether we have violated any design rules or not. This step is called as the DRC and is very important. DRC errors must be corrected before the layout is completed. In order to make DRC click Verify>DRC. A new window pops up. Click "OK". Icfb window will display the DRC steps, and finally report the errors found. If the layout gets along with all DRC rules, you should see the message "Total errors found: 0".

18. Select Verify>Markers>Delete all, and click "OK", this will clear all the markers that may result from errors you have made. Now we will introduce an error and then learn how to detect it. Stretch ("s") the gate poly right above the pMOS transistor, so that the distance between the active area and the end of the poly are only 0.4u. (DRC states that this distance must be at least 0.6u, and states this rule as "Minimum POLY1 extension of GATE = 0.6um". Now click Verify>DRC and click "OK". Icfb will display that you have violated this rule by displaying “Minimum POLY1 extension beyond GATE = 0.6”.

19. In this example there is only one error, and we know where the error is. Usually there are a number of errors and they are hard to locate. Now we will learn how to locate errors. Click Verify>Markers>Find. A new window pops up, check in the box for "Zoom to Markers", then click "Next". Correct the distance between active and top of the poly extension (0.6). Now click Verify>Markers>Delete all. Carry out a new DRC and make sure that there are no errors in the layout.

20. If there are no errors, click Design>Save.

You have completed your first layout... A few more steps are still remaining. In order to use this layout in the simulations, we have to "extract" it and form an "extracted" view.

21. Click Verify>Extract.

22. Click OK. CIW must report that "Total errors found: 0".


23. Now close the layout view, and open "extracted" view of the inverter. Press "Shift" and "f" together if the transistors are not seen. The view will look like the one on the right.

This is the end of the tutorial. So, you have drawn your first inverter layout, carried out the DRC, and generated extracted view.


6.6. LLAYOUTAYOUT VERSUSVERSUS S SCHEMATICCHEMATIC C CHECKHECK (LVS) (LVS)

Till now, you designed the schematics and layout of a CMOS inverter. However, you did not check yet whether the drawn layout is same as the schematics. In order to check whether the schematics and the layout are same, a special check mechanism is used called as LVS. What it does is to compare the netlists of the schematic view and the extracted view.

1. Open the extracted view of the inverter.

2. Click Verify>LVS. The window on the right will pop up:

3. Make sure that schematic and extracted are checked for “Create Netlist” part. Fill in the schematic and extracted “Library”, “Cell” and “View” as in the figure.

4. Click Run.5. After a short while, you will have

a message box stating that the LVS check is completed. Click OK in the message box.

6. In order to display the results, click on Output in the LVS window.

7. Now let’s consider our case. The transistors you drew in the layout have 1.4µm width, however, the ones in the schematics have probably different widths. So this will be found by LVS check and given as a warning. The following part is the possible LVS output that you will have. Some explanations are added with bold characters.

@(#)$CDS: LVS version 4.4.5 04/20/2000 16:37 (cds11182) $

Like matching is enabled.Net swapping is enabled.Using terminal names as correspondence points.

Net-list summary for /home/vlsi/tepegoz/EE413/LVS/layout/netlist count

4 nets4 terminals1 nmos41 pmos4

This part is the summary of the extracted view. There are 4 nets, 4 terminals (A,Q,vdd,gnd), and 2 transistors.

Net-list summary for /home/vlsi/tepegoz/EE413/LVS/schematic/netlist count

4 nets4 terminals


1 nmos41 pmos4

This part is the summary of the schematics similar to the extracted view case.

Terminal correspondence points 1 A 2 Q 3 gnd! 4 vdd!

The net-lists match logically but have mismatched parameters.

This line summarizes the results of the LVS check. It states that schematic and extracted views are same circuits, however there area some components with mismatched parameters.

layout schematicinstances

un-matched 0 0rewired 0 0size errors 2 2pruned 0 0active 2 2total 2 2

netsun-matched 0 0merged 0 0pruned 0 0active 4 4total 4 4

terminalsun-matched 0 0matched butdifferent type 0 0total 4 4

This part is the detailed information about the LVS check. The first part is about the instances of the components like the transistors, capacitors, or resistors. The report says that there are 2 size errors. If the schematic and the layout were different, there would be some unmatched components also.

Probe files from /home/vlsi/tepegoz/EE413/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:I /I1? Bad width : 2e-06 in layout, 1e-05 in schematic -I /I0? Bad width : 2e-06 in layout, 1e-05 in schematic -

This part is the further information about the LVS check. Last 2 lines state that instance I1 has 2 µm width in the layout, but 10 µm width in the schematics. Same for I0 also. Now, go and check what is I0 and I1 in the schematic view.

Probe files from /home/vlsi/tepegoz/EE413/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:


prunedev.out:

audit.out:I /+1? Bad width : 2e-06 in layout, 1e-05 in schematic -I /+0? Bad width : 2e-06 in layout, 1e-05 in schematic -

As the last, this part is the further information about layout view.

8. In the previous report, there are 2 layout and 2 schematic warnings, which are due to mismatch in the transistor dimensions (if you get more than this, you should go back to your design, and correct the problems). In order to correct this mismatches, you should go back to the schematics, and make the width of the transistor 1.4 u. After this, check and save the design, and start the LVS again. If there is no further warning or error, you should get a report very similar to this:

@(#)$CDS: LVS version 5.0.0 05/30/2003 19:44 (cds11939) $

Like matching is enabled.

Using terminal names as correspondence points.

Net-list summary for /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/layout/netlist count


Net-list summary for /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/schematic/netlist count


Terminal correspondence points 1 A 2 Q 3 gnd! 4 vdd!

The net-lists match.

layout schematicinstances

un-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 2 2total 2 2

netsun-matched 0 0merged 0 0pruned 0 0active 4 4total 4 4

terminalsun-matched 0 0matched butdifferent type 0 0total 4 4

Probe files from /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/schematic

devbad.out:netbad.out:mergenet.out:termbad.out:prunenet.out:prunedev.out:


audit.out:

Probe files from /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

9. Now, you will generate another view, called analog_extracted view, which contains additional information to extracted view for simulations. For this purpose, click on Build Analog on LVS window. Make sure that Include All is selected for Extracted Parasitics option, and then click OK. This will generate analog_extracted view to the inverter cell. You may go and check this view.


7.7. SSIMULATIONIMULATION OFOF THETHE I INVERTERNVERTER L LAYOUTAYOUT

In this tutorial, we will simulate the layout of the inverter, and see the differences. In the previous tutorials, you had simulated the schematics of the inverter. What you will do here is very similar to that except that you will simulate not the schematics, but the layout of the circuit. Also in the previous tutorials, you had generated the analog_extracted view. Extraction actually means generating netlist from the layout. During the extraction, many parasitics and more realistic parameters can be used. For instance, the capacitance of the metal lines crossing over another can be extracted, and added to the extracted view. So, extracted view simulations are more realistic than schematic simulations.

We will use “invsim” generated for the schematic simulations.

1. Open the schematic of “invsim”.2. Arrance vpulse such that it gives a square wave between 0 and 5 V, and with frequency of 5 Mhz.

Use a load of 1 pF.3. Click Tools>Analog Environment.4. Click Setup>Environment.5. There is a list named Switch View List, this list determines the order of views Analog Environment

will search for. Priority is from left to right, so type analog_extracted at the first place. Then click OK.

6. Click Analyses>Choose, and select "tran", enter "0.5u" for the simulation time.7. Click Output>To be Plotted>Select on Schematic.8. Click on the input and output wires of the inverter.9. Is the result what you expect? 10. Why do you think that layout simulation is important?


8.8. A SA SAMPLEAMPLE D DESIGNESIGN F FLOWLOW

In the previous parts, you completed a simple transistor level design. Check the following design flow, and try to understand which parts you have completed in the previous chapters.


Design of the circuit on paper

Draw Schematics

Simulate schematics

Good?

Y

N

Draw Layout

Do Design Rule Check (DRC)

Good?

Do Extraction and LVS

Good?

Simulate layout

Good?

END

N

Y

N

Y

N

Y

Find t

he e

rrors

and c

orr

ect

them

START

tutorial(1st assignment)

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