top design & implementation mistakes and how to …...title 1399 - top design &...

1Copyright © 2019 Arm TechCon, All rights reserved.Copyright © 2019 Arm TechCon, All rights reserved.

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Staff Application EngineerArm Luke Dare

Top Design & Implementation Mistakesand How to Avoid Them

2Copyright © 2019 Arm TechCon, All rights reserved.

Agenda

We have been helping people develop Arm-based solutions for over 20 years, I want to share the best tips we’ve learned that can help you to avoid unnecessary, critical development issues.

In the next 50 minutes we’ll look at some case studies where things have gone wrong in projects for perfectly understandable reasons, but we’ll also see how these problems could have possibly been avoided.

Respinning silicon and providing software patches in the field costs billions of dollars and delays the development of next generation products – do everything you can to avoid it!

Please turn phones off


1 – Design Review Red Flags• Validate your debug and trace use cases!• Design Reviews are littered with examples of broken debug and one has

to deal with the painful consequences• Classic example is power domains – many designers have done this

• Neglect to put debug and trace in its own power domain and when the CPU goes into power down, the debug subsystem turns off too, the debugger disconnects, and bye-bye debug and development

• Remember:• System != System Under Test• Sanity check design reviews

• $Cost• Platform respin or instrumentation to provide a compromised solution


2 – Coherency Woes• Making assumptions about bus behaviour and tying off signals can

cause problems • Example: Upper bits of the ACE ADDR bus are sometimes used to

signal distributed virtual memory• Designers that are not familiar with this might unwittingly tie these signals off• This renders DVMs and multi-cluster coherency unusable

• Remember:• Check all signals that are tied off• Run inter-cluster coherency tests

• $Cost• Respin or compromised system performance


3 – Integration - GIC-400 AxUSER Connection• Cortex-A CPUs indicate the CPU ID using some specific signals on their

bus interface• Different CPUs use different signals• Also dependent on the bus interface type (ACE or CHI)

• Interconnect needs to generate AxUSER[2] to differentiate clusters• The bit selected will depend on the interconnect and its topology

• An integration mistake would make the GIC-400 completely unworkable!

• Remember:• Just because IP blocks are designed to work together, they might need specific

configuration to work as expected

• $Cost• Respin or crippled performance


4 – A73 CPU Power Down Sequence Case Study

Cortex-A73 MPCore

SCUL2 Cache

CPU0

L1 Cache

• Step 1: Disable the data cache

• Step 2: Clean and invalidate all data from the L1 data cache

• Step 3: Set ECTLR.SMPEN = 0

• Step 4: ISB

• Step 5: DSB SY

• Step 6: WFI, wait until STANDBYWFI output is asserted

• Step 7: Activate the core output clamps

• Step 8: Assert nCPUPORESET LOW for at least eight cycles to propagate reset

• Step 9: Remove power from the PDCPU power domain.

PMC

STANDBYWFI[0]

L1 Cache

CPU1

snoopCLAMPEN

No hit

Clamp assertion is asynchronous-> CPU1 might never receive a proper snoop response, which cause the CPU hang

• Step 1: Disable the data cache

• Step 2: Clean and invalidate all data from the L1 data cache

• Step 3: Set ECTLR.SMPEN = 0

• Step 4: ISB

• Step 5: DSB SY

• Step 6: WFI, wait until STANDBYWFI output is asserted

• Step 7: Assert nCPUPORESET LOW for at least eight cycles to propagate reset

• Step 8: Activate the core output clamps

• Step 9: Remove power from the PDCPU power domain.

No hitnCPUPORESET[0]

No hit snoopsnoop

Different CPUs might have different requirements. The power sequence described in the TRM must be strictly followed to implement the low power mode!


5 – Multi-NIC Bus Topology

M1

S0

S3

S1 S2

M0 M2

M3

Dotted lines indicate master/slave interface connections

Registering component – possibly included to ease timing

Transaction queue


S0S1

S0 S1

M1

S0

S3

S1 S2

M0 M2B

DC

A

Write address transfer sequence

M0M1

M1M0

M3

A = M0 to S1

D = M1 to S1

B = M0 to S0

C = M1 to S0



S0S1

S0 S1

M1

S0

S3

S1 S2

M0 M2 Data transfer requirements

M0M1

M1M0

§S1 must see data from M1

§M1 must send data to S0

§S0 must see data from M0

§M0 must send data to S1

Result = DEADLOCK

M3




M1

S0

S3

S1 S2

M0 M2

M3

Break at points of divergence

Apply CDAS:Cyclic Dependency Avoidance Schemes


6 – Expecting Sensible Behavior

Even relatively simple systems can behave in unexpected ways that can lead to major problems

Example:

• The Cortex-M7 CPU can speculatively read from almost any address at any time unless you comprehensively take active measures to prevent it

• If it reads from an unresponsive address it can effectively be left waiting forever

• If you don’t have a strategy in place to avoid or recover from this scenario then you can face problematic system behaviour

Remember:

• Think about what system components can do (not what they should do)!

$Cost

• Expensive firmware/software updates in the field


7 – Micro-architecture != Architecture

Arm recommends that designers' program to the architecture specification

• This allows for the maximum portability of code - code that works an in-order Cortex-A53 will also run on an out-of-order processor like the Cortex-A76

Example problem:

• A programmer attempts to disable speculation using micro-architecture IMPLEMENTATION DEFINED registers. Typically, they want to do this due to erroneous hardware that isn’t tolerant of speculative reads, but hardware which utilizes the performance and cache ability of Normal memory.

• The Cortex-A53 TRM lists fields in micro-architecture IMPLEMENTATION DEFINED registers that look like they can turn off speciation. However, they are IMPLEMENTATION DEFINED and thus not portable as speculation is inherently permitted by the architecture to Normal memory. Reusing this code can lead to catastrophic problems that are only seen days, months or years later

Remember: target your code at the architecture

≠


8, 9, & 10 – More Usual Suspects

Don’t forget!

• None of the bus protocols Arm uses for its processors has an inherent bus timeout capability; we see designs where accesses are hanging because a memory location does not respond to the transaction request.

• CHI signals are crammed together in a single bus – but with variable sized fields, take care to connect up the buses that have different sized fields.

• Not all IP components are necessarily compatible. For example the GIC-500 Generic Interrupt Controller has a fixed view of how Processor ID Fields are defined that makes it unsuitable for use with the DynamIQ Shared Unit. Be sure that the components in your system will work together!


Leverage Arm’s Expertise

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Improve design quality Reduce cost and risk


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Lots of self-help material is also available

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Copyright © 2019

Thank You!

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