the role of eda in soc design

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Desig n The Role of EDA in SoC Design HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer Synopsys, Inc.

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The Role of EDA in SoC Design. HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer Synopsys, Inc. Agenda. Economic Technical Challenges Methodology. Agenda. Economic Challenges Technical Challenges Methodology. - PowerPoint PPT Presentation

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Page 1: The Role of EDA in SoC Design

Des

ign The Role of EDA in SoC

Design

HKSTP International Technology ConferenceJanuary 14, 2003

Dr. Chi-Foon ChanPresident and Chief Operating OfficerSynopsys, Inc.

Page 2: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (2) HKSTP International Technology Conference

Agenda

• Economic

• Technical Challenges

• Methodology

Page 3: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (3) HKSTP International Technology Conference

Agenda

• Economic Challenges

• Technical Challenges

• Methodology

Page 4: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (4) HKSTP International Technology Conference

IDM IDM $122B$122B

Various sourcesAprox. Values for 2001

Fabless $10B

IP $0.3BIP $0.3B

DesignDesign

Semiconductor Value Flow in 1996

Systems Systems $851B$851B

Embedded Embedded SW $0.4BSW $0.4B

FoundryFoundry$5.4B$5.4B

MaskMask

DataData

EDA $2.5BEDA $2.5B

Back-EndBack-End$5.9B$5.9B

Front-EndFront-End$22B$22B

Masks $2.1BMasks $2.1B

MaterialsMaterials $4.2B $4.2B

ManufacturingManufacturing

Page 5: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (5) HKSTP International Technology Conference

Various sourcesAprox. Values for 2001

IP $0.9BIP $0.9B

DesignDesign

Semiconductor Value Flow in 2001

Embedded Embedded SW $0.8BSW $0.8B

MaskMask

DataData

EDA $3.6BEDA $3.6B

Back-EndBack-End$5.6B$5.6B

Front-End Front-End $24B$24B

Masks $2.3BMasks $2.3B

MaterialsMaterials $4.0B $4.0B

ManufacturingManufacturing IDM IDM $106B$106B

Fabless $13B

Systems Systems $1050B$1050B

FoundryFoundry$9.1B$9.1B

Page 6: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (6) HKSTP International Technology Conference

IDM IDM $122B $122B

Various sourcesAprox. Values for 2001

IP $1.8BIP $1.8B

DesignDesign

Semiconductor Value Flow in 2006

Embedded Embedded SW $1.7BSW $1.7B

FoundryFoundry$31B$31B

MaskMask

DataData

EDA $6.1BEDA $6.1B

Back-EndBack-End$10B$10B

Front-EndFront-End$31B$31B

Masks $3.7BMasks $3.7B

MaterialsMaterials $6.7B $6.7B

ManufacturingManufacturing

Fabless $52B

Systems Systems $1429B$1429B

Page 7: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (7) HKSTP International Technology Conference

50%

60%

70%

80%

90%

100%

110%

Peak Peak +3 Peak +6 Peak +9 Peak +12 Peak +15 Peak +18 Peak +21 Peak +24

Semiconductor Sales Downturn

Source: SIA WSTS 3-mos average, Synopsys

October 2002

1996

1985

1998

1989

9/01

1996

1985

1998

1989

2002

Page 8: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (8) HKSTP International Technology Conference

50%

60%

70%

80%

90%

100%

110%

Peak Peak +3 Peak +6 Peak +9 Peak +12 Peak +15 Peak +18 Peak +21 Peak +24

Semiconductor Sales Downturn

Source: SIA WSTS 3-mos average, Synopsys

1996

1985

1998

1989

2002

9/01

Page 9: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (9) HKSTP International Technology Conference

50%

60%

70%

80%

90%

100%

110%

Peak Peak +3 Peak +6 Peak +9 Peak +12 Peak +15 Peak +18 Peak +21 Peak +24

Semiconductor Sales Downturn

Source: SIA WSTS 3-mos average, Synopsys

October 2002

1996

1985

1998

1989

Page 10: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (10) HKSTP International Technology Conference

Semiconductor Sales Downturn

Source: SIA WSTS, Synopsys

Worldwide

Asia Pacific

Per

cent

of P

eak

Mon

th S

ales

50%

60%

70%

80%

90%

100%

Oct 2001 Feb 2001 June 2001 Oct 2001 Feb 2002 June 2002 Oct 2002

Page 11: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (11) HKSTP International Technology Conference

ApplicationApplication Graphics Wireless Networking Networking Wireless

GeometryGeometry 0.13µ 0.13µ 0.13µ 0.13µ 0.13µ

TransistorsTransistors 30M 12M 12M 24M 12M

CostCost $10.7M $9.0M $5.7M $10.9M $16.3M

Staff-monthsStaff-months 346 326 161 333 483

Escalating Development Costs and Time

Source: International Business Strategies, 2002

Sample (Actual) VDSM Projects

Average: $10M+, 300+ Staff-months!Average: $10M+, 300+ Staff-months!

Page 12: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (12) HKSTP International Technology Conference

Process Sophistication Leads to Complex Alliances

FabFab

ProcessProcess

LibrariesLibraries

IP BlocksIP Blocks

ToolsTools

FlowFlow

Page 13: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (13) HKSTP International Technology Conference

Semiconductor Partnerships

Page 14: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (14) HKSTP International Technology Conference

Agenda

• Economic Overview

• Technical Challenges

• Methodology

Page 15: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (15) HKSTP International Technology Conference

Manufacturability •Process antenna effect (PAE)•Minimum area rule (MAE)•Double cut via•End-of-line wire extension•Metal filling / wide wire slotting

Interconnect Delay

Deep Subm Creates Many Problems

In 0.18u Wire-to-Wire Cap Dominates (CW >> CS)

CS

CW

0.25

M1M2

Less Charge

M3

Metal 3 Jumper Reduces Metal 1 L

M1Diode

Drains Charge

Reliability•Electromigration•Hot electron device degradation

Signal Integrity•Crosstalk

• Capacitive coupling• Inductive coupling

• IR (voltage) Drop

Page 16: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (16) HKSTP International Technology Conference

Challenges in Design Implementation

IPIPBus

Interface

MPEG A/D

, D

/A

PL L

Sync

Arbiter

CDI

R A MMem

ory

Con

trol

Large, Complex Chips

Signal Integrity Manufacturability

Timing Closure

Page 17: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (17) HKSTP International Technology Conference

Growing Verification Complexity

> 1M lines of HDL code!

Lin

es

of

Co

de

1980 2002

More Tools and Larger Verification Teams

GatesGates

Sim

ula

tio

n C

yc

les

Sim

ula

tio

n C

yc

les

2007

2001

1M 10M 100M

100M

100B

10T

1995

> 200B Simulation Cycles

70%Verification

Design30%

Page 18: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (18) HKSTP International Technology Conference

Average Gate Counts By Region

0%

10%

20%

30%

1-100K 101K-300K

301K-999K

1M-1.9M 2M-3.9M 4M-5.9M 6M-7.9M 8M+

Gates

North AmericaEuropeJapanAsia

Synopsys SNUG Data 2002

Designs tend to be larger in North America (more mP) and tend to be smaller in Asia (more consumer electronics)

Page 19: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (19) HKSTP International Technology Conference

Most Non-North America Chips Run at <150MHz

0%

20%

40%

60%

1-100MHz 101K-150MHz

151-200MHz 201-400MHz 401-600MHz 601-800MHz 800MHz+

North America

Europe

Japan

Asia

Synopsys SNUG Data 2002

Page 20: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (20) HKSTP International Technology Conference

Design Geometries by Region

0%

20%

40%

60%

<.11 0.11 0.13 0.15 0.18 0.25 >.25

microns

North America

Europe

Japan

Asia

Synopsys SNUG Data 2002

44% of designs in Asia at .25-micron or larger compared to 22% in Japan and 17% in Europe

Page 21: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (21) HKSTP International Technology Conference

Most Non-North America Chips Run at <150MHz

0%

20%

40%

60%

1-100MHz 101K-150MHz

151-200MHz 201-400MHz 401-600MHz 601-800MHz 800MHz+

North America

Europe

Japan

Asia

Synopsys SNUG Data 2002

Page 22: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (22) HKSTP International Technology Conference

Customers Will Increasingly Converge on Platforms

Physical ImplementationPhysical Implementation

Design PlanningDesign Planning

ExtractionExtraction

Physical VerificationPhysical Verification

Mask Synthesis / OPCMask Synthesis / OPC

Lan

gu

ag

esL

ang

ua

ges

Ass

erti

on

s an

d T

estb

ench

esA

sser

tio

ns

and

Tes

tben

ches

Smart VerificationSmart Verification

Architecture DesignArchitecture Design

Mixed Signal / AnalogMixed Signal / Analog

Ver

ific

atio

n I

PV

erif

icat

ion

IP

Des

ign

Dat

ab

ase

Des

ign

Dat

ab

ase

Tim

ing

an

d S

ign

al I

nte

gri

tyT

imin

g a

nd

Sig

nal

In

teg

rity Te

stTe

st Pow

erPo

wer

Phys

ical

Phys

ical SynthesisSynthesis

IPIP

Verification PlatformVerification PlatformImplementation PlatformImplementation Platform

Page 23: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (23) HKSTP International Technology Conference

Agenda

• Economic

• Technical Challenges

• Methodology

Page 24: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (24) HKSTP International Technology Conference

PhysicsPhysics

ComplexityComplexity

Design Pressures

Courtesy of NVIDIA

Page 25: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (25) HKSTP International Technology Conference

Challenge: HW/SW Complexity

100M100MGatesGates

20072007

2000 EY2000 EY

10M10MGatesGates

20012001

200 EY200 EY

1M1MGatesGates

19951995

20 EY20 EY

SolutionsSolutions

1.1. Higher level of abstractionHigher level of abstraction

• System-level toolsSystem-level tools

2.2. IP design reuseIP design reuse

Page 26: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (26) HKSTP International Technology Conference

… 80% of the circuitry in SoCswill be acquired, not designed

Star IPStar IPIn-house IPIn-house IP3rd Party IP3rd Party IP

Customer

Customer

Designed

Designed50%

80%95%

2000 2005 2010

By 2005..

Page 27: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (27) HKSTP International Technology Conference

• IP is at the core of deep

sub-micron SoC design

methodology

• Platforms = IP + SLD (HW)

Page 28: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (28) HKSTP International Technology Conference

IP Reuse: 3 Fundamental Hurdles

Efficiently acquiring

3rd-party IP

Creating &integratingquality IP

Changing the corporate

culture

Page 29: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (29) HKSTP International Technology Conference

IP Reuse: 3 Solutions

Choose solid IP partners

Design using integrated platform of

tools

Start right: Use “top down”

methodology

Page 30: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (30) HKSTP International Technology Conference

Agenda

• Economic

• Technical Challenges

• Methodology

Page 31: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (31) HKSTP International Technology Conference

Current Realities of IC Design

EconomicEconomicStressStress

• Craft advantageous economic ventures

• Partner with EDA to overcome technical challenges

• Use “partnered” tools: platforms and IP deal with shrinking geometries and increasing complexities

SolutionSolution==

SmartSmartPartnershipsPartnerships

DesignDesignChallengeChallenge

IncreasingIncreasingComplexityComplexity

Page 32: The Role of EDA in SoC Design

© 2003 Synopsys, Inc. (32) HKSTP International Technology Conference

2002 EE Times Reader EDA Survey

66%66%

47%47%

45%45%

41%41%

34%34%

34%34%

30%30%

22%22%

21%21%

12%12%

Best integration w/ other vendors’ toolsBest integration w/ other vendors’ tools

Technology leader todayTechnology leader today

Technology leader in 3 yearsTechnology leader in 3 years

Clear vision of futureClear vision of future

Most ethical companyMost ethical company

Knowledgeable sales repsKnowledgeable sales reps

Well-managed companyWell-managed company

Best before-sales system supportBest before-sales system support

Offers consulting design servicesOffers consulting design services

Best documentationBest documentation

Best training servicesBest training services

Best Web siteBest Web site

9%9%

20%20%

8%8%

Attribute in selecting vendorAttribute in selecting vendor Importance Importance

Best after-sales support Best after-sales support

Page 33: The Role of EDA in SoC Design

Des

ign