The architecture and instruction set of this new 16-bitmicroprocessor were designed to meet the requirements of a

broad spectrum of hew microprocessor applications.

Stephen P. MorseWilliam B. PohlmanBruce W. RavenelIntel Corporation

The new Intel 8086 microprocessor was designedto be a compatible successor to the 8080, and yetit provides an order of magnitude increase in pro-cessing throughput over the older machine. Theprocessor design was constrained to be assembly-language-level compatible with the 8080 so thatexisting 8080 software could be reassembled andcorrectly executed on the 8086. To allow this com-patibility the 8080 register set and instruction sethave to appear as logical subsets of the 8086registers and instructions.The goals of the 8086 architectural design were

to provide symmetric extensions of existing 8080features, as well as the following new processingcapabilities not found in the 8080:

Intel 8086 Device CharacteristicsALU Width: 16 bitsMemory addressing capability: 1,048,576 bytesAddressable 110 ports: 64KProcess: HMOSGate propagation delay: = 2 nsClock period: 200 ns standard 125 ns selectedMemory access: 800 ns standard 500 ns selectedRelative performance: 7 to 12 times

8080A, depend-ing on characterof program

Pins: 40Power: + 5V

16-bit arithmetic, signed 8- and 16-bit arithmetic(including multiply and divide), efficient inter-ruptible byte-string operations, improved bit-manipulation facilities, mechanisms to providefor re-entrant code, position-independent code,dynamically relocatable programs.

Another design goal was to be able to addressdirectly more than 64K bytes and support multi-processor configurations.'The 8086 memory structure includes up to one

megabyte of memory space and up to 64K bytes ofinput/output ports. The register structure includesthree files of registers. Four 16-bit general registerscan participate interchangeably in arithmetic andlogic operations, two 16-bit pointer and two 16-bitindex registers are used for address calculations,and four 16-bit segment registers allow extendedaddressing capabilities. Nine flags record the pro-cessor state and control its operation.The instruction set supports a wide range of

addressing modes and operations for data transfer,signed and unsigned 8- and 16-bit arithmetics,logicals, string manipulation, control transfer, andprocessor control. The external interface includes areset sequence, interrupts, and a multiprocessor-synchronization and resource-sharing facility.

Memory structure

The 8086 memory structure consists of twocomponents-the memory space and the input/

018-9162/78/0600-0018$00.75 © 1978 IEEEM COMPUTER18

output space. All instruction code and operandsreside in the memory space. Peripheral and I/Odevices ordinarily reside in the I/O space, except inthe case of memory-mapped devices.

15

OFFSETADDRESS

Memory space. The 8086 memory is a sequenceof up to 1 million 8-bit bytes, a considerable increaseover the 64K bytes in the 8080. Any two consecu-tive bytes may be paired together to form a 16-bitword. Such words may be located at odd or evenbyte addresses (16-bit references to odd locationsrequire two hardware memory cycles, while thoseto even locations require just one). The most signi-ficant 8 bits of word are located in the byte withthe higher memory address.Since the 8086 processor performs 16-bit arith-

metic, the address objects it manipulates are 16 bitsin length. Since a 16-bit quantity can address only64K bytes, additional mechanisms are required tobuild addresses in a megabyte memory space. The8086 memory may be conceived of as an arbitrarynumber of segments, each at most 64K bytes insize. Each segment begins at an address which isevenly divisible by 16 (i.e., the low-order 4 bits of asegment's address are zero). At any given momentthe contents of four of these segments are imme-diately addressable. These four segments, called thecurrent code segment, the current data segment,the current stack segment, and the current extrasegment, need not be unique and may overlap. Thehigh-order 16 bits of the address of each currentsegment are held in a dedicated 16-bit segmentregister and are called the segment address. In thedegenerate case where all four segments start atthe same address, namely address 0, we have an8080 memory structure.Bytes or words within a segment are addressed

using 16-bit offset addresses within the 64K bytesegment. A 20-bit physical address is constructedby adding the 16-bit offset address to the 16-bitsegment address with 4 low-order zero bits append-ed, as illustrated in Figure 1.

n

SEGMENTADDRESS

C

Input/output space. In contrast to the 256 I/Oports in the 8080, the 8086 provides 64K addres-sable input or output ports. Unlike the memory, theI/O space is addressed as if it were a single segment,without the use of segment registers. Input/outputphysical addresses are in fact 20 bits in length,but the high-order 4 bits are always zero. Portsmay be 8 or 16 bits in size, and 16-bit ports may belocated as odd or even addresses.

Register structure

The 8086 processor contains three files of four16-bit registers and a file of nine 1-bit flags. Thethree files of registers are the general register file,the pointer and index register file, and the segmentregister file. There is a 16-bit instruction pointerwhich is not directly accessible to the programmer;

1l 0

PHYSICALADDRESS

Figure 1. To address 1 million bytes requires a 20-bit memoryaddress. This 20-bit address is constructed by offsetting the effec-tive address 4 bits to the right of the segment address, filling inthe 4 low-order bits of the segment address with zeros, and addingthe two.

rather, it is manipulated with control transfer in-structions. The 8086 register set is a superset ofthe 8080 registers, as shown in Figures 2 and 3.Corresponding registers in the 8080 and 8086 donot necessarily have the same names, thereby per-mitting the 8086 to use a more meaningful set ofnames.

June 1978

0

19

GENERAL REGISTERS0,

HL:

BC:

DE:

SP:

H

7 0A

L

B C

POINTER AND INDEX REGISTERS15 0

SEGMENT REGISTERS15

INSTRUCTION POINTER AND FLAGS15

PC:

FLAGS:

41 PRESENT IN 8086BUT10 NOT IN 8080.

Figure 2. The 8080 register structure is a subset of thenew 8086 register structure.

General register file. The AX-BX-CX-DX registerset is called the general register file, or HL group

(for reasons that will be apparent below). Thegeneral registers can participate interchangeably inthe arithmetic and logical operations of the 8086.Some of the other 8086 operations (such as thestring operations) dedicate certain of the generalregisters to specific uses. These uses are indicatedby the mnemonic phrases in Figure 3. The generalregisters have a property that distinguishes themfrom the other registers-viz., that their upper andlower halves are separately addressable. Thus, thegeneral registers can be thought of as two files offour 8-bit registers-the H file and the L file.

Pointer and index register file. The SP-BP-SI-DIregister set is called the pointer and index registerfile, or the P and I groups. The registers in this fileare similar in that they generally contain offsetaddresses used for addressing within a segment.Like the general registers, the pointer and indexregisters can participate interchangeably in the16-bit arithmetic and logical operations of the 8086.They are also similar in that they can enter into

address computations. There are some differences,however, which result in dividing this file into twosubfiles, the P or pointer group (SP, BP) and the I orindex group (SI, DI). The difference is that thepointers are by default assumed to contain offsetaddresses within the current stack segment, and theindexes are by default generaDly assumed to containoffset addresses within the current data segment.There are also mnemonics associated with theseregisters' names, as shown in Figure 3.

Segment register file. The CS-DS-SS-ES register setis called the segment register file, or S group. Thesegment registers play an important role in thememory addressing mechanisms of the processor.These registers are similar in that they are used inall memory address computations (see descriptionof memory structure). The segment registers' nameshave associated mnemonic phrases, as shown inFigure 3.The contents of the cs register flefine the current

code segment. All instruction fetches are taken tobe relative to cs, using the instruction pointer(iP) as an offset. The contents of the DS registerdefine-the current data segment. GeneraLLy, aLL datareferences except those involving BP or sp aretaken by default to be relative to DS. The contentsof the ss register define the current stack segment.All data references which explicitly or implicitlyinvolve sP or BP are taken by default to be relativeto ss. This includes all push and pop operations,including those caused by caLL operations, interrupts,and return operations.In general, the default segment register for the

two types of data references (DS or ss) can be over-ridden. By preceding the instruction with a special1-byte prefix the reference can be forced to be rela-tive to one of the other three segment registers.The contents of the ES register define the currentextra segment. The extra segment has no specificuse, although it is usually treated as an additionaldata segment.Programs which do not load or manipulate the

segment registers are said to be dynamically relo-catable. Such a program may be interrupted, movedin memory to a new location, and restarted withnew segment register values.

Flag register file. The AF-CF-DF-IF-OF-PF-SF-TF-ZFregister set is caLLed the flag register file or F group.The flags in this group are all one bit in size, andare used to record processor status information andto control processor operation. The flag registers'names have the following associated mnemonicphrases:

COMPUTER

SI Z I IA I I

I

20

AF: Auxiliary carryCF: CarryDF: DirectionIF: Interrupt enableOF: OverflowPF: ParitySF: SignTF: TrapZF: Zero

The AF, CF, PF, SF, and ZF flags retain their familiar8080 semantics, generally reflecting the status ofthe latest arithmetic or logical operation. The OFflag joins this group, reflecting the signed arith-metic overflow condition. The DF, IF, and TF flagsare used to control certain aspects of the processor.The DF flag controls the direction of the stringmanipulation instructions (auto-incrementing orauto-decrementing). The IF flag enables or disablesexternal interrupts. The TF flag puts the processorinto a single-step mode for program debugging.More detail is given on each of these three flagslater in the article.

AX:

BX:

CX:

DX:

SP:

BP:

SI:

DI:

Instruction set

The 8086 instruction set-while including mostof the 8080 set as a subset-has more ways toaddress operands and more power in every area. Itis designed to implement block-structured languagesefficiently. Nearly all instructions operate on either8- or 16-bit operands. There are four classes ofdata transfer. All four arithmetic operations areavailable. An additional logic instruction, test, isincluded. Also new are byte and word string manip-ulation and inter-segment transfers.

Operand addressing. The 8086 instruction setprovides many more ways to address operandsthan were provided by the 8080. Two-operand opera-tions generally allow either a register or memoryto serve as one operand, and either a register or aconstant within the instruction to serve as theother operand. In general, operands in memorymay be addressed directly with a 16-bit offsetaddress, or indirectly with base (BX or BP) and/orindex (SI or DI) registers added to an optional 8-or 16-bit displacement constant. The result of atwo-operand operation may be directed to either ofthe source operands, with the exception, of course,of in-line immediate constants. Single-operandoperations are applicable uniformly to any operandexcept immediate constants. Virtually all 8086operations may specify 8- or 16-bit operands.

Memory operands. Operands residing in memorymay be addressed in four ways:direct 16-bit offset address;indirect through a base register, optionally withan 8- or 16-bit displacement;indirect through an index register, optionallywith an 8- or 16-bit displacement;

June 1978

CS:

DS:

SS:

ES:

IP:

FLAGS:

GENERAL REGISTERS0 77 0

AH AL

BH BL

CH CL

DH DL

POINTER AND INDEX REGISTERS15 0

SEGMENT REGISTERS15 0

INSTRUCTION POINTER AND FLAGS15 0O

.~~~~T _Z_

ACCUMULATOR

BASE

COUNT

DATA

STACKPOINTER

BASE POINTER

SOURCEINDEXDESTINATIONINDEX

CODE

DATA

STACK

EXTRA

Figure 3. The powerful 8086 register structure has many moreregisters and four more flags than the 8080. The chief differenceis that they can process 16-bit data. However, the general registersremain byte-addressable.

indirect through the sum of a base register andan index register, optionally with an 8- or 16-bitdisplacement.

The general register, BX, and the pointer register,BP, may serve as base registers. When BX is thebase, the operand by default resides in the currentdata segment. When BP iS the base, the operand bydefault resides in the current stack segment. Whenboth base and index registers are used, the operandby default resides in the segment determined bythe base register. When an index register aloneis used, the operand by default resides in the cur-rent data segment.

21

Register operands. The four 16-bit general regis-ters and the four 16-bit pointer and index registersmay serve interchangeably as operands in 16-bitoperations. Three exceptions to note are multiply,divide, and the string operations, all of which usethe AX register implicity. The eight 8-bit registersof the HL group may serve interchangeably in 8-bitoperations. Again, multiply, divide, and the stringoperations use AL implicitly.

Immediate operands. All two-operand operationsexcept multiply, divide, and the string operationsallow one source operand to appear within theinstruction as immediate data. Sixteen-bit imme-diate operands having a high-order byte which isthe sign extension of the low-order byte may beabbreviated to 8 bits.

that two array elements can be accessed concur-rently.

Example: An example of a procedure-callingsequence on the 8086 illustrates the interactionof the addressing modes and activation records.

;CALL MYPROC (ALPHA, BETA)PUSH ALPHAPUSH BETACALL MYPROC

;PROCEDURE MYPROC (A, B)MYPROC:

PUSH BPMOV BP,SPSUB SP,LOCALS

;body of procedure

;Pass parameters by;Pushing them on the stack;Call the procedure

;Entry point;Save previous BP value;Make BP point at new record;Allocate local storage on stack;for reentrant procedures

Virtually all 8086 operations mayspecify either 8- or 16-bit operands.

Addressing mode usage. The addressing modespermit registers BX and BP to serve as baseregisters and registers si and DI as index registers.Possible use of this for language implementationis discussed below:

Simple variables and arrays: A simple variable isaccessed with the direct address mode. An arrayelement is accessed with the indirect access modeutilizing the sum of the registers si (where sicontains the index into the array) and displace-ment (where displacement is the offset of thearray in its segment).Based variables: A based variable is located ata memory address pointed at by some othervariable. If the contents of the pointer variablewere placed in BX, the indirect addressing modeutilizing BX would access the based variable.If the based variable were an array and the indexinto the array were placed in si, the indirectaddressing mode utilizing the sum of the registerBX and the register si would access elements ofthe array.Stack marker: Marking a stack permits efficientimplementation of block-structured languages andprovides an efficient address mechanism for re-entrant procedures. Register BP can be used asa stack marker pointing to the beginning of anactivation record in the stack. The indirectaddress mode utilizing the sums of the baseregister BP and a displacement (where displace-ment -is the offset of a local variable in theactivation record) will access the variable declaredin the currently active block. The indirect addressmode utilizing the sum of the base register BP,index register si (where Si contains the indexinto an array), and displacement (where displace-ment is the offset of the array in the activationrecord) wir access an element of the array. Regis-ter DI can be used in the same manner as si so

MOV SP,BPPOP BPRET 4

;Deallocate local storage;Restore previous BP;Return and discard 4 bytes;of parameters

Upon entry to the procedure MYPROC its parametersare addressable with positive offsets from BP(stack grows towards lower memory addresses).Since usually less than 128 bytes of parameters arepassed, only an 8-bit signed displacement from BPis needed. Similarly, local variables to MYPROC areaddressable with negative offsets from BP. Again,economy of instruction size is realized by using8-bit signed displacements. A special return instruc-tion discards the parameters pushed on the stack.

Data transfer. Four classes of data transferoperations may be distinguished: general-purpose,accumulator-specific, address-object transfers, andflag transfers.The general-purpose data transfer operations are

move, push, pop, and exchange. Generally, theseoperations are available for all types of operands.The accumulator-specific transfers include input

and output, and the translate operation. The first256 ports can be addressed directly, just as theywere addressed in the 8080. However, the 8086 alsopermits ports to be addressed indirectly througha register (DX). This latter facility allows 64Kports to be addressed. Furthermore, the 8086 portsmay be 8 or 16 bits wide, whereas the 8080 onlypermitted 8-bit wide ports. The translate operationperforms a table-lookup byte translation. We willsee the usefulness of this operation below, when itis combined with string operations.The address-object transfers-load effective

address and load pointer-are an 8086 facility notpresent in the 8080. The load effective addressoperation provides access to the address of anoperand, as opposed to the value of the operanditself. The load pointer operations provide a meansof loading a segment register and a general orpointer register in a single operation. Such 32-bitpointers are used to gain access to the full mega-byte of memory.

COMPUTER22

The flag transfers provide access to the collec-tion,of flags for such operations as push, pop, load,and store. A similar facility for pushing and poppingflags was provided in the 8080; the load and storeflags facility is new in the 8086.

Arithmetics. Whereas the 8080 provided for only8-bit addition and subtraction of unsigned numbers,the 8086 provides all four basic mathematicalfunctions. Both 8- and 16-bit operations and bothsigned and unsigned arithmetic are provided.Standard 2's-complement representation of signedvalues is used. Sufficient conditional transfersare provided to allow both signed and unsignedcomparisons. The OF flag allows detection of thesigned overflow condition. The 8080 provided a cor-rection operation to allow addition to be performeddirectly on packed binary-coded representationsof decimal digits. In the 8086, correction operationsare provided to allow arithmetic to be performeddirectly on unpacked representations of decimaldigits (e.g., ASCII) or on packed decimal repre-sentations.

Multiply and divide. Both signed and unsignedmultiply and divide operations are provided. Mul-tiply produces a double length product (16 bitsfor 8-bit multiply, 32 bits for 16-bit multiply), whiledivide returns a single-length quotient and a single-length remainder from a double-length dividendand single-length divisor. Sign extension operationsallow one to construct the double-length dividendneeded for signed division. A quotient overflow(e.g., divide by zero) will automatically interruptthe processor.

Decimal instructions. Packed BCD operations areprovided in the form of an accumulator adjustmentinstruction. Two such instructions are provided-one for an adjustment following an addition andone following a subtraction. The addition adjust-ment is identical to the 8080 DAA instruction; thesubtraction adjustment is similarly defined.Unpacked BCD operations are also provided in

the form of accumulator adjust instructions (ASCIIis a special case of unpacked BCD). Four such in-structions are provided, one each for adjustmentsinvolving addition, subtraction, multiplication, anddivision. The addition and subtraction adjustmentare similar to the corresponding packed BCD ad-justments except that the AH register is updated ifan adjustment on AL is required. Unlike packedBCD, unpacked BCD byte multiplication does notgenerate cross terms, so multiplication and divisionadjustments' are possible. The multiplication adjust-ment consists of converting the binary value in theAL register into BCD digits in AH and AL; thedivide adjustment does the reverse. Note thatadjustments for addition, subtraction, and multipli-cation are performed following the arithmetic opera-tion; division adjustment is performed prior to adivision operation.

The following examples show how these adjustments wouldbe used.

ASCII addition: a + b - > c

O - > (CARRY)DO i = 1 to N

(a[i] ) - >(AL)(AL) + (b[i] ) - >(AL)

where " +" denotes add with carryadd-adjust (AL) - >(AX)(AL) - >(C[i])

ASCII subtraction: a - b -> c

O - > (CARRY)DO i = 1 to N

(a[i]) - >(AL)(AL) - (b[i]) - > (AL)

where "- denotes subtract with borrowsubtract-adjust (AL) - > (AX)(AL) -> (C[i])

ASCII multiplication: a * b - > c

(b) AND OFH - >(b)o- > (c[1)DO i = 1 to N

(a[i] AND OFH - > (AL)(AL) * (b) - > (AX)multiply-adjust (AL) - > (AX)(AL) + (C[i]J - > (AL)add-adjust (AL) - > (AX)(AL) - > (C[i])(AH) - > (C[i + 1])

ASCII division: a /b -> c

(b) AND OFH - >(b)O - >(AH)DO i = N to 1

(a[i]) AND OFH - > (AL)divide-adjust (AX) - >(AL)(AL) / (b) - > (AL)

with quotient going into (AH)(AL) - >(C[i])

Logicals. The standard logical operations AND,OR, XOR, and NOT are carry-overs from the 8080.Additionally, the 8086 provides a logical TEST forspecific bits. This consists of a logical AND instruc-tion which sets the flags but does not store theresult, thereby not destroying either operand.The four unit-rotate instructions in the 8080

are augmented with four unit-shift instructions inthe 8086. Furthermore, the 8086 provides multi-bit shifts and rotates, including an arithmetic rightshift.

String manipulation. The 8086 provides a groupof 1-byte instructions which perform various primi-tive operations for the manipulation of byte andword strings (sequences of bytes or words). Theseprimitive operations can be performed repeatedlyin hardware by preceding the instruction' with aspecial prefix. The single-operation forms may becombined to form complex string operations intight software loops with repetition provided byspecial iteration operations. The 8080 did not pro-vide any string-manipulation facilities.

Hardware operation control. All primitive stringoperations use the si register to address the source

June 1978 23

operands, which are assumed to be in the currentdata segment. The DI register is used to addressthe destination operands, which reside .in the cur-rent extra segment. The operand pointers areincremented or decremented (depending on thesetting of the DF flag) after each operation, oncefor byte operations and twice for word operations.Any of the primitive string operation instruc-

tions may be preceded with a 1-byte prefixindicating that the operation is to be repeateduntil the operation count in cx is satisfied. Thetest for completion is made prior to each repetitionof the operation. Thus, an initial operation countof zero will cause zero executions of the primitiveoperation.

Primitive operations manipulatingbyte or word strings can be performed

repeatedly in hardware, greatlyincreasing speed and efficiency.

The repeat prefix byte also designates a valueto compare with the ZF flag. If the primitive opera-tion is one which affects the ZF flag, and the ZFflag is unequal to the designated value after anyexecution of the primitive operation, the repetitionis terminated. This permits the scan operation toserve as a scan-while or a scan-until.During the execution of a repeated primitive

operation the operand pointer registers (sI and DI)and the operation count register (cx) are updatedafter each- repetition, whereas the instructionpointer will retain the offset address of the repeatprefix byte (assuming it immediately precedes thestring operation instruction). Thus, an interruptedrepeated operation will be correctly resumed whencontrol returns from the interrupting task.

Primitive string operations. Five primitive stringoperations- are provided:

* MOVB (or MOVW) moves a byte (or word) oper-and from the source operand to the destinationoperand. As a repeated operation this providesfor moving a string from one location in memoryto another.* CMPB (or CMPW) subtracts the destination byte(or word) operand from the source operand andaffects the flags but does not return the result.As a repeated operation this provides for com-paring two strings. With the appropriate repeatprefix it is possible to compare two strings anddetermine after which string element the twostrings become unequal, thereby establishing anordering between the strings.

* SCAB (or SCAW) subtracts the destination byte(or word) operand from AL (or AX) and affectsthe flags but does not return the result. As arepeated operation this provides for scanning forthe occurrence of, or departure from, a givenvalue in the string.

* LODB (or LODW) loads a byte (or word) operandfrom the source operand to AL (or AX). This oper-ation ordinarily would not be repeated.

* STOB (or STOW) stores a byte (or word) operandfrom AL (or AX) to the destination operand. Asa repeated operation this provides for filling astring with a given value.

Software operation control. The repeat prefixprovides for rapid iteration in a hardware-repeatedstring operation. Iteration-control operations pro-vide this same control for implementing softwareloops to perform complex string operations. Theseiteration operations provide the same operationcount update, operation completion test, and ZFflag tests that the repeat prefix provides.The iteration-control transfer operations perform

leading- and trailing-decision loop control. Thedestinations of iteration-control transfers must bewithin a 256-byte range centered about the instruc-tion.Four iteration-control transfer operations are

provided:

* LOOP decrements the cx ("cotint") register byone and transfers if cx is not zero.

* LOOPZ (also called LOOPE) decrements the cxregister by one and transfers if cx is not zero andthe ZF flag is set (loop while zero or loop whileequal).* LOOPNZ (also called LOOPNE) decrements the cxregister by one and transfers if cx is not zeroand the ZF flag is cleared (loop while not zero orloop while not equal).

* Jcxz transfers if the cx register is zero. Thisis used for skipping over a loop when the initialcount is zero.

By combining the primitive string operationsand iteration-control operations with other opera-tions, it is possible to build sophisticated yetefficient string manipulation routines. One instruc-tion that is particularly useful in this context isthe translate operation; it permits a byte fetchedfrom one string to be translated before beingstored in a second string, or before being operatedupon in some other fashion. The translation is per-formed by using the value in the AL register toindex into a table pointed at by the BX register.The translated value obtained from the table thenreplaces the value initially in the AL register.As an example of use of the primitive string

operations and iteration-control operations to im-plement a complex string operation, consider thefollowing application: An input driver must transfercharacters until one of several different EBCDICcontrol characters is encountered. The transferredASCII string is to be terminated with an EOTcharacter. To accomplish this, si is initialized topoint to the beginning of the EBCDIC buffer, DIis initialized to point to the beginning of the bufferto receive the ASCII characters, BX iS made to

COMPUTER24

point to an EBCDIC to ASCII translation table,and cx is initialized to contain the length of theEBCDIC buffer (possibly empty). The translationtable contains the ASCII equivalent for eachEBCDIC character, perhaps with ASCII NULS forillegal characters. The EOT code is placed intothose entries in the table corresponding to thedesired EBCDIC stop characters. The 8086 instruc-tion sequence to implement this example is thefollowing:

Jcxz EmptyNext:LODB Ebcbuf ;fetch next EBCDIC characterXLAT Table ;translate it to ASCIICMP AL,EOT ;test for the EOTSTOB Ascbuf ;transfer ASCII characterLOOPNE Next ;continue if not EOT

Empty:The body of this loop requires just seven bytes

of code.

Transfers. Two basic varieties of calls, jumps,and returns are provided in the 8086: intra-segmenttransfers, which transfer control within the currentcode segment, and inter-segment transfers, whichtransfer control to an arbitrary code segment,which then becomes the current code segment.Furthermore, both direct and indirect transfersare supported; indirect transfers make use of thestandard addressing modes, as described previously,to locate an operand which specifies the destinationof the transfer. By contrast, the 8080 providesonly direct intra-segment transfers.

Facilities for position-independent code andcoding efficiency not found in the 8080 have beenintroduced in the 8086. Intra-segment direct callsand jumps specify a self-relative direct displace-ment, thus allowing position-independent code. Ashortened jump instruction is available for trans-fers within a 256-byte range centered about theinstruction, thus allowing for code compaction.Returns may optionally adjust the sp register soas to discard stacked parameters, thereby makingparameters passing more efficient.The 8080 provided conditional jumps useful for

determining relations between unsigned numbers.The 8086 augments these with conditional jumpsfor determining relations between signed numbers.Trhe seldom-used conditional calls and returnsprovided by the 8080 have not been incorporatedinto the 8086.

External interface. The 8086 processor providesboth common and uncommon relationships toexternal equipment. The two varieties of interrupts,maskable and non-maskable, are not uncommon,nor is single-step diagnostic capability. Moreunusual is the ability to escape to an externalprocessor to perform specialized operations. Also

June 1978

uncommon is the hardware mechanism to controlaccess to shared resources in a multiple-processorconfiguration.

Interrupts. The interrupt mechanism of the 8086is much more general than that of the 8080-andin fact bears no resemblance to it. The 8086 pro-cessor recognizes two varieties of external inter-rupt-the non-maskable interrupt and the maskableinterrupt. A pin is provided for each variety.

Interrupts result in a transfer of control to a newlocation in a new code segment. A 256-elementtable (interrupt transfer vector) containing pointersto these interrupt service code locations resides atthe beginning of memory. Each element is four

The interrupt mechanism of the 8086is much more general than that ofthe 8080-and in fact bears no

resemblance to it.

bytes in size, containing an offset address and asegment address for the service code segment.Each element of this table corresponds to aninterrupt type, these types being numbered 0 to255. All interrupts perform a transfer by pushingthe current flag settings onto the stack and thenperforming an indirect call (of the inter-segmentvariety) through the interrupt transfer vector.Program execution control may be transferred

by means of operations similar in effect to that ofexternal interrupts. A generalized 2-byte instruc-tion is provided that generates an interrupt of anytype; the type is specified in the second byte. Aspecial 1-byte instruction to generate an interruptof one particular type is also provided. Such aninstruction would be required by a software de-bugger so that breakpoints can be "planted" on1-byte instructions without overwriting, even tem-porarily, the next instruction. And finally an inter-rupt return instruction is provided which pops andrestores the saved flag settings in addition to per-forming the normal subroutine return function.

Single step. When the TF flag register is set, theprocessor generates an interrupt after the execu-tion of each instruction. During interrupt transfersequences caused by any type of interrupt, the TFflag is cleared after the push-flags step of the inter-rupt sequence. No instructions are provided forsetting or clearing TF directly. Rather, the flagregister file image saved on the stack by a previousinterrupt operation must be modified so that thesubsequent interrupt return operation restores TFset. This allows a diagnostic task to single-stepthrough a task under test, while still executingnormally itself.

External processor synchronization. Instructionsare included that permit the 8086 to utilize anexternal processor to perform any specialized oper-

25

ations (e.g., exponentiation) not implemented onthe 8086. Consideration was given to the ability toperform the specialized operations either via theexternal processor or through software routines,without having to recompile the code.The external processor would have the ability

to monitor the 8086 bus and constantly be awareof the current instruction being executed. In par-ticular, the external processor could detect thespecial instruction ESCAPE, and then perform thenecessary actions. In order for the external pro-cessor to know the 20-bit address of the operandfor the instruction, the 8086 will react to the ESCAPEinstruction by performing a read (but ignoring theresult) from the operand address specified, therebyplacing the address on the bus for the externalprocessor to see. Before doing such a dummy read,the 8086 will have to wait for the external proces-sor to be ready. The "test" pin on the 8086 pro-cessor is used to provide this synchronization. The8086 instruction WAIT accomplishes the wait.

If the external processor is not available, thespecialized operations could be performed by soft-ware subroutines. To invoke the subroutines, aninterrupt-generating instruction would be executed.The subroutine needs to be passed the specificspecialized-operation opcode and address of theoperand. This information would be contained inan in-line data byte(s) following the interrupt-generating instruction.

rSYSTEMS/SOiWAREENGINEER

Determine software/hardware tradeoffs for design optimization of realtime micro/mini based systems.Design and develop software opera-ting systems for specific products.BSEE required with MS in computersciences desirable. 5 to 12 years ofapplicable experience, with somemanagement and supervisory experi-ence is required.

Send resume and salaryrequirements to:

Attention A. KnudsenManager Development Engineering

ANACONDA COMPANYI/C ENGINEERING3221 S. La Cienega Blvd.

L.A., Calif. 90016Equal Opportunity Employer MIF

I

The same number of bytes are required to issuea specialized operation instruction to the externalprocessor or to invoke the software subroutines.Thus, the compiler could generate object code thatcould be used either way. The actual determinationof which way the specialized operations were car-ried out could be made at load time and the objectcode modified by the loader accordingly.

Sharing resources with parallel processors. Inmultiple-processor systems with shared resourcesit is necessary to provide mechanisms to enforcecontrolled access to those resources. Such mecha-nisms, while generally provided through softwareoperating systems, require hardware assistance. Asufficient mechanism for accomplishing this is alocked exchange (also known as test-and-set-lock).The 8086 provides a special 1-byte prefix which

may precede any instruction. This prefix causesthe processor to assert its bus-lock signal for theduration of the operation caused by the instruc-tion. It is assumed that external hardware, uponreceipt of that signal, will prohibit bus access forother bus masters during the period of its assertion.The instruction most useful in this context is an

exchange register with memory. A simple softwarelock may be implemented with the following codesequences:

Check:MOVLOCK XCHGTESTJNZ

MOV

AL,1 ;set AL to 1 (implies locked)Sema,AL ;test and set lockAL,AL ;set flags based on ALCheck ;retry if lock already set

;critical region

Sema,0 ;clear the lock when done

Conclusion

The Intel 8086 microprocessor architecture wasdesigned to meet the requirements of a broad classof new microprocessor applications. Its symmetricoperational organization will allow the efficientimplementation of software systems, especiallythose written in higher-level languages. The arith-metic, logical, byte-string, and bit operationssupport the common computational needs of micro-processor applications. The ability to support re-entrant code, position-independent code, anddynamically relocatable programs will allow reason-able operating system implementations in largerapplications, while the large address space supportsthose applications' memory requirements. Otheraspects of the architecture make feasible veryefficient smaller applications, where the perform-ance the 8086 offers is often crucial. As an evolutionof the popular 8080 processor, the 8086 presentsthe most advanced microprocessor capabilitiesavailable today. *

COMPUTER

Acknowledgments

The 8086 could never have been realized withoutthe work of a skilled device design team. Theinternal layout, logic design, and circuit were doneby Jim McKevitt, John Bayliss, Kit Ng, and PeterStoll. Much to their credit, functional 8086's wereavailable within a month of the date predictedalmost two years earlier.The architecture design itself was greatly aided

by the extensive analysis of Bruce MacLennan,and many hours of discussions with Bill Brown,Kevin Kahn, and Dean Schulz.

Reference

1. B. Jeffrey Katz, Stephen P. Morse, William B. Pohl-man, and Bruce W. Ravenel, "8086 MicrocomputerBridges the Gap Between 8- and 16-Bit Designs,"Electronics, February 16, 1978, pp. 99-104.

Stephen P. Morse has been with IntelCorporation since 1975, where he wasresponsible for the architectural defin-ition of the 8086 processor. Prior tojoining Intel he had over eight yearsof industrial experience with GeneralElectric Corporate Research and Devel-opment, Compagnie Internationalepour l'Informatique in France, IBMWatson Research Center, and Bell

Telephone Labs. He has been involved in such areas asmicroprocessor software systems, language and compilerdesign, and computer graphics and has held teachingpositions at Stanford University, University of Californiaat Berkeley, State University of New York at Albany,Pratt University, and City College of New York.A member of the ACM, Morse received his PhD from

New York University in 1967.

l William B. Pohlman is programmanager for mid-range microproces-sors at Intel Corporation. His tech-nical interests include computer archi-tecture, VLSI structures and imple-mentation techniques, and multi-_microprocessor systems. Before joiningIntel in 1975, he was responsible forthe LSI-11 chip set development at

l.~v |/.h Western Digital Corporation.Pohhman received his BSEE from California State

University at Northridge in 1966, and his MSEE fromthe University of Southern California in 1969. He is amember of the ACM and the IEEE.

'?Bruce W. Ravenel is president ofLanguage Resources, a San Franciscofirm which supplies Pascal compilersand other high-level language systemproducts. Previously a microprocessor

_i architect and senior software engineer_ - atIrsi Corporation, he played key_roles ithe design of the 8086 and its

support software system. Before join-_ig Intel in 1976, Ravenel was at the

University of Colorado doing research in the area ofsoftware portability and portable compiler design. He isa member of the ACM and the IEEE Computer Society.

Hardware /Fimware / SoftwareENGINEERS

"Any Goal That Can BeOperationalized Can Be Achieved"

Career development requires careful planning. If you are con-sidering career alternatives, Winter, Wyman and Companycan be your first step in reaching for new goals, new challenges,new environments, new levels of responsibility and newrewards. Now or in the future.Winter, Wyman is a full service Employment Consulting firmwell equipped to specialize in the placement of computer profes-sionals. Our business and reputation is built upon trust, capabilityand high standards of professional practice. This reputationallows us to maintain excellent working relationships with a verybroad range of clients in the computer industry, including com-puter vendors, users, peripheral manufacturers, system houses,software houses, engineering and research firms.Even if you are not considering an immediate job change, yourplanning begins now. The following is only a partial listing ofpositions for which we are seeking qualified applicants.

Software DevelopmentMGR. SOFTWARE DEVELOPMENT To 45KDirect total advanced software effort for growing computersystems vendor.

SOFTWARE PROJECT MGRS. To 32KSeveral positions tor Cobol, Fortran, PI/I, ALGOL, PASCAL,JOVIAL and RPG compiler designers.SOFTWARE PROJECT LEADERS (2) To 30KData General Systs. House. Req. extensive knldg. ot DGECLIPSE, RDOS, IDEA. Dev. Bus./Mtg. systs.SR. SYSTEMS PROGRAMMERS-DBMS (5) To 30KData Base software toolsmiths. Devi. transaction processingmonitor, schema editor, query language.SYSTEMS PROGRAMMERS (Several) To 28KMainframe/mini OS devl.: micro-prog: data comm./network-ing. Real-time assem. lang. prog.DIAGNOSTIC PROGRAMMERS To 28KDsgn./devl./debug diag. programs, test software. Heavyassem lang and mini OS exp on DEC, Data General, Prime, GA,Interdata equip. Microproc. exp.APPLICATIONS PROGRAMMERS To 25KReal-Time or On-Line Systs. util. micro/mini med systs.ASSEMBLY LANGUAGE AND FORTRAN. Knldg of RSX-1l,RT-11 RSTS, UNIX, RDOS, et.

Hardware/Firmware DevelopmentMANAGER, COMPUTER DESIGN To 35KMS/PHD in EE or CS. Knldg. CPU arch. I/0, component in-teg. High speed real time proc,MICROCOMPUTER HARDWAREIFIRMWARE OpenDESIGNERSBS/MSEE or CS with 2-5 yrs. dsgn. ot micro based products.Knldg. micro syst. archit., telecom.MICROPROCESSOR DESIGN ENGINEERS To 26KBS/MSEE with extensive CPU archit/sftwre exp., logic dsgn.simulation, prototyping.COMPUTER ARCHITECTS To 32KBS/MSEE 3-5 yrs. exp. spec. devi mini systs. Fam. with ad-vanced microprog. CPU archit. Have major impact in the devl.of new family of computer systs.LOGIC pESIGN ENGINEERS To 24KBSEE 3 yrs. dsgn. exp in periph device controllers/interfaces.Mini or micro interface dsgn. important. Floppy disc, PDP-l1,NOVA and 8080 exp.MGR. HARDWARE DEVELOPMENT/PRODUCT To 36KPLANNINGBSEE, MBA desirable. Computer mtg. seeks strong tech.mgr. to oversee product evaluation, planning and release.

If qualified you are invited to call or send resume In comrpiete confidence. All responses will be acknowledged.

Contact:Mr. James P. Masciarell

Manager Data Processing Placement

60 William St.Wellesley, Mass. 02181Phone (617) 235.8505

I&I

June 1978