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Testing Receiver Jitter Tolerance 1

Trends in Signal IntegrityJanuary 27, 2006

Trends in Signal Integrity Test

Testing a Receiver’s Jitter Tolerance

Thorsten GoetzelmannMichael ReserAgilent TechnologiesHigh Speed Digital Test

March, 2008

Trends in Signal IntegrityJanuary 27, 2006Page 2

Agenda

• Trend and Challenges Testing High-Speed Serial Technologies• Trends in High-Speed Serial Markets• New Challenges for Designers• Physical Layer Test Challenges

• Receiver Tolerance Testing• What do Standards require• The Importance of the Receiver• How to implement Jitter Emulation

• Summary



Why is RX Tolerance becoming more important at higher data rates

What has a field goal try to do with RX Tolerance Testing??

It seems to be quite realistic to score a try from the 5 yard line

What about a field goal try from the 50 yard line?

As the bit period of a signal is getting smaller at higher data rates, the precision of a bit transition needs to be significantly higher (less jitter) in order to ensure error free operation of a communication system


Why is RX Tolerance becoming more important at higher data rates

What is changing when moving to higher data rates:

• the jitter budgets are getting significantly smaller

• jitter effects are becoming more and more relevant (e.g. power supply noise, cross-talk effects,..) at higher data rates

• new effects like Inter-Symbol Interference (ISI) due to imperfect transmission channels are causing significant eye closure

Based on those effects, it is becoming increasingly important to understand the limits of a receiver’s performance – even under worst case conditions.



Trends in the computing and communication environment

Serial busses are becoming mainstreamAs data rates go to 3, 5, and 6 Gb/s and beyond, technical challenges are increasing disproportionately.• PCI Express at 2.5 going to 5 Gb/s• SATA/SAS at 1.5, moves to 3 and 6 Gb/s• Front-side Bus technologies move to 4.8 & 6.4Gb/s• CEI defining tests for 6 and 11 Gb/s• External communications for computers:

– Various Ethernet standards emerging at 10 Gb/s, approaching 100Gb/s

– Fibre Channel applications are running at 8.5Gb/s moving towards17 Gb/s


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d (G

b/s)

Computing/Consumer Enterprise Public Network

0.1

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LAN

Hot technologies

Peri p

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A/DSa

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High Speed Market Segments & Technologies

5

HT1

QPHT3

DDR3DDR4

FB1

BoB

DDR4d

HT2

SATA1PCIe1

PCIe2

SATA2SAS1

SAS2SATA3

HDMIDP

10GbE

1GbE

10GFC8GFC

2GFC

4GFC

CEI 6G

CEI 11G

GPON

EPON

SONET-OC3

SONET-OC12

SONET-OC48

SONET-OC192

SONET-OC768

PCIe3

FSB

CEI 25G16GFC

Evolving technologies



Physical layer testing trends

Many players/vendors: Tests and specs designed to maximize interoperability

Volume production: Avoid high-speed test by minimizing sensitivity to manufacturing variations

• Heavy burden on R&D to get it right• Expertise on the entire system (TX/Channel/RX)• Design change in one area must be validated

versus others• Typical digital engineer toolbox running out of steam• Required Jitter tests are time consuming and complex


The new communications system

A bus is now to be viewed as a communications system even though spans are measured in inches or centimeters

RX latch

CDR

RX PLL

ChannelTX latch

TX PLL

ReferenceClock

Transmitter (TX) Receiver (RX)Channel (CH)

Clock (C)



RX latch

CDR

RX PLL

ChannelTX latch

TX PLL

ReferenceClock


Clock (C)

Low-cost channels become lossy and dispersive

A Channel requires accurate

characterization for impedance and

transmission characteristics

including equalization and

interactions with TX and RX

TDR and VNA measurements can be used to characterize the channelTDR and VNA measurements can be used to characterize the channel


Transmitters must compensate for low-cost cables and boards

Pre-emphasized signal analysis

(optimized signals to compensate channel

performance), precision waveform characterization for

compliance

Tools available today for complete solutionTools available today for complete solution

RX latch

CDR

RX PLL

ChannelTX latch

TX PLL

ReferenceClock


Clock (C)



Receivers must tolerate degraded signals

Precisely “impaired data streams” are required to verify

receiver robustness. Calibrated composition of various types of jitter (RJ, PJ, BUJ, ISI, SI)

is required to generate real-world stress

BERTs are offering complete Jitter Tolerance Test capabilities in one box.Opportunity to reduce complexity and automate testing.

BERTs are offering complete Jitter Tolerance Test capabilities in one box.Opportunity to reduce complexity and automate testing.

RX latch

CDR

RX PLL

ChannelTX latch

TX PLL

ReferenceClock


Clock (C)


Systems must tolerate low-cost clock sources

Phase noise analysis complements jitter analysis for clock characterization.

Jitter Transfer measurements can provide insight into

the device’s behavior

21st harmonicSSC fundamental

This used to be a quite difficult measurement task – new measurements using Phase Noise techniques allow critical insight into a PLLs performance

This used to be a quite difficult measurement task – new measurements using Phase Noise techniques allow critical insight into a PLLs performance

RX latch

CDR

RX PLL

ChannelTX latch

TX PLL

ReferenceClock


Clock (C)



Emerging test requirementsWhat is needed:• Ability to easily analyze all aspects of the Tx/Ch/Rx/RefClk and treat them

as a complete communications system, rather than individual components.

• Tools and techniques (training sequences,…) to bring devices into certain test or operation modes as otherwise testing will not be possible

• Efficiency – provide the right toolset to get to fast and accurate test results despite the overall complexity of Signal Integrity and the Jitter topic.

• Ease of use - let engineers focus on analyzing their designs rather than learning how to use test equipment.

• Confidence in measurement results - repeatability from one test system to the next.

• Accurate, complete & affordable measurement capabilities.


Agenda



• Summary



The most neglected topic: the RX inputWhere to use the BERT?

RX TX

core

Device under Test

DUT

In Out

TX Test:

Stimulate with any Pattern Generator or built-in BIST

Measure with Scope (real-time, sampling), BERT Analyzer

RX TX

Loop-back

Device under Test

DUT

In Out

RX Test:

Stimulate with BERT Generator (any generator with jitter capabilities)

Analyze with BERT Analyzer


RX Specification

TRX_MIN_PULSE

RJ

DJ

Jitter / UI

FrequencyCDR cut-off

1st: Compliance Eye

2nd: Jitter Tolerance Curve

3rd: Dynamic Voltage Range



Rx Spec: Compliance Eye Diagram

Mix of jitter

1 UI

Mix of jitter


RX Spec: Jitter Tolerance Mask

In-band jitter

PLL/CDR follows

-> no big issue

Out-band jitter

Beyond PLL/CDR bandwidth, causes eye closure

-> CRITICAL

Cut-off at fdata / 1667

Limited UI at low freq



RX Spec: Dynamic Voltage Range

TRX_MIN_PULSE

• Min. Pulse Width• Min. Pulse Amplitude• Amplitude Ratio


RX Tolerance Test Setup; PCI Express Gen 2



Accurate Jitter Injection capabilitiesbuilt-in & calibrated

Jitter Tolerance Test Setup & Jitter Components

SJ

ISI

RJ

BUJ

PJ

With N4903A J-BERT


Sinusoidal (SJ) & Periodic (PJ) Jitter

Ideal clock:

Jittered clock:

)2sin( tfcπ

( ))2sin(2sin 101

34 tftf cc πππ +

)2sin(101

34 tfcππJitter:

UI32

Accurately solved by…



Random Jitter: the Gaussian Distribution

time

mean value

sigmaNormalized Events sigma

General:

# events = n x σ (sigma)

Random Jitter: n(BER) x s

n # events BER

---------------------------

2 67% 0.33

4 97% 0.03

6 99.7% 0.003

9.8 106 10-6

12.2 109 10-9

14.1 1012 10-12

sigmasigma



BUJ: the bounded Distribution

time

Normalized Events

bounded

• BUJ is sometimes also called ‘bounded RJ’• Depending on PRBS polynomial, filter frequency and PRBSgeneration rate, other Jitter Histograms can be created (overlaying events, sometimes mathematically hard to describe)




Duty Cycle Distortion (DCD)

Single ended Signals

Differential Signal

Offset causes DCDIdeal Signal DCD Signal



Inter-Symbol Interference (ISI)

C

R

Loss

1 2 2

2: 0 -> 1 transition1: 1-> 0 transition

1

3 3

3: 1 UI pulse




Common and Differential Mode Noise

Differential Signals

Edge Modulation Level

Modulation

Differential Mode Noise

Common Mode Noise



Agenda



• Summary



•

Leading pulse, pattern, data and clock generation

for digital design

Infiniium oscilloscopes and DCA-J

Pulse Data Generator

Generation

AnalysisSerial BERTs, ParBERT

Pattern generator and error detector with

jitter sourcesand BER, jitter and

eye analysis

High performance realtime scopes and wide bandwidth oscilloscope

with jitter analysis

Design VerificationBoards, general purpose

Device Characterization:Transceiver, MUX, SERDES, backplanes

Agilent’s Jitter solution portfolio

Agilent Technologies is the premier supplier for Physical Layer Test toolsAgilent Technologies is the premier supplier for Physical Layer Test tools


Summary• As data rates go to 5 Gb/s and beyond, jitter measurements are

getting more and more complex

• Agilent provides industry-leading test solutions for each of the critical jitter measurement tasks > RX/TX/Channel/RefClk

• The N4903A J-BERT addresses the complexities of calibrated jitter injection and automated RX jitter characterization

• For additional information:• www.agilent.com/find/jitter Agilent Jitter Solutions• www.agilent.com/find/jitter_info Jitter Application Information• www.agilent.com/find/sigint Other Agilent Jitter eSeminars• www.agilent.com/find/J-BERT N4903A product page• www.agilent.com/find/DCAJ 86100C product page• www.agilent.com/find/Infiniium DSO 90000 product page

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