team smash
DESCRIPTION
TEAM SMASH. The Pipelined Megacessor. Architectural View. Top Level Design Pipeline Stages Instruction Fetch Instruction Decode Execution Data Memory Register Write-back. Top-Level View. Instruction Fetch Stage. Instruction Decode Stage. Execution Stage. Memory Stage. - PowerPoint PPT PresentationTRANSCRIPT
TEAM SMASHThe Pipelined
Megacessor
Architectural View
Top Level Design Pipeline Stages
Instruction Fetch Instruction Decode Execution Data Memory Register Write-back
Top-Level View
Instruction Fetch Stage
Instruction Decode Stage
Execution Stage
Memory Stage
Write Back Stage
High-Level Components
Talk about connection between high level components
Highlight our idea of the pipeline, branch predictor and memory hierarchy
Debug Components
Seven Segment Display LCD Display Pipeline value switch Clock Divider
LCD Display
Significance of Pipeline
Increase instruction throughput
Branch Predictor
Explain the hardware involved
Significance of Branch Predictor
Predict what the next PC address will be. Keeps the pipeline flowing
Our implementation – Always not taken As suggested by Instructors Simple approach but similar idea to more
complex solution
Significance of Memory Hierarchy
Registers only 32 but very fast
Cache stores data from most frequently used main
memory
Memory
Assembler
PYTHON!!!! The dictionary data structure regDict – register encoding dataAddyDict – Data Label Address branchAddyDict – Branch Label Address
Assembler
readData() 2 Passes
Create dictionary of label-address mappings Encode all data and output to mif
readText() 2 Passes
Create BranchAddyDict Encode all instructions using dictionaries
Assembly Code
Matrix Multiplier! Snake it the size and two matrices Multiply! Wam bam output the diagonal
Teamwork
What we learned
From course, project and other people
ALSO WE ARE FREE TO TALK ABOUT WHATEVER WE WANT!!!
I say we discuss the renegades of funk and how they contributed to our success!