systems overview computer is composed of three main components: cpu main memory io devices refers to...

Systems OverviewSystems Overview

Computer is composed of three main components:

• CPU

• Main memory

• IO devices

Refers to page 48-51 2

Memory width and Memory width and lengthlength

Memory width: Number of bits stored in each memory register (dictated by width of system bus).

Memory length: Number of registers.

Refers to page 64 3

Width

Length

2width = max length

One Bit (One Shot) One Bit (One Shot) StorageStorage

AND-gate

Refers to page 118 4

01 1

01

01

Better One Bit StorageBetter One Bit Storage

Latch

• Multiple implementations available (S-R, J-K, D, T, 2NOR)

• Q can be set, cleared, and remember in-between


S

R Q

Q’

Qt S R Qt+1

0 0 0 0

0 0 1 0

0 1 0 1

1 0 0 1

1 1 0 1

1 0 1 0

Types of MemoryTypes of Memory

Memory Type

Access Speed

Read/Write/Rewrite

DRAM 50ns Yes - Read and Write many times

SRAM 10ns Yes - Read and Write many times

ROM Write Once

PROM Write Once

EPROM 150ns UV erasable PROM (UV window)

EEPROM Electrically erasable PROM (high voltage)

FLASH Reprogrammable, non-volatile


Static Memory (SRAM)Static Memory (SRAM)

• Lots of Flip-Flops

• Fast (<10ns read cycles)

• Expensive (only used in fast cache)

• Often “byte-wide” – read one byte at a time

• Frequency division


Frequency DivisionFrequency Division


Three positive-edge triggered T (toggle) Flip-Flops

1

Clock

Clock

f/2

f/4

1 1

Dynamic Memory (DRAM)Dynamic Memory (DRAM)AdvantagesAdvantages

• Single bit storage is a FET and a ~20fF capacitor

• Equivalent storage of SRAM in ¼ area.

• Read speeds of 5-50ns


Dynamic Memory (DRAM)Dynamic Memory (DRAM)DisadvantagesDisadvantages

• “Leaky” – loses data unless refreshed (100x a second).

• Read speeds of 5-50ns….but “rest” period means average read speed of 100ns (10 million reads a second).

• Recovery period needed for bit lines, a delay known as cycle time.


One Bit DRAMOne Bit DRAM


Word line acts like electrical switch

Bit line writes byte

Capacitor stores last written bit

One Bit DRAM WriteOne Bit DRAM Write


1. Close switch to specify what bit

2. Write “1”

1

3. Open switch to store bit

One Bit DRAM ReadOne Bit DRAM Read


1. Close switch to specify what bit

2. Read bit (in this case, 1)

1

DRAM ArrayDRAM Array


Word Line 1

Word Line 2

Bit Line 1 Bit Line 2

DRAM Array One Bit ReadDRAM Array One Bit Read


1. Pick this bit to read.12. Close Word Line 2 Switch(Row Address Select)

3. Read Bit Line 2(Column Address Select)

DRAM Array Row RefreshDRAM Array Row Refresh


1. Close Word Line 2 Switch

2. Read all bits to memory...and 3. amplify and rewrite back to appropriate bits.

Dynamic Memory (DRAM)Dynamic Memory (DRAM)Techniques/ImprovementTechniques/Improvement

ss• Interleave read operations – read from “even”

bank, then “odd” bank, allowing recovery time to take place during read of opposing bank.

• EDO – Extended Data Output means 4 consecutive column reads for each row address select.

• SDRAM- Synchronous burst (only send one address, then use on-chip CAS), self-refreshing, selectable burst lengths.


DRAM Physical PackageDRAM Physical Package(and the kitchen sink)(and the kitchen sink)

• SIMM – Single Inline Memory Module

• DIMM – Dual Inline Memory Module

• Small cards with 8-9 DRAM chips (if 9, it’s for parity checking)

• Available in 256MByte, 512Mbyte, 1GByte (and 2GByte)

• Each memory cell on each chip contains 8 bits so 8x8=64 bits read every 10ns. Pentium 64 bus can use 16bits each transfer, so each 16bit instruction available every 10/4ns.

• Voltage used on chips is falling from logic 5V to 2.5V


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