System Integration and System Integration and PerformancePerformance

System BusSystem Bus

Connects the CPU with main memory Connects the CPU with main memory and other system components.and other system components.

Each bus line can carry a single bit Each bus line can carry a single bit value during any bus transfer value during any bus transfer operation.operation.

Computer systems have Computer systems have THEE subsetsTHEE subsets of bus lines to carry specific types of of bus lines to carry specific types of information.information. The data busThe data bus The address busThe address bus The control busThe control bus

Data busData bus moves data among moves data among computer system components. The computer system components. The number of lines is the same as the number of lines is the same as the CPU word size.CPU word size.

Address busAddress bus carries the bits of a carries the bits of a memory address. memory address.

Control busControl bus carries commands, carries commands, command responses, status codes, command responses, status codes, and similar messages. and similar messages.

Bus ClockBus Clock

Timing reference for all attached devices.Timing reference for all attached devices. The frequency of bus clock pulses is The frequency of bus clock pulses is

measured in measured in megahertz. megahertz. Each clock pulse marks the start of a new Each clock pulse marks the start of a new

opportunity to transmit data.opportunity to transmit data. The time interval from one clock pulse to The time interval from one clock pulse to

the next is called the next is called bus cyclebus cycle. . Bus cycle can’t be shorter than the time Bus cycle can’t be shorter than the time

required for an electrical signal to required for an electrical signal to traverse the bus from end to end. traverse the bus from end to end.

Data Transfer Data Transfer RateRate Rate at which data is transmitted through a Rate at which data is transmitted through a

medium or communication channel.medium or communication channel.bus capacity = data transfer unit * clock ratebus capacity = data transfer unit * clock rate

= 64 bits * 100 MHz= 64 bits * 100 MHz

= 8 bytes * 100,000,000 Hz= 8 bytes * 100,000,000 Hz

= 800,000,000 bytes per second= 800,000,000 bytes per second

two ways to increase the maximum bus datatwo ways to increase the maximum bus data

transfer rate: transfer rate:

- increase clock rate- increase clock rate

- increase the data transfer unit size- increase the data transfer unit size

Bus ProtocolBus Protocol Governs the format, content, and timing of Governs the format, content, and timing of

data, memory addresses, and control data, memory addresses, and control messages sent across the bus. messages sent across the bus.

Efficient bus protocol consumes a minimal Efficient bus protocol consumes a minimal number of bus cycles, maximize bus for data number of bus cycles, maximize bus for data transfers. But it is complex, increase the transfers. But it is complex, increase the complexity and cost of the bus and all complexity and cost of the bus and all devices. devices.

Prevents devices from interfering with one Prevents devices from interfering with one another. another.

A multiple master bus or DMA gives devices A multiple master bus or DMA gives devices other than the CPU control of the bus, other than the CPU control of the bus, resulting in improved computer system resulting in improved computer system performance. performance.

Logical and Physical Logical and Physical AccessAccess CPU communicates with devices through I/O CPU communicates with devices through I/O

ports. To simplify the bus and the CPU ports. To simplify the bus and the CPU instruction set, interaction with all devices is instruction set, interaction with all devices is implemented with simple data movement implemented with simple data movement instructions. CPU treats each device as if it is instructions. CPU treats each device as if it is a storage device with a linear address space.a storage device with a linear address space.

The device controller must translate access The device controller must translate access commands to the linear address space into commands to the linear address space into whatever physical actions are necessary to whatever physical actions are necessary to perform the access. perform the access.

Device ControllersDevice Controllers

Perform a number of functions:Perform a number of functions: - Implement the bus interface and access - Implement the bus interface and access

protocolsprotocolsDevice controllers monitor the bus control Device controllers monitor the bus control lines for signals to devices and translate those lines for signals to devices and translate those signals into appropriate commands to the signals into appropriate commands to the storage or I/O device. Similarly, data and storage or I/O device. Similarly, data and status signals from the device are translated status signals from the device are translated into appropriate control and data signals. A into appropriate control and data signals. A controller implements all bus interface controller implements all bus interface functions for its attached device. functions for its attached device.

- Translate logical access into physical access.- Translate logical access into physical access.Device controllers know the physical details of Device controllers know the physical details of the attached devices and issue specific the attached devices and issue specific instructions to the device based on that instructions to the device based on that knowledge. knowledge.

E.g the device controller converts a logical E.g the device controller converts a logical access to a specific disk sector within a linear access to a specific disk sector within a linear address space into a command to read from a address space into a command to read from a specific head, track, and sector. specific head, track, and sector.

- Permit several devices to share access to a bus Permit several devices to share access to a bus connectionconnection

This function is important because the number of This function is important because the number of physical I/O ports on the system bus is limited. physical I/O ports on the system bus is limited. Computer systems have several storage and I/O Computer systems have several storage and I/O devices. Device controllers allow those devices to devices. Device controllers allow those devices to share a smaller number of bus connections. Most share a smaller number of bus connections. Most storage and I/O devices can’t sustain the system storage and I/O devices can’t sustain the system bus data transfer rate for extended periods. bus data transfer rate for extended periods. Sharing a single bus connection among multiple Sharing a single bus connection among multiple slower devices efficiently allocates the large slower devices efficiently allocates the large communication capacity of a bus connection to communication capacity of a bus connection to many lower-capacity devices. many lower-capacity devices.

Mainframe ChannelMainframe Channel

A channel is an advanced type used A channel is an advanced type used in mainframe computer. Channels in mainframe computer. Channels have greater data transfer capacity, have greater data transfer capacity, a larger maximum number of a larger maximum number of attached devices, and greater attached devices, and greater variability in the types of devices variability in the types of devices that can be controlled compared that can be controlled compared with device controllers. with device controllers.

InterruptsInterrupts

In a logical sense, an interrupt is a In a logical sense, an interrupt is a signal to the CPU that some event signal to the CPU that some event has occurred that requires the CPU has occurred that requires the CPU to execute a specific program or to execute a specific program or process. process.

In a physical sense, an interrupt is an In a physical sense, an interrupt is an electrical signal generated by a electrical signal generated by a device and then sent over the device and then sent over the control bus. control bus.

Register in the control unit that stores Register in the control unit that stores an interrupt code received over the bus an interrupt code received over the bus or generated by the central processing or generated by the central processing unit is called interrupt register.unit is called interrupt register.

At the conclusion of each execution At the conclusion of each execution cycle, the control unit checks the cycle, the control unit checks the interrupt register for a nonzero value. interrupt register for a nonzero value.

If one is present, the CPU suspends If one is present, the CPU suspends execution of the current process, reset execution of the current process, reset the interrupt register to zero, and the interrupt register to zero, and proceeds to process the interrupt. When proceeds to process the interrupt. When the interrupt has been processed, the the interrupt has been processed, the CPU resumes executing the suspended CPU resumes executing the suspended process.process.

Communication with devices through interrupts allows Communication with devices through interrupts allows the CPU to do something useful while it’s waiting for an the CPU to do something useful while it’s waiting for an interrupt. interrupt.

If the CPU is executing only a single process or program If the CPU is executing only a single process or program then there is no performance gain. If the CPU is sharing then there is no performance gain. If the CPU is sharing its processing cycles among many processes then the its processing cycles among many processes then the performance improvement can be substantial. performance improvement can be substantial.

When one process requests data from a device the CPU When one process requests data from a device the CPU suspends it and starts executing another process’s suspends it and starts executing another process’s instructions. When an interrupt is received, indicating instructions. When an interrupt is received, indicating that the access is complete, the CPU retrieves the data, that the access is complete, the CPU retrieves the data, suspends the process it currently is executing, and suspends the process it currently is executing, and returns to executing the process that requested the returns to executing the process that requested the data. data.

Interrupt HandlersInterrupt Handlers

To process each possible interrupt. To process each possible interrupt. Each interrupt handler is a Each interrupt handler is a

separate program stored in a separate program stored in a separate part of primary storage. separate part of primary storage.

In order to process an interrupt, In order to process an interrupt, the CPU must load the first the CPU must load the first instruction of the correct interrupt instruction of the correct interrupt handler for execution. handler for execution.

When the CPU detects an interrupt, it When the CPU detects an interrupt, it executes a master interrupt handler executes a master interrupt handler program called the supervisor. program called the supervisor.

The supervisor examines the The supervisor examines the interrupt code stored in the interrupt interrupt code stored in the interrupt register and uses it as an index to register and uses it as an index to the interrupt table. So the supervisor the interrupt table. So the supervisor extracts the corresponding memory extracts the corresponding memory address and transfers control to the address and transfers control to the interrupt handler at that address. interrupt handler at that address.

Multiple InterruptsMultiple Interrupts Classified three categories:Classified three categories:

– I/O eventI/O event – notify the OS that an access request – notify the OS that an access request has been processed and that data is ready for has been processed and that data is ready for transfer. transfer.

– Error conditionError condition - indicates errors that occur - indicates errors that occur during normal processing.during normal processing.

– Service requestService request – used by the application – used by the application programs to request OS services. An interrupt code programs to request OS services. An interrupt code is assigned to each service program, and an is assigned to each service program, and an application program requests a service by placing application program requests a service by placing the corresponding interrupt number in the interrupt the corresponding interrupt number in the interrupt register. The interrupt code is detected at the register. The interrupt code is detected at the conclusion of the execution cycle, the requesting conclusion of the execution cycle, the requesting process is suspended, and the service program is process is suspended, and the service program is executed. executed.

Buffers and CachesBuffers and Caches

A buffer is a small storage area A buffer is a small storage area used to hold data in transit from used to hold data in transit from one device to another. one device to another.

Buffers resolve differences in data Buffers resolve differences in data transfer rate or data transfer unit transfer rate or data transfer unit size. size.

A cache is a storage area to A cache is a storage area to improve the system performance.improve the system performance.

However a cache differs from a buffer in However a cache differs from a buffer in several important ways including:several important ways including:

- data content is not automatically removed - data content is not automatically removed as it is used.as it is used.

- used for bi-directional data transfer- used for bi-directional data transfer

- used only for storage devices accesses- used only for storage devices accesses

- larger than buffer- larger than buffer

- cache content must be managed intelligently- cache content must be managed intelligently When used for input, a cache gives more When used for input, a cache gives more

rapid access if the data being requested rapid access if the data being requested already is in the cache. The cache controller already is in the cache. The cache controller guesses what data the CPU will request next guesses what data the CPU will request next and loads that data into the cache before it and loads that data into the cache before it are requested. are requested.

The Performance of writing The Performance of writing to a cacheto a cache When the data is written to a cache, the When the data is written to a cache, the

confirmation signal is sent immediately to confirmation signal is sent immediately to sending device, before the data is written to the sending device, before the data is written to the storage device. storage device.

Sending a confirmation before data is written to Sending a confirmation before data is written to the secondary storage device can improve the secondary storage device can improve program performance. program performance.

Performance improves because the program Performance improves because the program immediately can proceed with other processing immediately can proceed with other processing tasks. tasks.

If the program is performing a series of write If the program is performing a series of write operations, performance improvements will cease operations, performance improvements will cease as soon as the cache is full. as soon as the cache is full.

The Performance of a cache during The Performance of a cache during readread operation operation

Read accesses first are routed to the cache. Read accesses first are routed to the cache. If the data is already in the cache then it is If the data is already in the cache then it is

accessed from the receiving device. accessed from the receiving device. Performance is improved because access to Performance is improved because access to

the cache is much faster than access to the the cache is much faster than access to the storage device. storage device.

If the requested data is not in the cache, If the requested data is not in the cache, then it must be read from the storage then it must be read from the storage device. device.

A performance is realized only if requested A performance is realized only if requested data already is waiting in the cache. data already is waiting in the cache.

CompressionCompression

Reduces the number of bits used to Reduces the number of bits used to encode a set of related data items.encode a set of related data items.

A compression algorithm can be lossless A compression algorithm can be lossless or lossy. or lossy.

Lossless compression – the result of Lossless compression – the result of compressing and then decompressing compressing and then decompressing any data input is exactly the same as the any data input is exactly the same as the original input. It is required in many original input. It is required in many applications, e.g, accounting records, applications, e.g, accounting records, executable programs, and most stored executable programs, and most stored documents. documents.

Lossy compression – the result of Lossy compression – the result of compressing and then compressing and then decompressing a data input is decompressing a data input is different to the original input. different to the original input.

It is applied in audio and video data. It is applied in audio and video data. Decompression algorithm – restore Decompression algorithm – restore

compressed data to its original state. compressed data to its original state. Data compression requires increased Data compression requires increased

processing resources to implement processing resources to implement the compression and decompression the compression and decompression algorithms while reducing resources algorithms while reducing resources needed for data storage and needed for data storage and communication. communication.

Compression is used to reduce Compression is used to reduce secondary storage requirements. secondary storage requirements.

Data sent to the storage device is Data sent to the storage device is compressed before it’s written. compressed before it’s written.

Data read from storage is Data read from storage is decompressed before it’s sent to the decompressed before it’s sent to the requester. requester.

Data is compressed as it enters the Data is compressed as it enters the channel and then decompressed as channel and then decompressed as it leaves the channel. it leaves the channel.