A Wafer-Level Defect Screening Technique A Wafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for to Reduce Test and Packaging Costs for

“Big-D/Small-A” Mixed-Signal SoCs“Big-D/Small-A” Mixed-Signal SoCs

Sudarshan Bahukudumbi Sudarshan Bahukudumbi

Sule Ozev Sule Ozev

Krishnendu Chakrabarty Krishnendu Chakrabarty

Vikram IyengarVikram Iyengar

Published in January of 2007Published in January of 2007Presented by Vonn HolyoakPresented by Vonn Holyoak

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References

Function of paper

Testing at Packaged Level

Testing at Wafer Level

Compare the effects of differentmethods of testing a mixedsignal SoC (system on chip).

Develop an improved model for testing SocsAt the wafer level

Evaluate the method by use of a cost model

Consumer ElectronicsConsumer Electronics– Low profit marginsLow profit margins– High packaging costsHigh packaging costs

Packaging Costs vary directly with Packaging Costs vary directly with number of pinsnumber of pins

Packaging of faulty dies (IC at wafer level) Packaging of faulty dies (IC at wafer level) is a major cost concernis a major cost concern

Why important

Wafer Level DifficultiesWafer Level Difficulties

Measurement inaccuraciesMeasurement inaccuracies– Analog cores tested on digital signal Analog cores tested on digital signal

processorsprocessors

Noisy DC Power supplyNoisy DC Power supply

Improper Grounding of wafer probeImproper Grounding of wafer probe

Lack of proper noise shielding of wafer probeLack of proper noise shielding of wafer probe

Lead to high YIELD LOSS and TEST ESCAPE!

ParametersParametersM = # of batch of identical cores under testM = # of batch of identical cores under testI = # of core under testI = # of core under testP = # of points of Fast Fourier TransformP = # of points of Fast Fourier Transformxxi i = response of each data point= response of each data pointXXii = Characteristic Spectrum of core under test = Characteristic Spectrum of core under test E = Eigen SignatureE = Eigen SignatureY% = Expected YieldY% = Expected YieldK = Constant based on analysis usedK = Constant based on analysis usedTT+ + = the event that the test passes= the event that the test passesTT- - = the event that the test fails= the event that the test failsDD+ + = the die is fault free= the die is fault freeDD- - = the die is defective= the die is defectiveP(TP(T+ + l Dl D--) = Probability of test pass for faulty die) = Probability of test pass for faulty dieP(TP(T- - l Dl D++) = Probability of test fail for good die) = Probability of test fail for good dieN = Total # of dies producedN = Total # of dies producedttapap = Total test application time at production level = Total test application time at production levelccapap = Cost of test application during after package testing = Cost of test application during after package testingCCpp = Cost of packaging per unit die = Cost of packaging per unit dieAAdiedie = Area of the die under consideration = Area of the die under considerationCCsilsil = Cost of silicon per unit area of die = Cost of silicon per unit area of dieCCocapocap = Overall Production Cost = Overall Production Cost

CCococwapwap = Overall Cost with wafer level and after package testing = Overall Cost with wafer level and after package testing

δC = Difference in cost of production with and without wafer level testingδC = Difference in cost of production with and without wafer level testing

TestingTesting

Output response of a circuit is compared Output response of a circuit is compared to a signature responseto a signature response– Because of multiple error sources, a reliable Because of multiple error sources, a reliable

signature is difficult to derivesignature is difficult to derive

Spectral Analysis compares the response Spectral Analysis compares the response of many data pointsof many data points– Uses FFT (Fast Fourier Transform) to analyze Uses FFT (Fast Fourier Transform) to analyze

pointspoints– It is necessary to combine information into a It is necessary to combine information into a

single parametersingle parameter

Two MethodsTwo Methods

Mean-Signature-Based-Correlation (MSBC)Mean-Signature-Based-Correlation (MSBC)

Golden-Signature-Based-Correlation Golden-Signature-Based-Correlation (GSBC)(GSBC)

Mean-Signature-Based-Correlation Mean-Signature-Based-Correlation (MSBC)(MSBC)

Reference Spectum as SignatureReference Spectum as Signature

Averages of spectral of identical coresAverages of spectral of identical cores

Correlation Between the Reference Signature Correlation Between the Reference Signature and the Tested signature:and the Tested signature:

Golden-Signature-Based-Golden-Signature-Based-Correlation (GSBC)Correlation (GSBC)

In order not to have to store the data on In order not to have to store the data on order to acquire Mean-Based-Signatureorder to acquire Mean-Based-Signature

Signature is obtained a prioriSignature is obtained a priori– Assumes ideal operating conditionsAssumes ideal operating conditions

Same Correlation is used as before Same Correlation is used as before

Pass/Fail CriterionPass/Fail CriterionNumber of passing units estimated using Number of passing units estimated using

expected yield informationexpected yield information

ResultsResults

Cost ModelCost Model

N = Total # of dies producedN = Total # of dies producedttapap = Total test application time at production level = Total test application time at production level

ccapap = Cost of test application during after package testing = Cost of test application during after package testing

CCpp = Cost of packaging per unit die = Cost of packaging per unit die

AAdiedie = Area of the die under consideration = Area of the die under consideration

CCsilsil = Cost of silicon per unit area of die = Cost of silicon per unit area of die

CCocapocap = Overall Production Cost = Overall Production Cost

CCocwapocwap = Overall Cost with wafer level and after package testing = Overall Cost with wafer level and after package testing

δC = Difference in cost of production with and without wafer level testingδC = Difference in cost of production with and without wafer level testing

Applying the cost model

3 Typical die sizes were used

Values are given from published data

The more conservative values were used

Industry Yield Curve plotted to illustrate cost savings

ConclusionConclusion

Industrial use very practicalIndustrial use very practical

Technical AdvancementTechnical Advancement

Industries ImpactedIndustries Impacted– All manufacturers of mixed SoC chipsAll manufacturers of mixed SoC chips– All downstream industries benefit from cost All downstream industries benefit from cost

savingssavings