stgc trigger demonstrator
DESCRIPTION
sTGC Trigger Demonstrator ATLAS Israel Annual Meeting 3 0 December 2012 Lorne Levinson, Julia Narevicius, Alex Roich, Meir Shoa, Vladimir Smakhtin. sTGC trigger demonstrator. Demonstrate t rigger path only from chamber to Sector Logic input - PowerPoint PPT PresentationTRANSCRIPT
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L. Levinson, sTGC Trigger Demonstrator 1
sTGC Trigger Demonstrator
ATLAS Israel Annual Meeting30 December 2012
Lorne Levinson, Julia Narevicius,Alex Roich, Meir Shoa, Vladimir Smakhtin
30 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 230 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 3
sTGC trigger demonstratorDemonstrate trigger path only from chamber to Sector Logic input
• Not for studying detector properties and ultimate resolution:ToT is non-linear and saturates, probably not used for final ASD
• use cosmic rays
• BNL VMM1 ASD: 32 ASDs for strips, 12 for pads
• Strips: convert ToT to charge by measuring length of ToT with 1nsec sampling: – Emulates future “TDS” = Trigger Data Serializer ASIC– peak-to-time would be the same
flash ADC would deserialize with 5nsec /bit– Serial output at 6.25Gb/s
• Pads: Simple trigger: dual 3-out-of-4 coincidence logic
• Serial transmission of pad trigger data to TDS (but without BCID assignment)
• Centroid finding, centroid choosing, track vector calc
• Latency measurement30 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 4
Not demonstrated
• Because ToTs are saturated, no attempt to get precision centroids: • No Router, instead there is direct 6Gb/s link from TDS to centroid
finder via twinax cables• No readout of VMM
30 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 530 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 6
Pad over-lapping for 3-out-4 coincidence
• Shown above: pad overlap in a pair of layers• Three rows of 7 pads. Two rows of 8 pads• The second pair of layers in the multiplet is the same.• 37 pads per pair of layers
– Total 4x37 = 148 pads
• Trigger looks in 12ns windows (six 2ns samples): if 3 or more pads are non-zero, a trigger is generated
30 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 7
sTGC Trigger Demo-1 FPGA board
30 December, 2012
Power module
Trigger Data Serializer FPGA
16+12 ASD connectors
Pad trigger/ centroidFPGA
10G Quad fibre interface
10G twinax*4 connector
Ethernet readout
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L. Levinson, sTGC Trigger Demonstrator 8
Status• PCB boards being tested
– FPGAs correctly receives non-standard LVDS from VMM ASDs
• Firmware done, not tested, but much the same as for Demo-0
• Reassembling pad signal extraction and ASD adapter boards … there are both “left” and “right” VMM boards– Board to bring pad signals to edge of chamber for 2 or 3 rows of pads– Boards to adapt VMM ASDs to the strips on edge of chamber– Boards to adapt VMM ASDS to the board that extracts the pad signals
• We have 46 VMMs in Israel, 44 needed for full test
• Configuration system, HW and SW, being built for up to 48 ASDs
• Getting results for Milestone Meeting will be tight, depends on – no disasters with the PCB boards – understanding of 6.25Gb/sec serial links (deserializers)– We have backup parallel 6Gb/s links if problems with serial links
30 December, 2012
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L. Levinson, sTGC Trigger Demonstrator 9
Configuration of 12x4 VMM ASDs
30 December, 2012
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Latency sTGC
NSW Trigger, TDAQ Week Oct 2012 10
min(ns)
max(ns) Notes
TOF from interaction point to SW (10 m) 35 35Propagation delay in chamber 25 25ASD 10 10up- to down-stream package (50cm) 0 3delay for pad trigger & deskew 10 20 strips are pipelined until pad trigger arriveslatency for the last sample of the pulse 64 100 depends on shaping time; ToT is accumulated on the flyToTd: ToT to digital and zero suppression 20 30 uses a 10:1 deserializer to aggregate 1ns samplesOn chamber cabling (up to 4m) to Router 20 20 5 nsec/mToTD-to-Router ser/deserializer 5 10Router 5 10 switch Router to Centroid serializer/deserializer 40 70 GBT does not meet this limit. A different link must be used.fiber to Centroid card in USA15 90m 495 495 5.5nsec/mfind valid centroids and centroid averages 32.5 65 8 layers done in parallel, measured to be 13 clocksdifference of centroid averages 2.5 5calc sub-ROI pointed to at Big Wheel (LUT) 5 5 datasheet BRAM access time =2nsecresynch to BC clock driving output serializer 0 6.25 90° phase chosen to best match pipeline lengthcentroid to Sector Logic serializer 5 10 Total 774 919
L. Levinson
The table shows the latency from the interaction point, through the precision strip trigger logic for the Inner Layer to the Sector Logic in USA-15. We take as a model the Xilinx Virtex6. All times are estimates except that for the centroid finder which has been measured.
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L. Levinson, sTGC Trigger Demonstrator 11
The end
30 December, 2012