Status – Week Status – Week 228228

Victor MoyaVictor Moya

SummarySummary

Hierarchical Z-Buffer.Hierarchical Z-Buffer.

Hierarchical Z-BufferHierarchical Z-Buffer

Two Level Hierarchical Z-Buffer for Two Level Hierarchical Z-Buffer for 3D Graphics Hardware. Cheng-3D Graphics Hardware. Cheng-Hsien Chen, Chen-Yi Lee.Hsien Chen, Chen-Yi Lee.

System, Method and Apparatus for System, Method and Apparatus for Multi-Level Hierarchical Z Multi-Level Hierarchical Z Buffering. US Patent Application Buffering. US Patent Application 2003/0151606.2003/0151606.

Hierarchical Z-BufferHierarchical Z-Buffer

PA CLIP RAST INT PS FTEST

HZ HZ ZTEST

Hierarchical Z-BufferHierarchical Z-BufferHZ MEM

Z CACHE

DECODE

ENCODE

COMBINING CACHE

MEMORY(Z-BUFFER)

MERGELOGIC

Hierarchical BufferHierarchical Buffer

Model from ATI patent application.Model from ATI patent application. See also two other ATI patents about early See also two other ATI patents about early

implementations of the HZ.implementations of the HZ. Two level HZ.Two level HZ.

but only one used?but only one used? Early Z access is performed in two phases:Early Z access is performed in two phases:

access to the HZ L2.access to the HZ L2. if passes, access the Z cache.if passes, access the Z cache. if miss, access memory (fetch new Z cache if miss, access memory (fetch new Z cache

line).line).

Hierarchical Z-BufferHierarchical Z-Buffer

Z CacheZ Cache small lines? 32 bit per pixel, 4 pixels per small lines? 32 bit per pixel, 4 pixels per

line?line? data is compressed in the Z-Buffer.data is compressed in the Z-Buffer. decode/decompress at line fetch.decode/decompress at line fetch. encode/compress at line evict.encode/compress at line evict. compress mechanism is also used to compress mechanism is also used to

calculate the farthest Z value in the line.calculate the farthest Z value in the line. size?size? replacement policy?replacement policy?

Hierarchical Z-BufferHierarchical Z-Buffer

HZ MemoryHZ Memory each position stores the farthest Z value each position stores the farthest Z value

in a NxM tile of the original Z Buffer.in a NxM tile of the original Z Buffer. data precission? 8 bits? 16 bits? 32 bits?data precission? 8 bits? 16 bits? 32 bits? combine cache to build the tile farthest combine cache to build the tile farthest

value.value. number of HZ levels?number of HZ levels?

L1 on die, L2 on cache/memory.L1 on die, L2 on cache/memory.

Hierarchical Z-BufferHierarchical Z-Buffer

HZ memoryHZ memory combining cache size?combining cache size? replacement policy? FIFO?replacement policy? FIFO? update mechanismupdate mechanism

Hierarchical Z-BufferHierarchical Z-Buffer

HZ MemoryHZ Memory size?size?

Example:Example:– 8x8 tiles8x8 tiles– 8 bits per value8 bits per value– 2048x2048 resolution2048x2048 resolution– 64KB64KB– a second level can be implemented using a second level can be implemented using

pointers.pointers.– LARGE!LARGE!

Hierarchical Z-BufferHierarchical Z-Buffer

Bit-mask Cache HZ Buffer

Z write

Hierarchical Z-BufferHierarchical Z-Buffer

TMPZ

COVERAGEMASK

CO

VE

RA

GE

?

Hierarchical Z-BufferHierarchical Z-Buffer

Light weight Z-Buffer?Light weight Z-Buffer? HZ Buffer:HZ Buffer:

2 bit pointer (L2 HZ).2 bit pointer (L2 HZ). 4 x 8 bit Z values (L1 HZ).4 x 8 bit Z values (L1 HZ). ~49 KB for 1024x768.~49 KB for 1024x768.

HZ test per primitive.HZ test per primitive. HZ test per fragment.HZ test per fragment.

Hierarchical Z-BufferHierarchical Z-Buffer

Bit-mask cache:Bit-mask cache: builds HZ blocks.builds HZ blocks. holds the current farthest Z for the holds the current farthest Z for the

block.block. 1 bit per block pixel: covered.1 bit per block pixel: covered. FIFO replacing policy.FIFO replacing policy. if full block covered update HZ buffer.if full block covered update HZ buffer.

Hierarchical Z-BufferHierarchical Z-Buffer

access HZ

access Z Cache

cull

discard

passes

test

hit cull

pass

discard

pass

miss

Access memoryReplace

test

Hierarchical Z-BufferHierarchical Z-BufferTriangleTraversal

HierarchicalZ

Interpolatorfragment

test Z test?

ZCache

MemorController

HZ TEST BOXES

Hierarchical Z BufferHierarchical Z Buffer

Z testfragment fragment

Z cacheMemory

ControllerHierarchical

Z

Z TEST AND Z AND HZ UPDATE BOXES

Cache simulationCache simulation

c1 c2 c3 c4

box1

box2

acc1

acc1

res1acc2

acc2

res2

accc3

acc3

res3

Latency 2

Throughput 1

Box2 = cache

c5

Cache simulationCache simulation

c1 c2 c3 c4

box1 acc1 res1 res2

accc3

res3

c5

acc2

Latency 1 cycle

Throughput 1

Box1 => included cache

Cache simulationCache simulation

Use always 2+ cycle access Use always 2+ cycle access caches?caches?

Use always in-box caches?Use always in-box caches? Shared cache?Shared cache?